Current-Mode Ripple Control Boost Converter

In current-mode control, the controller tries to control the inductor current directly. The duty ratio of the switch is controlled indirectly. Among various types of current-mode control, the ripple control, also called hysteretic current-programmed control [39, 80], offers the tightest control over the inductor current and the fastest attainable response of the inductor current. The block diagram of the current-mode ripple control regulator

is shown in Fig. 5.25(a). The hysteretic comparator limits the inductor current within a hysteretic window ∆I. As shown in Fig. 5.25(b), the switch is turned off when the inductor current rises to the top threshold, Icmd+ ∆I/2. When the inductor current falls to the bottom threshold, the switch is turned on again. The current command, I_cmd, is generated by the error amplifier. Additional compensation network is required to improve frequency response and stability.

Much work has been done to analyze the small-signal dynamic response of the current-mode boost converter [6, 39, 46, 55, 80]. The derived small-signal transfer functions can be used to design the feedback compensation loop. The procedure of analysis is similar to that of a voltage-mode converter. However, the inductor current is now a control signal because it is tightly controlled by the current command. The duty ratio is no longer a control input and is substituted by other variables. It can be shown that the small-signal control-to-output transfer function of the current-mode ripple control boost converter is expressed as:

If we introduce the control-to-inductor-current gain, k, then:

G_eo = k × R_load× (1 − D) 2

An RHP zero still exists in the control-to-output transfer function. Refer to Eq. 5.40, the RHP zero expression is exactly the same as that for voltage-mode. Using current mode

I_L I_cmd

t_on t_off

T_S

I I^p-p t_D

t_D

Figure 5.26: Inductor current waveform in a current-mode ripple control regulator.

does not move this at all. The reason explained in the previous subsection still exists in current-mode control. No matter what kind of control law is employed, it takes time for the switch to increase the average inductor current. Therefore, the output voltage will decrease initially and then increase.

Even though the RHP zero does exit, the number of pole is reduced from two to one.

The inductor is virtually disappeared from the loop because the inductor current is directly controlled, which makes compensation easier. Compensation of the error amplifier and loop design will be discussed in the next subsection.

5.3.4 Circuit Design for Fixed Switching Frequency

Main concept of obtaining fixed switching frequency operation by inserting delay is the same as the voltage-mode ripple control buck regulator. Before going through detailed circuits design, switching frequency variation is first investigated.

Figure 5.26 shows the inductor current waveform in a current-mode ripple control regulator. During the on-time of the switch, ton, the inductor current ramps up with the

slope expressed in Eq. 5.20 which is represented by A and a:

dIL

dt (on) = VIN− (VDS + IL× RL)

L = A = a

L (5.42)

During the off-time, t_{of f}, the inductor current ramps down with the slope expressed in Eq. 5.22 which is represented by B and b:

dI_L

dt (of f ) = V_IN − (V_out+ V_d+ I_L× R_L)

L = −B = −b

L (5.43)

In a ripple control regulator, the fixed hysteresis band, ∆I, controls the AC current through the inductor. But the actual inductor current ripple, I_p−p, is larger than the hysteresis band, because of the delay, tD. The on-time current ripple, ∆I(on), is:

∆I_(on)= A ×

Neglecting losses, V_DS and I_L× r_L, the equation is simplified as below:

f_SW = V_IN× (V_out+ V_d− V_IN)

∆I × L × (V_out+ V_d) + t_D× (V_out+ V_d)² (5.49) In common condition, only V_IN, V_out, and t_D affect the switching frequency, because ∆I and L are seldom altered in a running system. Compared with the voltage-mode switching frequency in Eq. 5.2, the switching frequency of current mode is not a function of ESR and ESL of the output capacitor, because ESR and ESL only affect the output voltage.

Therefore, the switching frequency of the current-mode ripple control regulator is less disturbed by non-ideal factors. Figure 5.27 estimates the switching frequency variations against V_IN with different V_out. Parameters used are the followings: ∆I=0.2 A, L=8.2 µH, and t_D=150 ns. The switching frequency still varies significantly with output and input voltage. To improve this drawback, circuits for synchronizing current-mode ripple control boost regulators are proposed in this thesis.

Figure 5.28 shows the proposed control loop for the boost converter. Both the output voltage and the inductor current are sampled by the controller. The output voltage is sensed through a compensation network and then amplified by an error amplifier (EA).

In the ripple control regulator, the inductor current must be monitored during the whole switching cycle. Therefore, a small sensing resistor is placed in series with the inductor.

Then a current sense amplifier (CSA) amplifies the signal. A comparator with hysteresis is used to avoid false crossing detections caused by the noise and is an essential part to the ripple controller. Similar to the proposed voltage-mode ripple controller, a delay element is placed after the comparator. A negative feedback loop that uses a PFD is added to determine the accurate delay value which is directly proportional to VT H.

150

Figure 5.27: Frequency variations of the current-mode ripple control boost regulator.

V_out

Figure 5.28: Proposed frequency synchronized boost converter.

Figure 5.29: Type II error amplifier. (a)Configuration. (b)Gain and phase versus fre-quency characteristics

The compensation network used in the regulator is a type II error amplifier compen-sation [7]. Circuits and frequency responses are shown in Fig. 5.29. The locations of the zero and pole are:

fz = 1

2π × R₂× C₁ (5.50)

f_p = 1

2π × R₂× C₂ (5.51)

and mid-frequency voltage gain, A_V, is:

A_V = R2

R₁ (5.52)

A pole at the DC creates high gain at low frequencies. The gain is Z_C1/R₁. Thus, power line 120-Hz ripple is attenuated down to a very low level at the output. In the mid-frequency range where the impedance of C₁, Z_C1 is small compared to R₂ and ZC₂ is large compared to R₂, the gain slope is flat and equals to R₂/R₁. At higher frequencies where ZC2 is small compared to R2, the gain is ZC2/R1.

The type II error amplifier gains some phase boost in the frequency between the pole and zero. Therefore, the crossover frequency of total open-loop gain is usually placed here to obtain good phase margin. The farther apart fz and fp are, the greater the phase margin. However, if f_z is chosen too low, low-frequency gain will be lower at 120 Hz.

As a result, 120 Hz attenuation will be poorer. If f_p is chosen too high, gain at high frequencies is higher. Thus, high-frequency noise spikes would come through at higher amplitude. A compromise between good phase margin, better 120Hz attenuation, and lower high-frequency noise spike must be made.

The sequence of designing a loop is first to establish the crossover frequency, fc, where the total open-loop gain should be 0 dB. Then choose the error-amplifier gain so that the total open-loop gain is forced to be 0 dB at the frequency. Next, design the error-amplifier gain slope so that the total open-loop gain comes through fc at a -20 db/dec slope. Finally, tailor the error-amplifier gain versus frequency so that the desired phase margin is achieved.

Sampling theory shows that f_c must be less than half the switching frequency for the loop to be stable. However, it must be considerably less than that to attenuate large-amplitude switching frequency ripple at the output. Thus, the usual practice is to fix f_c at one-tenth the switching frequency.

5.3.5 Design Considerations

Similar to the voltage-mode ripple control regulator, there are also some prerequisites for the proposed technique to work properly. Design considerations are investigated for the fixed frequency current-mode ripple control (CMRC) boost regulator.

Filter Capacitor

The filter capacitance in a switching power supply is generally selected to limit output voltage ripple within the specified level. The series impedance of the capacitor and the output current determines the output voltage ripple. As described in the previous section, the three elements of the capacitor that contribute to its impedance are ESR, ESL, and capacitance.

In a voltage-mode ripple control regulator, the output ripple is monitored to trigger switching operations. As a result, ESR and ESL are two key factors to determine the switching frequency. However, in a current-mode ripple regulator, the inductor current ripple is monitored instead of the output voltage ripple. The output voltage ripple no longer affects the switching frequency. Thus, the only consideration for choosing the filter capacitor is to meet the output voltage ripple level.

The output voltage change due to the capacitor’s capacitance is usually assumed neg-ligible. For this assumption to be true, the filter capacitance must satisfy the following equation:

C À I_out(max)× D_max

f_SW × ∆V_out (5.53)

where I_out(max) is the maximum output current and D_max is the maximum duty ratio.

Because the filter capacitor supplies the entire load current during the on time, sufficient capacitance keeps output voltage within tolerance under maximum output current and maximum duty ratio. In many cases, to get sufficiently low ESR, capacitors with much more capacitance than needed are selected.

Typical output voltage and inductor current waveforms of the boost converter are

V1 V2

I_peak

I_valley

V

_out

I

_L

Figure 5.30: Output voltage and inductor current waveforms of the boost converter.

shown in Fig. 5.30. The ESL is removed from the circuit for simplicity. The output voltage ripple is mainly caused by the ESR. During the on time, the capacitor supplies the load current. The current flowing through the capacitor’s ESR develops a voltage drop, −I_out× r_C. During the off-time, the voltage drop is (I_L− I_out) × r_C. Thus,

V 1 = rC × Ipeak

V 2 = r_C × I_valley

(5.54)

From the above equations, we find that the output ripple relates to the inductor current and ESR. Thus, the maximum ESR needed to limit the ripple within ∆V_out is:

r_C 6 ∆V_out

³Iout(max)

1−Dmax +^∆I₂

´ (5.55)

ESL can cause large output ripple and must be reduced. This can be done by choosing low ESL capacitors or replacing one large device with several smaller ones in parallel.

Filter Inductor

The filter inductance must larger than the critical value that causes the circuit to operate at the edge of continuous conduction mode. At the edge of critical conduction, the average inductor current is equal to half of the inductor ripple current. In the boost power stage, the relationship of the average output current and the average inductor current is stated in Eq. 5.30. Therefore, from Eq.5.33, the minimum required inductance is obtained with a given minimum output current, I_out(min), and switching frequency:

L_(min) ' V_IN

In the current mode, the inductor current ripple is limited by the hysteretic window,

∆I. The maximum required inductance is determined by ∆I at a given switching fre-quency. With inductance larger than the maximum value, the inductor current cannot reach the hysteretic window within the required time. From Eq. 5.44, the relationship is expressed below: equation, we obtain the maximum inductance:

L_(max) ' V_IN

If t_D is much smaller than T_S× D, then the above equation is simplified as below:

L_(max)' VIN × (Vout+ Vd− VIN)

∆I × f_SW × (V_out+ V_d) (5.59)

Note that the minimum and the maximum inductance values are determined by I_out(min) and ∆I respectively at a given frequency. Divide Eq. 5.59 by Eq. 5.56, we obtain a ratio of maximum-to-minimum allowable inductance:

L_(max)

L_(min) = 2 × I_out(min)

∆I × (1 − D) = 2 × I_out(min)× (V_out+ V_d)

∆I × V_IN (5.60)

This inductance ratio is independent of the switching frequency and is adjustable by chang-ing ∆I. A wide range of allowable inductance provides more selection of the inductor and safety against component variations. Although decreasing ∆I increases the inductance ratio, noise may interference normal operations of the hysteretic comparator with a small

∆I. Also note that the inductance ratio becomes smaller with a small Vout-to-VIN ratio.

Assume t_D = 200 ns, ∆I = 0.1 A, V_d = 0.4 V, I_out(min) = 200 mA, Figures 5.31 to 5.33 plot the required maximum and minimum values of the filter inductor at different switching frequencies.

The choice of inductance must between the lowest maximum value and the highest minimum value within the possible input voltage range at the specified switching fre-quency. Although the inductance ratio is almost independent of the switching frequency, the differences between maximum and minimum inductance are smaller at higher fre-quencies. It will be difficult to choose appropriate inductors. As a result, smaller ∆I is required at high frequency. A proper choice of input voltage with respect to the specified output voltage also relaxes the inductance restrictions. Extremely high or low Vout-to-VIN

ratio usually offer few inductance choices. For example, 2.5 V output is suitable for input voltage as low as 0.8 V. On the other hand, input voltages lower than 1.2 V is not suitable to a 5 V output.

0.00

Figure 5.31: Required filter inductance at 200 kHz.

0.00

Figure 5.32: Required filter inductance at 300 kHz.

0.00

Figure 5.33: Required filter inductance at 450 kHz.

I_out

I_L V_out (this work)

V_out (original)

Figure 5.34: Load transient responses: Comparison of the proposed with an original CMRC boost regulator.

5.3.6 Simulation Results

Proposed current-mode ripple control boost regulator shown in Fig. 5.28 was simulated using SPICE. Parameter values are listed in Table 5.5. Output voltage is 3.3 V and input voltage is 2.4 V which is nominal voltage of a two-cell NiMH battery. Figure 5.34 shows the output voltage and the inductor current waveforms during a load transient. The output current stepped from 200 mA to 500 mA. For comparison, output voltage of an original varying-frequency CMRC boost regulator is also presented. The original CMRC boost regulator refers to that shown in Fig. 5.25. In steady state, the switching frequency was locked at 300 kHz. During the load transient, both regulators exhibited fast transient

V_out

I_L

V_IN

V_TH

Figure 5.35: Line transient response of proposed CMRC boost regulator.

response. The output voltage swing increased after the load transient because it is the product of capacitor ESR and output current, r_C × I_out. A decrease in average output voltage occurs with the increase in load current because of the finite gain of the error amplifier. Thus, load regulation is 0.96 %/A from simulation. Refer to Eq. 5.48 and 5.49, load current affects little on switching frequency. Therefore, even the original CMRC regulator varied slightly in switching frequency.

Battery voltage range of a two-cell NiMH battery is from 2.8 V (fully charged) to 1.8 V (depleted). Thus, the input voltage is gradually decreasing while the system is operat-ing. The original ripple regulator may encounter varying switching-frequency problem in

V_IN = 2.8V V_IN = 1.8V

V

_out

I

_cmd

I

_L

Figure 5.36: Output Voltage, current command, and inductor current waveforms during line transient.

battery-powered systems. Simulated line transient waveforms of the proposed regulator are shown in Fig. 5.35. Waveforms of Vout, IL, VIN, and threshold voltage of the delay element, V_{T H}, are shown from top to bottom. Larger V_{T H} represents more delay is add to the loop. V_IN dropped from 2.8 V to 1.8 V at t = 5 ms. Zoomed waveforms are also shown in Fig. 5.37. The ripple control regulator exhibited excellent line transient response because the decrease in V_IN instantly affects the up and down slopes of the inductor current. Therefore, the duty ratio immediately responses the change in V_IN. Refer to Eq.5.30, the inductor current, IL is inversely proportional to (1 − D) if Iout is

unchanged. Thus, I_L was increased after the line transient because duty ratio, D, was increased. Since I_L is controlled by the current command, I_cmd, generated by the error amplifier, average of Vout also dropped because the Icmd was increased. Their waveforms are shown in Fig. 5.36. As a result, the average value of V_out changed with V_IN, which is interpreted as line regulation. Line regulation is 0.75 %/V according to the definition in Eq. 2.4.

Referring to Fig. 5.27, switching frequency is higher when VIN = 1.8 V than 2.4 V with the same delay. To maintain a fixed switching frequency, V_{T H} in Fig. 5.35 was increased by the phase-locked loop. To verify the effectiveness of the phase-locked loop, Figure 5.37 compares the switching frequency with an original CMRC regulator under different input conditions. No extra delay is inserted besides internal system delay. Before the line transient shown in Fig. 5.37(a), the switching frequencies of the proposed fixed-frequency regulator and the original regulator were equally 300 kHz. After the line transient from 2.8 V to 1.8 V, both immediate switching frequencies were increased to 455 kHz. After 1.5 ms, the control loop had already entered steady state. As Fig. 5.37(b) shows, switching frequency of proposed regulator had come back to 300 kHz, but it was still 455 kHz for the original regulator.

5.4 Summary

Methods and circuits for achieving fixed output frequency operations of ripple control buck and boost regulator have been presented. Switching frequency of conventional rip-ple control regulators is a function of circuit delay, ESR of the output capacitors, and many other parameters. The proposed control loop adjusts delay of the controller and

V_out (original) V_out (this work)

V_IN = 2.8V V_IN = 1.8V (a) During the line transient.

V_out (original) V_out (this work)

(b) 1.5 ms after the line transient.

Figure 5.37: Switching frequency comparison between proposed and an original CMRC boost regulator during line transient.

Table 5.5: Parameters used in CMRC boost regulator.

Output voltage, V_out 3.3 V

Input voltage, V_IN 2.4 V

Reference voltage, V_r 1.2 V

Output current, I_out 200–500 mA

Filter inductor, L 8.2 µH

Filter capacitor, C 100 µF

DCR of inductor, r_L 0.1 Ω

ESR of capacitor, r_C 50 mΩ

On-state resistance of MOSFET, R_ON 20 mΩ Input clock frequency, f_clk 300 kHz Diode forward voltage, V_d 0.4 V

CSA gain 5

Inductor current hysteresis, ∆I 0.2A Current-sense resistor, R_S 80 mΩ Compensation resistor, R₁ 2.1 kΩ Compensation resistor, R₂ 11 kΩ Compensation capacitor, C₁ 80 nF Compensation capacitor, C2 2 nF

thus controls the output frequency. This is done by using a PLL to lock the frequency of the switching signal with the input clock. A linear model of the PLL has been derived for stability analysis. Simulation results showed the proposed method provides the rip-ple regulator a fixed frequency operation. Good load/line transient response and tight regulation were also observed from simulation.

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