Circuit Topology

4.1.1.1 The Current-Reuse LC VCO

Several LC VCO topologies have been proposed in past and present literature, such as NMOS-pair cross-coupled LC VCO, PMOS-pair cross-coupled LC VCO, and NMOS-pair & PMOS-pair cross-coupled LC VCO. Fig. 4.1, Fig. 4.2, and Fig. 4.3 show three such kinds of VCOs with a current source. The symmetric topologies have

the advantage that they create the symmetric waveforms and could reduce the l/f noise up conversion [37]. If there is no current source in VCO, the VCO has the benefit of better phase noise. A widely known oscillator is the conventional differential negative-Gm oscillator that is shown in Fig. 4.1. The topology consists of two identical half circuits composed of switching transistors, inductors, and varactors. A signal feeds back from the drain of M1 to the gate of M2 which acts as an active buffer, and vice versa. The topology of Fig. 4.3 consumes more voltage headroom, larger MOS sizes are needed to get enough transconductance to lower the overdrive voltage. But the parasitic capacitances will increase and thus the tuning range will reduced. The transconductance of the topologies are determined by the current consumption and the sizes of devices. The cross-coupled MOS pair forms the positive feedback and the input impedance Rin = (-2/gmn) + (-2/gmp) in Fig. 4.3. The VCOs in Fig. 4.1 and Fig. 4.2 have the larger voltage headroom and the wider tuning range.

The related smaller geometry of the devices is sufficient to get enough transconductance to start the oscillation. The input impedance of cross-coupled pair is Rin = -2/gmn or -2/gmp in Fig. 4.1 or Fig. 4.2. Therefore, these three topologies have their own trade-offs.

VDD

L1 L2

Fixed Capacitor

Varator 1 Vtune Varator 2

M1 M2

Fig. 4.1. NMOS-pair cross-coupled LC VCO.

VDD

L1 L2

Fixed Capacitor

Varator 1 Vtune Varator 2

M1 M2

Fig. 4.2. PMOS-pair cross-coupled LC VCO.

M3 M4

VDD

L1

Fixed Capacitor

Varator 1 Vtune Varator 2

M1 M2

Fig. 4.3. NMOS-pair & PMOS-pair cross-coupled LC VCO.

In Fig. 4.4, this topology uses both NMOS and PMOS transistors as a negative conductance generator, which is improved from conventional NMOS-pair &

PMOS-pair cross-coupled LC VCO. The series stacking of NMOS and PMOS allows the supply current to be reduced by half compared to that of the conventional LC VCO while providing the same negative conductance. This structure drives the current in the half of period and let the LC tank discharge in another half period to create the oscillation [38]. Because the NMOS & PMOS pair operates in triode region near the peak of the voltage swing, the voltage swing is only limited by the power supply. Recently, three current-reuse CMOS LC VCO has been published [38],[39],[40]. Two types of low power current-reuse CMOS differential LC VCO are shown in Fig. 4.5 and Fig. 4.6.

M3

VDD

L1

Fixed Capacitor

Varator 1 Vtune Varator 2

M2

Fig. 4.4. NMOS & PMOS pair LC VCO.

M1

VDD L1

Varator 1 Vtune Varator 2

M2

Rs

Fig. 4.5. Current-reuse LC VCO by Seok-Ju Yun [38].

M1

VDD L1

Varator 1 Vtune Varator 2

M2

R1 C1

R2

Fig. 4.6. Current-reuse LC VCO by Zheng Wang [39].

4.1.1.2 Noise Filtering Technique

As published by Leeson [41], the phase noise of an LC VCO can be described as equation 4.1. In Leeson’s equation, Δf is offset frequency, Q is loaded quality factor of the LC tank, Ao is voltage swing amplitude, F is excess noise factor, Δf1/ f3 is corner frequency of device's flicker noise, and f⁰ is oscillation frequency. This equation describes that the most effective way to lower phase noise to improve the loaded quality factor of the LC tank. In order to reduce the phase noise of VCO, the research has been focus on improving the quality factor of the LC tank and suppressing the harmonics inside the VCO core.

( )

Low frequency bias noise would be up converted into phase noise through the switching action of the cross-coupled transistors [46]. The high-frequency bias noise is usually grounded by the large junction capacitances of the bias transistors. PMOS device is preferred to bias the circuit than NMOS device because PMOS has lower corner frequency of flicker noise. From equation 4.2, large device size is used since the flicker noise is related to the device size. The nonlinear of the transistors will generate harmonic distortion at the VCO tank output nodes. Second and third harmonics of the fundamental current flow into the lower impedance side of the LC tank. Reducing device sizes means more low frequency flicker noise would be up converted into phase noise. Therefore the optimum device sizing is a tradeoff between AM-PM conversion factor and switching device's flicker noise.

Noise Frequencies around the second harmonic down convert to the oscillation frequency, and up convert to around the third harmonic. We can use parallel inductor and capacitor at the output node of bias transistor to provide high impedance at the second harmonic. Thus parallel LC can suppress the second harmonic leaking from the LC tank across the oscillation as shown in Fig. 4.7. A noise filter in the tail tuned to the second harmonic. This circuit oscillates with the largest possible amplitude because there is no current-source in series with the differential pair to consume

voltage headroom. In other words, the noise filter consumes zero voltage headroom and outputs the largest possible amplitude.

L1 VDD L2

Varator 1 Vtune Varator 2

M1 M2

Fig. 4.7. Voltage-biased VCO with noise filter.

8 8

2 _o 9 ^mbias

F IR g R

V

γ γ

= + π + (4.3)

Phase noise is scaled by a specific noise factor F. The noise factor is given by [47]

as equation 4.3 where I is the bias current, γ is the channel noise coefficient of the transistor, R is the load resistance, g_mbiasis the transconductance of the current source transistor, and Vo is the voltage across the resonator and is proportional to the slope at the zero crossing voltage of the switching cell [47]. The first and second terms in equation 4.3 describe the phase noise contributions from the resonator loss and differential pair transistors. The third term in equation 4.3 represents the phase noise produced by down conversion of the CS noise component at the second harmonic of the oscillation frequency. The second term can be reduced by increasing Vo. To realize the concept, we have employed a second harmonic LC tank.

4.1.1.3 The Proposed 24 GHz VCO 01

Fig. 4.8 shows the proposed VCO. It consists of current-reuse VCO structure, filtering inductor, main LC tank, and second harmonic LC tank. The two output buffer employ common source amplifier for testing purpose.

Vcontrol VDD

Vout + Vout

-Vbias Vbias

Fig. 4.8. Proposed 24 GHz VCO 01.

In CMOS VCO, the integration of a high-Q LC tank is not easy due to the low resistivity of the silicon substrate, and this greatly affects the phase-noise performance.

The phase noise reduction is achieved by circuit design techniques in CMOS LC VCO.

In Fig. 4.8, we use second harmonic LC tank which is open at the fundamental frequency and short at the second harmonic to suppress the down conversion of the noise around the second harmonic. The second harmonic LC tank can suppress the phase noise from various noise sources including the negative gm core transistors. Fig.

4.9 shows the two tanks connected with 50Ω terminations. Fig. 4.10 is the simulated result of the magnitude of the S-parameter of main and second harmonic LC tanks.

Fig. 4.11 is the simulated result of the magnitude of the S-parameter of total LC tank.

Term

Magnitude of S parameter

2nd LC tank Main LC tank

Fig. 4.10. Simulated results of main and second harmonic LC tanks.

20 40 60 80

Magnitude of S parameter

Fig. 4.11. Simulated result of total LC tank.