4.1 The Design of 24 GHz VCO 01
4.1.2 Simulated Performance
Fig. 4.12 shows the layout of the proposed VCO 01. The size of the layout is 1.03mm by 0.93mm including pads. Considering the layout effect, take the long layout line as shown in Fig. 4.13. Running EM simulation by ADS Momentum and obtain the layout effect model. Then, using ADS simulated with layout effect. Fig.
4.14 shows the output spectrum at 24GHz when control voltage is 0.75V. From output spectrum, second harmonic is 71dBc lower than fundamental tone. Fig. 4.15 shows
the phase noise performance for a carrier frequency of 24GHz. Phase noise at 1MHz offset from the carrier is -111.3 dBc/Hz. Fig. 4.16 shows the transient responses of the VCO differential output outside the buffer. The single-ended output amplitude is 280mV, which translates into -0.35dBm output power with a standard 50Ω load. The tuning range is 1.6GHz as shown in Fig. 4.17. The output power variation is 1.1dB as shown in Fig. 4.18. The simulated phase noise results for each technique in Fig. 4.19 show the phase noise reduction effect of each technique independently and the combined case for a carrier frequency of 24GHz and same power consumption. The phase noise of standard LC VCO is -101 dBc/Hz. The phase noise of filtering inductor is -105 dBc/Hz. The phase noise of 2nd harmonic LC tank is -106 dBc/Hz. Combined two techniques can improve phase noise about 10dB. Table 4.1 summarizes the VCO performance of simulated results.
Fig. 4.12. Layout of the proposed VCO 01.
Fig. 4.13. EM consideration.
GND
GND
GND
GND GND
GND
Vout2 Vout1
VDD
VDD Vbias
Vctrl
m4freq=
m2Vctrl=
Fig. 4.17. Control voltage versus output frequency.
m3Vctrl=
Fig. 4.18. Control voltage versus output power.
0.0 0.2 0.4 0.6 0.8 1.0 (1) Current-reuse LC VCO (2) Filtering inductor + (1) (3) 2nd harmonic LC tank + (1) (4) 2nd harmonic LC tank + (2)
Fig. 4.19. Simulated phase noise results for each technique.
Parameters Simulation result Technology TSMC 0.18um CMOS Center frequency (GHz) 24
Supply voltage (V) 1.8
Core Current (mA) 5.5
Tuning Range (GHz) 23.32 ～ 24.92
Vtune (V) 0 ～ 1.8
Output Power (dBm) -0.357 Phase Noise
@1MHz offset (dBc/Hz) -111 Chip area (mm2) 1.03 X 0.93 Power Consumption (mW) 10
Table 4.1 Summary of VCO 01 simulation results
4.1.3 Comparison and Summary
For the comparisons between recent VCO topologies in terms of power consumption, carrier frequency and phase noise, figure of merit (FOM) expression for 1MHz offset is used as equation 4.3 Where fo is the carrier frequency, Δf is the offset, L(Δf) is the phase noise, and P is the power consumption by the VCO.
( )
20log f0 10log( )
FOM L f P
f
⎛ ⎞
= − Δ + ⎜⎝Δ ⎟⎠− (4.3)
The comparison of the proposed VCO against recently reported high frequency VCOs (Frequency > 20GHz) is shown in Table 4.2. It can be seen that this simulated VCO achieves better phase noise due to second harmonic filtering. The FOM of proposed VCO is -189. It’s better than recently reported CMOS VCOs. Ref. [52] is designed at 24GHz and using 8GHz VCO cascaded with frequency tripler. Ref. [53] is using ring oscillator structure. The first one of Ref. [56] is designed at 24GHz and using 12GHz VCO cascaded with mixer. The second of Ref. [56] is designed at 24GHz and using 24GHz stand-alone VCO.
Ref. Technology fosc
[50] 0.25um SiGe 21.5 1.06 -6 -113 1MHz 3.2 130 -178
[51] 0.35um SiGe 42 10.9 3.5 -110 1MHz 5.5 280 -179
[52] SiGe 23.5 0.42 -10 -100 1MHz 3.3 180 -165
[53] 0.12um SiGe 24.3 6.5 -14 -105 10MHz 3.3 105 -152
[54] 0.25um SiGe 32 2 -19 -97 1MHz 5 215 -163
[55] 0.12um SOI CMOS 44 4 -6 -101 1MHz 1.5 7.5 -185
[56] 0.18um CMOS 25.1 3 -18.8 -100 1MHz 2.2 11 -177
[56] 0.18um CMOS 21.6 1.6 -4.2 -102 1MHz 3 45 -172
[57] 0.25um CMOS 19.4 5 -20.4 -101 1MHz 4.5 9 -177
This work 0.18um CMOS 24 1.6 -0.3 -111 1MHz 1.8 10 -189
PERFORMANCE OF REPORTED HIGH FREQUENCY VCOs (Frequency > 20 GHz)
Table 4.2. Summary of the comparison
This section presents current-reuse voltage-controlled oscillator (VCO) topologies by stacking switching transistors in series like a cascode. The VCOs can operate with only half the amount of dc current compared to those of the conventional VCO topologies. A filtering inductor was used at the source node of the NMOS transistor to improve phase noise. The second harmonic LC tank is used to suppress the second harmonic as well as leaking from the LC tank across the oscillation. These two techniques can improve phase noise more than 10dB totally at the carrier frequency of 24GHz. A 24GHz LC VCO was fabricated in a 0.18um CMOS process.
The simulation result shows the achieved phase noise of -111 dBc/Hz at 1-MHz offset while the VCO core draws 5.5mA from a 1.8V supply. The tuning range is from 23.32GHz to 24.92GHz. The size of the layout is 1.03mm by 0.93mm including pads.
4.2 The Design of 24 GHz VCO 02
In this section, another 24 GHz LC VCO is presented. First, the design and analysis of the proposed VCO is introduced. Then, the simulation results are discussed. Finally, comparison and summary are discussed.
4.2.1 Circuit Topology
Fig. 4.20 shows the proposed VCO. It consists of current-reuse VCO structure, filtering inductor, main LC tank, and T-structure filter. The two output buffer employ common source amplifier for testing purpose.
Vctrl VDD
Vout + Vout
-Vbias Vbias
Fig. 4.20. Proposed 24 GHz VCO 02.
In Fig. 4.20, we use T-Structure filter to suppress effect of harmonics. The T-Structure filter consists of L and C is shown in Fig. 4.21. It’s a 2nd order filter and the 4th order transfer function is shown as equation 4.4. The T-Structure filter is added parallel with main LC tank. From the transfer function, we have the zero as equation 4.5. The zero frequency is designed at the desired frequency. The Q of this filter is as equation 4.6. Fig. 4.22 shows the two tanks connected with 50Ω terminations. Fig.
4.23 is the simulated result of the magnitude of the S-parameter of T-Structure filter
and main LC tank. There are two poles at 48GHz and 72GHz.
Fig. 4.21. T-Structure filter consists of LC.
4 2
Magnitude of S parameter
Fig. 4.23. Simulated result of magnitude of the S parameter.
4.2.2 Simulated Performance
Fig. 4.24 shows the layout of the proposed VCO 02. The size of the layout is 0.90mm by 0.93mm including pads. Considering the layout effect, take the long layout line as shown in Fig. 4.25. Running EM simulation by ADS Momentum and obtain the layout effect model. Then, using ADS simulated with layout effect. Fig.
4.26 shows the output spectrum at 24GHz when control voltage is 0.75V. Fig. 4.27 shows the phase noise performance for a carrier frequency of 24GHz. Phase noise at 1MHz offset from the carrier is -111.6 dBc/Hz. Fig. 4.28 shows the transient responses of the VCO differential output outside the buffer. The single-ended output amplitude is 280mV, which translates into -0.68dBm output power with a standard 50Ω load. The tuning range is 1.56GHz as shown in Fig. 4.29. The output power variation is 1.3dB as shown in Fig. 4.30. The simulated phase noise results for each technique in Fig. 4.31 show the phase noise reduction effect of each technique independently and the combined case for a carrier frequency of 24GHz and same power consumption. The phase noise of standard LC VCO is -101 dBc/Hz. The phase noise of filtering inductor is -105 dBc/Hz. The phase noise of T structure filter is -106 dBc/Hz. Totally combined two techniques can improve phase noise about 10dB. Table 4.3 summarizes the VCO performance of simulated results.
VDD GND Vbias
Fig. 4.25. EM consideration.
20 40 60 80 100 120 140 160 180
0 200
-100 -80 -60 -40 -20
-120 0
Frequency (GHz)
Output (dBm)
Fig. 4.26. Output spectrum at 24GHz.
m1noisefreq=
m1=-111.6 dBc1.000MHz
0.2 0.4 0.6 0.8
0.0 1.0
-110 -100 -90 -80 -70 -60
-120 -50
Offset frequeny (MHz)
Phase noise (dBc/Hz)
m1
Fig. 4.27. Phase noise of the VCO at 24GHz.
10 20 30 40 50 60 70 80
Fig. 4.29. Control voltage versus output frequency.
m3Vctrl=
Fig. 4.30. Control voltage versus output power.
0.0 0.2 0.4 0.6 0.8 1.0
(1) Current-reuse LC VCO (2) Filtering inductor + (1) (3) T structure filter + (1) (4) T structure filter + (2)
Fig. 4.31. Simulated phase noise results for each technique.
Parameters Simulation result Technology TSMC 0.18um CMOS Center frequency (GHz) 24
Supply voltage (V) 1.8
Core Current (mA) 5.5
Tuning Range (GHz) 23.22 ～ 24.78
Vtune (V) 0 ～ 1.8
Output Power (dBm) -0.68
Phase Noise
@1MHz offset (dBc/Hz) -111.6 Chip area (mm2) 0.90 X 0.93 Power Consumption (mW) 9.9
Table 4.3 Summary of VCO 02 simulation results
4.2.3 Comparison and Summary
The comparison of the proposed VCO against recently reported high frequency CMOS VCOs (Frequency > 20GHz) is shown in Table 4.4. The FOM of proposed VCO is -189. It’s better than recently reported CMOS VCOs. Fig. 4.32 shows the simulated summary of phase noise reduction technique. In this figure, (5) is VCO01 and (6) is VCO02.
This work 0.18um CMOS 24 1.56 -0.68 -111.6 1MHz 1.8 9.9 -189
PERFORMANCE OF REPORTED HIGH FREQUENCY CMOS VCOs (Frequency > 20 GHz)
Table 4.4 Summary of the comparison
0.0 0.2 0.4 0.6 0.8 1.0 -120
-110 -100 -90 -80 -70 -60 -50 -40 -30 -20
Phase noise (dBc/Hz)
Offset Frequency (MHz)
(1) Current-reuse LC VCO (2) Filtering inductor + (1) (3) 2nd harmonic LC tank + (1) (4) T-structure filter + (1) (5) 2nd harmonic LC tank + (2) (6) T-structure filter + (2)
Fig. 4.32. Simulated summary of phase noise reduction technique.
This section presents current-reused voltage-controlled oscillator topologies by stacking switching transistors in series like a cascode. The VCOs can operate with only half the amount of dc current compared to those of the conventional VCO topologies. A filtering inductor was used at the source node of the NMOS transistor to improve phase noise. The T-structure is used to suppress harmonics as well as leaking from the LC tank across the oscillation. These two techniques can improve phase noise more than 10dB totally at the carrier frequency of 24GHz. A 24GHz LC VCO was fabricated in a 0.18um CMOS process. The simulation result shows the achieved phase noise of -111 dBc/Hz at 1-MHz offset while the VCO core draws 5.5mA from a 1.8V supply. The tuning range is from 23.32GHz to 24.782GHz. The size of the layout is 0.90mm by 0.93mm including pads.