3.1 The Design of Wideband Down Conversion Mixer (Mixer 01)
3.1.5 Comparison and Summary
The comparison of the proposed mixer against recently reported wideband mixer is shown in Table 3.2, it indicates that the proposed mixer provides better linearity, more compact chip size, and acceptable conversion gain and power consumption. In Ref. [32], the power consumption of mixer core is 71mW and the RF input return loss is better than 10dB for frequency from 10GHz to 21GHz.
Ref. [30] [31] [32] [33] this work
In this section, a 2.4 to 10.7 GHz wideband mixer for multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) applications is designed using a TSMC 0.18μm CMOS technology. The designed mixer uses a LC folded cascode structure and a feedforward compensated high-linearity differential transconductor. The LC folded cascode method is used to get enough voltage headroom to work with, and the modified feedforward compensated differential transconductor is adopted to achieve broadband impedance matching and lower the overall distortion. The measured results reveal that the proposed mixer achieves power conversion gain of 3.3 ± 1.5 dB, third-order input intercept point (IIP3) of 6.9 dBm, and input 1-dB compression point (P-1dB) of -2.8 dBm in the power consumption of 14.4mW from a 1.8V power supply. The chip area is 0.70 × 0.58 mm2.
This wideband down-conversion mixer is accepted for publication on the IEEE International Symposium on Circuits and Systems (ISCAS) 2007.
3.2 The Design of Wideband Down-Conversion Mixer with Broadband Active Balun
In this section, a wideband mixer with broadband active balun is presented. The proposed mixer employs a LC folded cascode structure and a feedforward compensated differential transconductor. The broadband active balun is used in the RF and LO ports. The design and analysis of broadband active balun is described in this section. Finally, the simulated and measured results are discussed.
3.2.1 Broadband Active Balun Design
3.2.1.1 Broadband Active Balun Circuit Description
In this section, a broadband active balun is analyzed and designed. The schematic of the proposed broadband active balun is shown as Fig. 3.15. It is improved from common-gate cascaded with common-source. The output1 is from common-source (MN1) stage and output2 is from two PMOS common-gate cascode (MP1 & MP2). The PMOS is used to reduce power consumption instead of NMOS.
The purpose of cascode two PMOS is to reduce phase difference.
Input
VDD
Output1
MN1
MP1 MP2
Rin
Output2
Fig. 3.15. Schematic of the proposed broadband active balun.
There are three kinds of matching circuits: LC matching, active matching and resistive matching. LC matching has lower noise, higher Q and filtering performance.
LC matching takes more die area than the other two matching. Active and resistive
matching have wideband performance. Active matching needs extra dc current and resistive matching is lossy and noisy. Based on these considerations, a compromise is made. Rin is used as input matching in order to save the die area. The Input impedance matching is shown as Fig. 3.16.
0 2 4 6 8 10 12 14 16 18 20
Input Returm Loss (dB)
Frequency (GHz)
With resistive matching Without resistive matching
Fig. 3.16. Input impedance matching.
The simulated amplitude balance and phase difference of the proposed active balun combine with mixer core are shown in Fig. 3.17. ADS simulated data show that the bandwidth is 11 GHz. The gain difference is less than 2 dB (-0.7 ～ -1.9) and phase difference is less than 4 degrees (178 ～ 182) with a bandwidth from 2GHz to 13GHz while consuming 1.8mW.
0 2 4 6 8 10 12 14 16
Gain Difference Phase Difference
Fig. 3.17. Simulated amplitude balance and phase difference.
Comparison of recently reported CMOS active Baluns with this study is shown as Table 3.3. The three references are measured results. Ref. [14] is the best CMOS active Balun in recently published papers.
Ref. [18] [7] [14] This Work
Process 0.18-um CMOS 0.25-um CMOS 0.18-um CMOS 0.18-um CMOS Architecture Differential Differential Differential CSCG Frequency (GHz) 5.1 ～ 5.9 5.4 ～ 5.8 0 ～ 8 2 ～13
Gain difference (dB) 0.02 0.5 2 2
Phase difference (Degrees) 0.58 1 3 4
Power (mW) 9.17 --- 1.44 1.8
Chip area (mm) --- --- 0.57X0.68 0.1X0.1
Table 3.3 Comparison of CMOS active baluns
3.2.1.2 Phase Difference Analysis
(a) (b)
Vin
Vout1 Vout2
Vin
Vout1 Vout2
Fig. 3.18. Circuits of (a) the conventional CSCG Balun and (b) the Cascode CG &
CS Balun.
Fig. 3.18(a) illustrates the conventional CSCG Balun. It’s consists of common-gate and common-source. Fig. 3.18(b) illustrates the cascode CG & CS Balun. It’s consists of common-gate cascode with common-gate and common-source.
The phase difference of Fig. 3.18(a) and Fig. 3.18(b) are derived as below.
G D
Fig. 3.19. Small-signal equivalent circuit model of common-source.
Fig. 3.19 illustrates the small-signal equivalent circuit model of common-source.
Assuming that all ports are terminated in the characteristic impedance Z0.
Drain
Fig. 3.20. Small-signal equivalent model neglecting Cgs.
To derive Zin, we consider Zx in Fig. 3.20 firstly. We have
( )( 1 )
Then Zin is given by Let us now calculate the relationship of Vin and Vout. We can sum the currents at the output node：
0
The S21 of common source can be written as
2 Then substituting (3.21), (3.23), and (3.25) into (3.24). The amplitude and phase of S21 can be derived as (3.26) and (3.34).
2
Fig. 3.21. Small-signal equivalent circuit model of common-gate.
Fig. 3.21 illustrates the small-signal equivalent circuit model of common-gate.
To derive Zin, we calculate Zx which is seen into Cgd at G node. We have
1 1 1 1 Let us now calculate the relationship of Vin and Vout. We can sum the currents at the output node：
1
Thus
The S21 of common gate can be written as
2
The amplitude and phase of S21 can be derived as (3.40) and (3.49).
21 (1 )
G
Fig. 3.22. Small-signal equivalent circuit model of cascode common-gate.
Fig. 3.22 illustrates the small-signal equivalent circuit model of cascade common-gate. We calculate Zin which is seen into S node at bottom. We have
1
in
m gs
Z ≈ g sC
+ (3.50) Let us now calculate the relationship of Vin and Vout. Let Vx denotes the voltage in the center of these two common-gate. We have
1 1
Then Id2 is written as
2 2 2 2 2
We have
Therefore, we know the relationship of Vin and Vout as the below equation.
2
. Substituting Zin and 2
1
V
V into it. Then S21 is derived.
The amplitude and phase of S21 can be derived as (3.57) and (3.65).
21 (1 )
Thus,
Therefore, the phase difference of Fig. 4.4(a) is given by (3.34) substrate (3.49) and the phase difference of Fig. 4.4(b) is given by (3.34) subtract (3.65). The phase mismatch is give by
21 21
From equation (3.66) and (3.67), we conducted simulation tests on TSMC 0.18μm CMOS process. Assuming L=0.18μm, W=2μm, Finger=15, and Id=1mA, we can obtain the simulated phase differences of the cascode common gate and the conventional active balun as shown in Fig. 3.23. Phase mismatch is means the degree away from 180. The result demonstrated the cascode common gate can improve phase performance.
Fig. 3.23. Simulated phase differences.
0 2 4 6 8 10 12 14 16 Cascode CG & CS Balun Conventional CSCG Balun
3.2.2 Design of the Wideband Mixer with Broadband Active Balun 3.2.2.1 Mixer Core
Fig. 3.24. shows the mixer core, which is composed of an LC folded cascode mixer and a feedforward compensated differential transconductor. Their design and analysis is described in section 3.1.
IF + RF
LO -VDD
RF +
LO +
IF -Vbias
M1 M2
M3 M4
M5 M6 M7 M8
Fig. 3.24. Schematic of the mixer core.
3.2.2.2 Proposed Wideband Mixer Topology
Fig. 3.25 illustrates the block diagram of the proposed wideband mixer. It includes mixer core, active baluns, and output buffer. Mixer core is the LC folded cascode mixer with modified differential transconductor. Active baluns are modified CSCG balun for generating balanced RF and LO signals to double balanced Gilbert mixer. Output buffer is differential amplifier and common-source amplifier for testing and matching purposes. All ports are single input and single output. This circuit can directly combine with frond-end and back-end circuits. The circuit schematic of the proposed wideband mixer is shown in Fig. 3.26.
RF +
RF -IF +
IF -LO + LO
-Output Buffer
RF IF
LO
Modified CGCS
Balun
Double Balanced
Mixer
Fig. 3.25. Block diagram of the proposed wideband mixer.
IF
VDD
M1 M2
M3 M4 M5 M6 M7 M8
RF
LO
Fig. 3.26. Complete Schematic of the proposed wideband mixer.
3.2.3 Simulation and Measurement Results
In this section, we show the measurement setups and results of the proposed mixer. The measurements were performed with the chip directly mounted on a 26×26 mm2 and thickness of 20 mil RO4003 microwave substrate with SMA connectors. Fig.
3.27 shows the test board with die mounted on RO4003 printed circuit board (PCB).
Fig. 3.28 shows the PCB layout. The chip layout and microphotograph are shown in Fig. 3.29 and Fig. 3.30. The die size is 0.85×0.57 mm2 including pads. Fig. 3.31 shows the measurement setup of power conversion gain. The DC power supplier provide 1.8V dc source to mixer in measurement. The connectors and lines both result in loss in measurement.
RF LO
IF VDD
VDD GND
Fig. 3.27. Die bonded to the PCB.
Fig. 3.28. PCB layout of the proposed mixer.
GND GND
GND GND
VDD VDD
VDD RF
IF
LO
Fig. 3.29. The chip layout of the proposed mixer.
Fig. 3.30. Microphotograph of the proposed mixer.
Fig. 3.31. Measurement setup of power conversion gain.
The mixer is designed using TSMC 0.18μm CMOS technology. All measurements were done at 1.8 V supply voltage and the power consumption is 25.7 mW including the output buffer. The power consumption of output buffer is 14.5 mW.
Fig. 3.32 illustrates the conversion gain versus the RF frequency with both RF and LO ports swept in frequency from 2 to 12 GHz, a fixed IF frequency of 50 MHz, RF power of -30 dBm, and LO power of -5 dBm. The flat conversion gain is 6.9 ± 1.5dB with a bandwidth of 2 to 11.5 GHz. Simulation1 means the bond wire equivalent model is using 20mil. But it’s not 20mil actually. Simulation2 is the practical bond wire length approximate calculated from the chip. The measured RF return loss is better than 10 dB as shown in Fig. 3.33. The measured LO and IF return loss are also better than 10dB as shown in Fig. 3.34 and Fig. 3.35. The measured RF-to-IF, LO-to-IF and RF-to-LO isolation shown in Fig. 3.36. are better than 20 dB. Fig. 3.37 and Fig. 3.38 are P1dB and IIP3 when RF frequency is 8GHz. Fig. 3.39 and and Fig.
3.40 show the linearity of the mixer as a function of frequency. The measured IIP3 is 1.8 ~ 6.5 dBm and P1dB is -3.5 ~ -8.5 dBm in the bandwidth of 2 to 11.5 GHz. Table 3.4 shows the performance summary of simulated and measured results.
DC Block DC Block
DC Block
Signal Generator Signal
Generator
Spectrum Analyzer
RF LO
IF
VDD
VDD GND
2 4 6 8 10 12 14
Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result
Power Conversion Gain (dB)
RF Frequency (GHz)
Fig. 3.32. Simulated and measured power conversion gain versus RF frequency with the IF frequency is 50MHz, RF power is -30dBm, and LO power is -5 dBm.
0 2 4 6 8 10 12 14
RF return loss (dB)
Frequency (GHz) Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result
Fig. 3.33. Simulated and measured RF return loss versus RF frequency.
0 2 4 6 8 10 12 14
Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result
LO return loss (dB)
Frequency (GHz)
Fig. 3.34. Simulated and measured LO return loss versus LO frequency.
0 200 400 600 800 1000 1200
IF return loss (dB)
Frequency (MHz)
Fig. 3.35. Simulated and measured IF return loss versus IF frequency.
2 4 6 8 10 12 14
Fig. 3.36. Measured Isolation versus RF frequency.
-30 -25 -20 -15 -10 -5 0 5 10
Power Conversion Gain (dB)
RF Input Power (dBm) RF frequency : 8 GHz
IF frequency: 50 MHz LO frequemcy : 7.95 GHz LO power : -5 dBm
P1dB: -7dBm
Fig. 3.37. Measured Power Conversion Gain versus RF input power, RF: 8GHz, LO:
7.95GHz.
-35 -30 -25 -20 -15 -10 -5 0 5 10 15
RF1 frequency : 8.001 GHz RF2 frequency : 8 GHz LO frequemcy : 7.9505 GHz LO power : -5 dBm
Output Power (dBm)
RF Input Power (dBm) Main Signal Power
3rd order IM Power
IIP3: 3.5dBm
Fig. 3.38. Measured IIP3 curves, gain:+7.6dB, RF: 8 and 8.001 GHz, LO: 7.9505 GHz -5dBm. The input referred IP3 is +3.5dBm.
2 4 6 8 10 12 14
Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result
Fig. 3.39. Simulated and measured P1dB versus RF frequency.
2 4 6 8 10 12 14
RF input power: -30 dBm LO input power: -5 dBm Simulation result1 - 20 mil bondwire
Simulation result2 - Modified bondwire Measurement result
IIP3 (dBm)
RF Frequency (GHz)
Fig. 3.40. Simulated and measured IIP3 versus RF frequency.
Parameters Simulation result Measurement result RF Input Return Loss (dB) < -10 < -10
Input P1dB (dBm) -11.3 ～ -8.4 -8.5 ～ -3.5
Table 3.4 Summary of simulation and measurement results
3.2.4 Comparison and Summary
The comparison of the proposed mixer against recently reported wideband mixer is shown in Table 3.5, it indicates that the proposed mixer provides better linearity, more compact chip size, and acceptable conversion gain and power consumption. In Ref. [32], the power consumption of mixer core is 71mW and the RF input return loss is better than 10dB for frequency from 10GHz to 21GHz.
Ref. [30] [31] [32] [33] this work
In this section, a 2 to 11.5 GHz wideband mixer using LC folded cascode mixer topology, modified feedforward compensated differential transconductor, and broadband active balun in TSMC 0.18μm CMOS technology is presented. The LC folded cascode method is used to get enough voltage headroom to work with, and the modified feedforward compensated differential transconductor is adopted to achieve broadband impedance matching and lower the overall distortion. The adoption of broadband active balun in the designed wideband mixer allows providing balance signals for mixer core from single input. The measured results reveal that the proposed mixer achieves power conversion gain of 6.9± 1.5 dB, third-order input intercept point of 6.5 dBm, and input 1-dB compression point of -3.5 dBm in the power consumption of 25.7mW from a 1.8V power supply. The chip area is 0.85 × 0.57 mm2. The designed mixer is suitable in the receiver front end of ultra-wideband system.
3.3 The Design of Single-Sideband Mixer for UWB Synthesizer
In this section, a single-sideband (SSB) mixer for UWB synthesizer is designed.
It is important to devise a SSB mixer to generate multi-band carrier signals for frequency translation with electronic band selection capability. The SSB mixer can provide either upper or lower sideband output through an electronic control.
3.3.1 Principle of SSB Mixer
Fig. 3.41 shows the block diagram of frequency summation, which consists of four mixers and two output combiner. Fig. 3.42 shows the block diagram of difference, which consists of four mixers and two output combiner. In the ideal case, the SSB mixer only generates either upper (w1+w2) or lower (w1-w2) sideband component. In practice, both sidebands are present due to non-quadrature phase or amplitude imbalance.
Fig. 3.41. Principle of SSB mixer: frequency summation.
VCO
Mixer
I
Q
I
Q
cos
1A i ω t
sin
1A i ω t
sin
2B i ω t cos
2B i ω t
+ +
+
-Fig. 3.42. Principle of SSB mixer: frequency difference.
The I/Q signals of Fig. 3.41 can derived as equation (3.68) and (3.69). We can see the frequency summation results from these two equations. The I/Q signals of Fig.
3.42 can derived as equation (3.70) and (3.71). We can see the frequency difference results from these two equations.
1 2 1 2 1 2
If we consider the SSB principle from frequency domain, Fig. 3.43 shows the lower side-band suppression. Using I/Q mixers to remove lower side-band signal as shown in Fig. 3.44. Fig. 3.45 shows the upper side-band suppression and Fig. 3.46 shows the remove of upper side-band signal. If summation or difference combining is performed at the SSB mixer output, it can be shown that the lower band or upper band is produced.
-Phase
Fig. 3.43. Lower side-band suppression.
0O
Fig. 3.45. Upper side-band suppression.
0O
3.3.2 SSB Mixer Circuit Design
3.3.2.1 UWB SSB Mixer Architecture
The block diagram of the UWB SSB mixer implementation is shown in Fig. 3.47, which consists of four mixers, two baluns, negative gain block, and two output combiner. This architecture finally achieve I+/I-/Q+/Q- signals of UWB 14 bands as shown in Table 3.6. Totally power consumption is 10 mW.
I
Table 3.6 Allocation of UWB 14 bands.
In Fig. 3.47, the structure of DBM is shown as Fig. 3.48 and its simulation summary is as Table 3.7. The structure of balun is shown as Fig. 3.49. The simulation results of phase difference and amplitude difference are shown as Fig. 3.50, Fig. 3.51, Fig. 3.52, and Fig. 3.53. Simulation summary of CGCS balun is as Table 3.8.
OUT - OUT +
IN2
-IN2 +
IN1 + IN1
-Fig. 3.48. Schematic of double balanced mixer.
Table 3.7 Simulation summary of DBM
Vin1 & Vin2 power (dBm)
Vin1 & Vin2 Frequency (MHz) 2112/ 7920 1584/ 7920 1056/ 7920 528/ 7920 1584/ 3960 1056/ 3960 528/ 3960 Power conversion gain (dB) 1.867 2.037 2.267 2.512 3.219 3.629 3.965
P 1dB (dBm) -7.2 -7.3 -7.1 -6.9 -7 -6.8 -6.8
IIP3 (dBm) 0.83 0.91 1.263 1.602 0.727 1.082 1.461
Power consumption (mW) -5
1.12
y
IN
m15=-1.7763.970 Hz m1 Freq=
Fig. 3.51. Amplitude difference of 3.96 GHz and 7.92 GHz.
m12Freq=
Fig. 3.52. Phase difference of 528MHz, 1.056GHz, 1.584GHz, and 2.112GHz.
m15Freq=
m15=0.2161.056 Hz m1 Freq=
Fig. 3.53. Amplitude difference of 528MHz, 1.056GHz, 1.584GHz, and 2.112GHz
Frequency Parameters
Phase difference (degree) 177.319 179.789 178.215 177.151 184.562 177.812 Amplitude difference (dB) 0.825 0.216 0.643 0.81 1.777 1.114
2112MHz 3960MHz 7920MHz 528MHz 1056MHz 1584MHz
Table 3.8 Simulation summary of balun
3.3.2.2 Simulated and Measured Results
In this section, we show the measurement results of the SSB mixer. The measurements were performed with the chip directly mounted on FR4 PCB with SMA connectors. Fig. 3.54 shows the test board with die mounted on printed circuit board (PCB). Fig. 3.55 shows the PCB layout. The chip layout and microphotograph are shown in Fig. 3.56 and Fig. 3.57. The die size is 0.620×0.693 mm2 including pads.
The DC power supplier provide 1.8V dc source to mixer in measurement. This circuit need another DC source to switch negative gain. Power consumption is 10mW.
Fig. 3.54. Die bonded to the PCB.
Fig. 3.55. PCB layout.
VDD GND
GND VDD SW
Out I+
Out
I-Out Q+
Out
Q-IN1 I
IN1 Q
IN2 I
IN2 Q
Fig. 3.56. The chip layout of SSB mixer.
Fig. 3.57. Microphotograph of SSB mixer.
We simulated the overall 14 bands of UWB. List two of them as below. In band 7 (6336MHz：7920-1584 MHz), the sideband rejection ratio is 48dB and carrier rejection ratio is 25dB. In band 13 (9504MHz：7920+1584 MHz), the sideband rejection ratio is 48dB and carrier rejection ratio is 25dB.
Fig. 3.58. Output waveform of band 7.
ts(var("VI+")), mVts(var("VI-")), mVts(var("VQ+")), mVts(var("VQ-")), mV
Fig. 3.60. Output waveform of band 13.
Fig. 3.61. Output spectrum of band 13.
Finally, the overall 14 bands output spectrums of UWB are measured. The DC power supplier provides two 1.8V dc source to VDD and switch in measurement. Fig.
3.62 shows the measurement setup of SSB mixer. The microstrip quadrature hybrid of 528MHz, 3960MHz, and 7920MHz are simulated by IE3D and made as shown in Fig.
3.63, Fig. 3.64, and Fig. 3.65. The quadrature hybrid of 2112 MHz, 1584 MHz, and 1056 MHz are provided by CIC (1~12.4G/ 90O KRYTAR/ Model 1230). List measured output spectrum as shown in Fig. 3.66, Fig. 3.67, Fig. 3.68, and Fig. 3.69.
m28freq=
dBm(var("VQ-")) 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 3800 400
-100
ts(var("VI+")), mVts(var("VI-")), mVts(var("VQ+")), mVts(var("VQ-")), mV
SSB Mixer
(PCB measurement)
Quadrature Hybrid
DC BLOCK
Frequency 1 input DC supply
1.8V
Switch 1.8V or 0V
Quadrature Hybrid
DC BLOCK
Frequency 2 input DC
BLOCK Output I+
Output
I-Output Q+
Output
Q-Fig. 3.62. Measurement setup of SSB mixer.
Fig. 3.63. The quadrature hybrid of 528MHz.
Fig. 3.64. The quadrature hybrid of 3960MHz.
Fig. 3.65. The quadrature hybrid of 7920MHz.
Fig. 3.66. Output spectrum of band 1.
Fig. 3.67. Output spectrum of band 2
Fig. 3.68. Output spectrum of band 7.
Fig. 3.69. Output spectrum of band 10.
3.3.3 Performance Summary
The single side band mixer using CMOS TSMC 0.18um is designed. This circuit is designed for UWB synthesizer. In this design, we use high linearity transconductor to improve linearity, and use the SSB mixer architecture to suppress side band. We adopt negative gain block to select upper side band or lower side band. From measurement results, output signal is too small and the input feedthrough to output is serious. The simulation and measurement summary is shown as Table 3.9. The sideband rejection performance is worse. This seems cause by unmatched off-chip output buffer.
Parameters Simulation Measurement Process
Supply voltage Ouptut frequency
Spurious < -20 dBc < -10 dBc
Sideband suppression Worst case ：48dBc Worst case ：10dBc Power consumption 10.278 mW 10.8mW
Die area (mm2)
TSMC 0.18um CMOS 1.8 V
UWB Band 1 ~ Band 14
0.620 X 0.693 ( active area: 0.303 X 0.456 )
Table 3.9 Simulation and measurement summary
Chapter 4 The Design of 24 GHz Voltage-Controlled Oscillator and Phase-Locked Loop
In this chapter, two kinds of 24 GHz voltage-controlled oscillator (VCO) and one kind of 24 GHz phase-locked loop (PLL) for collision avoidance radar system are presented.
4.1 The Design of 24 GHz VCO 01
In this section, design, implementation, and simulation of 24 GHz LC VCO with differential signal generation is presented. First, the design and analysis of the proposed VCO is introduced. Then, the simulation results are discussed. Finally, comparison and summary are presented.
4.1.1 Circuit Topology
4.1.1.1 The Current-Reuse LC VCO
Several LC VCO topologies have been proposed in past and present literature, such as NMOS-pair cross-coupled LC VCO, PMOS-pair cross-coupled LC VCO, and NMOS-pair & PMOS-pair cross-coupled LC VCO. Fig. 4.1, Fig. 4.2, and Fig. 4.3 show three such kinds of VCOs with a current source. The symmetric topologies have
the advantage that they create the symmetric waveforms and could reduce the l/f noise up conversion [37]. If there is no current source in VCO, the VCO has the benefit of better phase noise. A widely known oscillator is the conventional differential
the advantage that they create the symmetric waveforms and could reduce the l/f noise up conversion [37]. If there is no current source in VCO, the VCO has the benefit of better phase noise. A widely known oscillator is the conventional differential