Design of the Wideband Mixer with Broadband Active Balun

Fig. 3.24. shows the mixer core, which is composed of an LC folded cascode mixer and a feedforward compensated differential transconductor. Their design and analysis is described in section 3.1.

IF + RF

LO -VDD

RF +

LO +

IF -Vbias

M1 M2

M3 M4

M5 M6 M7 M8

Fig. 3.24. Schematic of the mixer core.

3.2.2.2 Proposed Wideband Mixer Topology

Fig. 3.25 illustrates the block diagram of the proposed wideband mixer. It includes mixer core, active baluns, and output buffer. Mixer core is the LC folded cascode mixer with modified differential transconductor. Active baluns are modified CSCG balun for generating balanced RF and LO signals to double balanced Gilbert mixer. Output buffer is differential amplifier and common-source amplifier for testing and matching purposes. All ports are single input and single output. This circuit can directly combine with frond-end and back-end circuits. The circuit schematic of the proposed wideband mixer is shown in Fig. 3.26.

RF +

RF -IF +

IF -LO + LO

-Output Buffer

RF IF

LO

Modified CGCS

Balun

Double Balanced

Mixer

Fig. 3.25. Block diagram of the proposed wideband mixer.

IF

VDD

M1 M2

M3 M4 M5 M6 M7 M8

RF

LO

Fig. 3.26. Complete Schematic of the proposed wideband mixer.

3.2.3 Simulation and Measurement Results

In this section, we show the measurement setups and results of the proposed mixer. The measurements were performed with the chip directly mounted on a 26×26 mm² and thickness of 20 mil RO4003 microwave substrate with SMA connectors. Fig.

3.27 shows the test board with die mounted on RO4003 printed circuit board (PCB).

Fig. 3.28 shows the PCB layout. The chip layout and microphotograph are shown in Fig. 3.29 and Fig. 3.30. The die size is 0.85^×0.57 mm2 including pads. Fig. 3.31 shows the measurement setup of power conversion gain. The DC power supplier provide 1.8V dc source to mixer in measurement. The connectors and lines both result in loss in measurement.

RF LO

IF VDD

VDD GND

Fig. 3.27. Die bonded to the PCB.

Fig. 3.28. PCB layout of the proposed mixer.

GND GND

GND GND

VDD VDD

VDD RF

IF

LO

Fig. 3.29. The chip layout of the proposed mixer.

Fig. 3.30. Microphotograph of the proposed mixer.

Fig. 3.31. Measurement setup of power conversion gain.

The mixer is designed using TSMC 0.18μm CMOS technology. All measurements were done at 1.8 V supply voltage and the power consumption is 25.7 mW including the output buffer. The power consumption of output buffer is 14.5 mW.

Fig. 3.32 illustrates the conversion gain versus the RF frequency with both RF and LO ports swept in frequency from 2 to 12 GHz, a fixed IF frequency of 50 MHz, RF power of -30 dBm, and LO power of -5 dBm. The flat conversion gain is 6.9 ± 1.5dB with a bandwidth of 2 to 11.5 GHz. Simulation1 means the bond wire equivalent model is using 20mil. But it’s not 20mil actually. Simulation2 is the practical bond wire length approximate calculated from the chip. The measured RF return loss is better than 10 dB as shown in Fig. 3.33. The measured LO and IF return loss are also better than 10dB as shown in Fig. 3.34 and Fig. 3.35. The measured RF-to-IF, LO-to-IF and RF-to-LO isolation shown in Fig. 3.36. are better than 20 dB. Fig. 3.37 and Fig. 3.38 are P1dB and IIP3 when RF frequency is 8GHz. Fig. 3.39 and and Fig.

3.40 show the linearity of the mixer as a function of frequency. The measured IIP3 is 1.8 ~ 6.5 dBm and P1dB is -3.5 ~ -8.5 dBm in the bandwidth of 2 to 11.5 GHz. Table 3.4 shows the performance summary of simulated and measured results.

DC Block DC Block

DC Block

Signal Generator Signal

Generator

Spectrum Analyzer

RF LO

IF

VDD

VDD GND

2 4 6 8 10 12 14

Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result

Power Conversion Gain (dB)

RF Frequency (GHz)

Fig. 3.32. Simulated and measured power conversion gain versus RF frequency with the IF frequency is 50MHz, RF power is -30dBm, and LO power is -5 dBm.

0 2 4 6 8 10 12 14

RF return loss (dB)

Frequency (GHz) Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result

Fig. 3.33. Simulated and measured RF return loss versus RF frequency.

0 2 4 6 8 10 12 14

Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result

LO return loss (dB)

Frequency (GHz)

Fig. 3.34. Simulated and measured LO return loss versus LO frequency.

0 200 400 600 800 1000 1200

IF return loss (dB)

Frequency (MHz)

Fig. 3.35. Simulated and measured IF return loss versus IF frequency.

2 4 6 8 10 12 14

Fig. 3.36. Measured Isolation versus RF frequency.

-30 -25 -20 -15 -10 -5 0 5 10

Power Conversion Gain (dB)

RF Input Power (dBm) RF frequency : 8 GHz

IF frequency: 50 MHz LO frequemcy : 7.95 GHz LO power : -5 dBm

P1dB: -7dBm

Fig. 3.37. Measured Power Conversion Gain versus RF input power, RF: 8GHz, LO:

7.95GHz.

-35 -30 -25 -20 -15 -10 -5 0 5 10 15

RF1 frequency : 8.001 GHz RF2 frequency : 8 GHz LO frequemcy : 7.9505 GHz LO power : -5 dBm

Output Power (dBm)

RF Input Power (dBm) Main Signal Power

3rd order IM Power

IIP3: 3.5dBm

Fig. 3.38. Measured IIP3 curves, gain:+7.6dB, RF: 8 and 8.001 GHz, LO: 7.9505 GHz -5dBm. The input referred IP3 is +3.5dBm.

2 4 6 8 10 12 14

Simulation result1 - 20 mil bondwire Simulation result2 - Modified bondwire Measurement result

Fig. 3.39. Simulated and measured P1dB versus RF frequency.

2 4 6 8 10 12 14

RF input power: -30 dBm LO input power: -5 dBm Simulation result1 - 20 mil bondwire

Simulation result2 - Modified bondwire Measurement result

IIP3 (dBm)

RF Frequency (GHz)

Fig. 3.40. Simulated and measured IIP3 versus RF frequency.

Parameters Simulation result Measurement result RF Input Return Loss (dB) < -10 < -10

Input P1dB (dBm) -11.3 ～ -8.4 -8.5 ～ -3.5

Table 3.4 Summary of simulation and measurement results

3.2.4 Comparison and Summary

The comparison of the proposed mixer against recently reported wideband mixer is shown in Table 3.5, it indicates that the proposed mixer provides better linearity, more compact chip size, and acceptable conversion gain and power consumption. In Ref. [32], the power consumption of mixer core is 71mW and the RF input return loss is better than 10dB for frequency from 10GHz to 21GHz.

Ref. [30] [31] [32] [33] this work

In this section, a 2 to 11.5 GHz wideband mixer using LC folded cascode mixer topology, modified feedforward compensated differential transconductor, and broadband active balun in TSMC 0.18μm CMOS technology is presented. The LC folded cascode method is used to get enough voltage headroom to work with, and the modified feedforward compensated differential transconductor is adopted to achieve broadband impedance matching and lower the overall distortion. The adoption of broadband active balun in the designed wideband mixer allows providing balance signals for mixer core from single input. The measured results reveal that the proposed mixer achieves power conversion gain of 6.9± 1.5 dB, third-order input intercept point of 6.5 dBm, and input 1-dB compression point of -3.5 dBm in the power consumption of 25.7mW from a 1.8V power supply. The chip area is 0.85 × 0.57 mm². The designed mixer is suitable in the receiver front end of ultra-wideband system.