寬頻混頻器暨24GHz鎖相迴路之互補式金氧半導體射頻積體電路研製

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(1)國立交通大學 電機學院 IC 設計產業研發碩士班 碩 士 論 文. 寬頻混頻器暨 24GHz 鎖相迴路之 互補式金氧半導體射頻積體電路研製 CMOS RFIC Design of Wideband Mixer and 24GHz Phase-Locked Loop. 研 究 生:張唐源 指導教授:鍾世忠. 教授. 中 華 民 國 九 十 六 年 一 月.

(2) 寬頻混頻器暨 24GHz 鎖相迴路之互補式金氧半導體射頻積體電路研製. 學生:張唐源. 指導教授:鍾世忠博士. 國立交通大學電機學院產業研發碩士班. 摘. 要. 本論文分為寬頻混頻器與鎖相迴路兩個部份。利用標準 TSMC 0.18μm RF CMOS 製程完成本論文中所設計的電路。 第一部份設計兩種適用於超寬頻系統的寬頻混頻器與一種用於超寬頻頻率合 成器中的單旁波帶混頻器。第一種寬頻混頻器的頻寬是從 2.4 到 10.7 GHz,此寬 頻混頻器採用的電路架構為 LC 摺疊疊接方式與一個高線性轉導器。第二種寬頻 混頻器的頻寬是從 2 到 11.5 GHz,此寬頻混頻器採用的設計方法為第一種寬頻混 頻器的架構與一個寬頻巴倫,輸入訊號可以單端輸入經過巴倫後產生雙端平衡輸 出。最後設計了一種可以使用於超寬頻頻率合成器中的單旁波帶混頻器。 第二部份設計兩種可應用於 24GHz 汽車防撞雷達系統之壓控振盪器與一種可 應用於 24GHz 防撞雷達系統之鎖相迴路。第一種振盪器採用的設計方法為電流 再利用架構、二倍頻過濾、與二次諧波 LC tank。模擬結果頻率可調範圍為 23.32GHz ~ 24.92GHz , 功 率 消 耗 為 10mW , 相 位 雜 訊 在 1MHz offset 為 -111.3dBc/Hz,輸出功率約-0.35dBm。第二種振盪器採用的設計方法為電流再利 用架構、二倍頻過濾、與 T 型濾波器。模擬結果頻率可調範圍為 23.32GHz~ 24.78GHz,功率消耗為 9.9mW,相位雜訊在 1MHz offset 為-111.6dBc/Hz,輸出 功率約-0.68dBm。最後,設計的鎖相迴路輸出頻率為 24GHz,模擬結果頻率可調 範圍為 22.78GHz~26.91GHz,功率消耗為 26mW,相位雜訊在 1MHz offset 為 -102dBc/Hz,PLL 輸出功率約-12dBm。. I.

(3) CMOS RFIC Design of Wideband Mixer and 24GHz Phase-Locked Loop. student:Tang-Yuan Chang. Advisors:Dr. Shyh-Jong Chung. Industrial Technology R & D Master Program of Electrical and Computer Engineering College National Chiao Tung University. ABSTRACT. The thesis consists of two parts: wideband mixer and phase-locked loop. These proposed circuits are fabricated using a standard TSMC 0.18μm RF CMOS process technology. The first part designs two kinds of wideband mixer for UWB systems and one kind of single-sideband mixer for UWB synthesizer. The bandwidth of the first wideband down conversion mixer is from 2.4 to 10.7 GHz. This mixer adopts a LC folded cascode structure and a feedforward compensated high-linearity differential transconductor. The bandwidth of the second wideband mixer is designed from 2 to 11.5 GHz. The adoption of broadband active balun allows providing balance signals for mixer core from single input. Finally, the single-sideband mixer designed for UWB synthesizer is presented. The second part designs two kinds of 24 GHz voltage-controlled oscillator and one kind of 24 GHz phase-locked loop for collision avoidance radar system. The first VCO adopted current-reuse topology, tail filtering inductor, and 2nd harmonic LC tank. The simulation result shows the achieved phase noise of -111.3 dBc/Hz at 1MHz offset. The tuning range is from 23.32GHz to 24.92GHz. The second VCO adopted current-reuse topology, tail filtering inductor, and T-structure filter. The simulation result shows the achieved phase noise of -111.6 dBc/Hz at 1MHz offset. The tuning range is from 23.32GHz to 24.782GHz. Finally, a 24 GHz fully integrated PLL is designed. The simulated closed-loop lock time is 2us. The PLL output power is -12dBm with a power dissipation of 26 mW, while exhibiting a phase noise of -102 dBc/Hz at 1MHz offset from the carrier. II.

(4) 誌謝 在這二年的研究所學習過程中,衷心的感謝指導教授鍾世忠教授的指導,感 謝指導教授在這兩年內給予非常大的自由度,並且在廣大的思考空間內不斷的指 引正確的方向,使我在高頻晶片設計領域獲益良多。也衷心地感謝口試委員孟慶 宗、邱煥凱、黃天偉教授在畢業口試時不吝指正與提供寶貴的意見。. 此外,最感謝的是父母親與家人的支持、關懷、與無怨無悔的付出,好友們 的支持鼓勵,使我得以順利完成研究所學業。. 最後,感謝電資 810 研究室的夥伴們,感謝 RFIC 達人-佩宗、超強的清標、 口才超好的竣義、天建、顯鴻、郁娟、敦智、克強、淑君、煥能、泓偉、永旭、 菁偉、懷文、奕慶、豐吉以及幫助過我的人,感謝大家陪我度過研究所的美好時 光,也豐富了我的研究生生活。. 總之,要感謝的人實在太多,對於所有曾經幫助我的人及與我相遇過的人,在 此一致併上我由衷的感謝,感謝你們,也祝福你們。. III.

(5) CONTENTS ABSTRACT (CHINESE)...................................................................................Ⅰ ABSTRACT (ENGLISH)………………………………………………….......Ⅱ ACKNOWLEDGEMENT..................................................................................Ⅲ CONTENTS............................................................................................................Ⅳ LIST OF TABLES................................................................................................ Ⅶ LIST OF FIGURES..........................................................................................VIII. Chapter1 Introduction. 1. 1.1 Motivation........…...............…..…………………………………………………...1 1.2 Research Results in RFIC Design….……………………………………………...2 1.3 Thesis Organization.……………………………………………………………….2. Chapter2 General Backgrounds. 3. 2.1 The Direct Conversion Receiver………………………………………………….3 2.2 Mixer Fundamentals……………..……………………………………………….5 2.2.1 Principles of Mixer………………………………….………………………………………...5 2.2.2 Performance Parameters…………………………..…………………………………………...6 2.2.3 Mixer Architecture…………………………….………………..……………………………...9. 2.3 Active Balun Fundamentals…………………………………………………….11 2.4 Voltage-Controlled Oscillator…………………………………………………....13 2.4.1 Principles of VCO.……………………………….………………………………………...13 2.4.2 Performance Parameters…………………………..………………………………………...17 2.4.3 Noise Model of VCO..……………………….……………………………………………...18 IV.

(6) 2.5 Phase-Locked Loop Fundamentals……………………………………………....24 2.5.1 Principles of PLL.……………………………….………………………………………...24 2.5.2 Noise Model in the PLL System.………………..………………………………………...28. 2.6 The 24 GHz Radar System……….……………………………………………....33. Chapter3 The Design of Wideband Mixer. 34. 3.1 The Design of Wideband Down Conversion Mixer (Mixer 01)…………………34 3.1.1 Feedforward Compensated Differential Tansconductor Analysis…………………………...34 3.1.2 LC Folded Cascode Mixer…………………………………………………………………..38 3.1.3 Proposed Mixer Design……………………………………….……………………………..39 3.1.4 Simulation and Measurement Results……………………..………………………………..40 3.1.5 Comparison and Summary…………………………………………………………………..45. 3.2 The Design of Wideband Mixer with Broadband Active Balun (Mixer 02)……46 3.2.1 Broadband Active Balun Design………………………………………..…………………...46 3.2.2 Design of the Wideband Mixer with Broadband Active Balun……………………………...56 3.2.3 Simulation and Measurement Results…………………………..…………………………..57 3.2.4 Comparison and Summary…………………………………………………………………..63. 3.3 The Design of Single-Sideband Mixer for UWB Synthesizer…………………65 3.3.1 Principle of SSB Mixer………………………………….………………………..………...65 3.3.2 SSB Mixer Circuit Design………………………….…..…………………………………..68 3.3.3 Performance Summary….……………………………..……………………………………..77. Chapter4 The Design of 24 GHz VCO and PLL. 78. 4.1 The Design of 24 GHz VCO 01…………………………………………………78 4.1.1 Circuit Topology………………………………….………………………………………...78 4.1.2 Simulated Performance………………………………..……………………………………..85 4.1.3 Comparison and Summary………………………………..…………………………………..89. V.

(7) 4.2 The Design of 24 GHz VCO 02…………………………………………..……91 4.2.1 Circuit Topology…………………………….……….……………………………………...91 4.2.2 Simulated Performance…………………………..…………………………………………..93 4.2.3 Comparison and Summary…………………………….……………………………………..96. 4.3 The Design of 24 GHz PLL……………………………………………………98 4.3.1 Phase-Locked Loop Design……………………..……………………………………..…...98 4.3.2 Simulated Results…………………………………...……………………………………..105 4.3.3 Summary………………………………..………..………………………………………..113. Chapter5 Conclusion. 115. REFERENCES.....................................................................................................117. VI.

(8) LIST OF TABLES. Table 3.1 Table 3.2 Table 3.3 Table 3.4 Table 3.5 Table 3.6 Table 3.7 Table 3.8 Table 3.9. Summary of simulation and measurement results (Mixer 01)……….....44 Summary of the comparison (Mixer 01)……………..…..…………45 Comparison of CMOS active baluns………………………....…………48 Summary of simulation and measurement results (Mixer 02)………….63 Summary of the comparison (Mixer 02)…………………..……………63 Allocation of UWB 14 bands……………..……………..………..……69 Simulation summary of DBM…….……..………………..……………69 Simulation summary of balun………..………………….…………......71 Simulation and measurement summary (SSB)…………..………..……77. Table 4.1 Summary of VCO 01 simulation results..………………..……………89 Table 4.2 Summary of the comparison (VCO 01)…………………..………..……90 Table 4.3 Table 4.4 Table 4.5 Table 4.6 Table 4.7. Summary of VCO 02 simulation results..….………..……..……………96 Summary of the comparison (VCO 02)…………………..………..……96 Summary of simulation results ……………………………..…………107 Summary of the comparison ……………………………..……………108 Summary of simulation results (PLL)……..………………..…………113. VII.

(9) LIST OF FIGURES. Fig. 2.1. Fig. 2.2. Fig. 2.3. Fig. 2.4. Fig. 2.5. Fig. 2.6. Fig. 2.7. Fig. 2.8. Fig. 2.9 Fig. 2.10. Fig. 2.11. Fig. 2.12. Fig. 2.13. Fig. 2.14. Fig. 2.15. Fig. 2.16. Fig. 2.17. Fig. 2.18. Fig. 2.19. Fig. 2.20. Fig. 2.21. Fig. 2.22. Fig. 2.23. Fig. 2.24. Fig. 2.25. Fig. 2.26. Fig. 2.27. Fig. 2.28. Fig. 2.29. Fig. 2.30. Fig. 2.31. Fig. 2.32. Fig. 2.33. Fig. 2.34.. Block diagram of direct conversion receiver architecture.….….4 LO signal leakage.……………………...........…………………….5 A strong interferer signal leakage.……………………………….5 Even order distortion………………………………….…………...5 P1dB……………………….………………………………………….8 IIP3…………………………..………….………………..……………8 Passive mixer..………………….….…………………………………9 Active mixer……………………...…………………………………...9 The prototype of the CMOS Gilbert mixer………………...10 Common source topology.………………………………………..……12 Common gate cascaded with common source…………………….…12 Differential topology.…………………………………………………12 Differential amplifier balun.…………………………………………13 Multi-tanh doublet type balun.……………………………………...13 Push-pull balun.……………………………………………………..13 Phase noise in receiver……………………………………………..14 Negative resistance and LC tank resistance………………………..15 Series to parallel.…………..………………………………………..15 Equivalent resonant model.…………………………………………..15 Input impedance of NMOS cross-coupled pair.…………………..15 Complementary cross-coupled pair…………………………………..16 Ring oscillator..……………………………………………………..16 Output spectrum of ideal and actual oscillators…………………..17 Lesson’s phase noise model………………………………………..18 Impulse current injects into LC tank.……………………………..20 Waveforms for impulse excitation…………………………………..20 Conversion of noise to phase noise sidebands.…………………..23 Block diagram of a basic PLL……………………………………..24 Ideal transfer function of the VCO………………………………..25 PFD response….……………………………………………………..26 PFD state diagram.…………………………………………………..26 Characteristic of an ideal phase detector.…………………………..26 PFD with CP…..……………………………………………………..27 Schematic of second order loop filter.……………………………..28 VIII.

(10) Fig. 2.35. Fig. 2.36. Fig. 2.37. Fig. 2.38. Fig. 2.39. Fig. 3.1. Fig. 3.2. Fig. 3.3. Fig. 3.4. Fig. 3.5. Fig. 3.6. Fig. 3.7. Fig. 3.8. Fig. 3.9. Fig. 3.10. Fig. 3.11. Fig. 3.12. Fig. 3.13. Fig. 3.14. Fig. 3.15. Fig. 3.16. Fig. 3.17. Fig. 3.18. Fig. 3.19. Fig. 3.20. Fig. 3.21. Fig. 3.22. Fig. 3.23. Fig. 3.24. Fig. 3.25. Fig. 3.26.. Noise source of PLL………………………………………………..28 PI type………………………………………………………………..29 Transfer function.……………………………………………………..30 Second order loop filter……………………………………………..31 Block diagram of 24GHz Radar system..…………………………..33 Modified differential transconductor.……………………………35 LC folded cascode mixer with an added resistance.…………39 Schematic of the proposed mixer………………………………..39 Die bonded to the PCB.……………………………………………40 PCB layout of the proposed mixer.………………………………40 The chip layout of the proposed mixer.…………………………..41 Microphotograph of the proposed mixer.…………...…………….41 Measurement setup of power conversion gain.…………………..41 Simulated and measured power conversion gain………….……..42 Simulated and measured RF return loss………………………………..43 Simulated and measured IF return loss………………………………..43 Measured Isolation….…………………………………………………..43 Simulated and measured P1dB………………………………………..44 Simulated and measured IIP3…………………………………………..44 Schematic of the proposed broadband active balun.…………………..46 Input impedance matching.…………..………………………………....47 Simulated amplitude balance and phase difference……………………..47 Circuits of two types Balun.……………………………………………..48 Small-signal equivalent circuit model of common-source.……………..49 Small-signal equivalent model neglecting Cgs.………………………..49 Small-signal equivalent circuit model of common-gate………………..51 Small-signal equivalent circuit model of cascode common-gate.……....53 Simulated phase differences.……………….……………………………55 Schematic of the mixer core.…………………………………….............56 Block diagram of the proposed wideband mixer.……………………….57 Complete Schematic of the proposed wideband mixer.………………...57. Fig. 3.27. Fig. 3.28. Fig. 3.29. Fig. 3.30. Fig. 3.31. Fig. 3.32. Fig. 3.33.. Die bonded to the PCB…..……………………………………….……..58 PCB layout of the proposed mixer…………….….……………………58 The chip layout of the proposed mixer.…………….…………………..58 Microphotograph of the proposed mixer.…………………………….….58 Measurement setup of power conversion gain…..……………………..59 Simulated and measured power conversion gain……………………….60 Simulated and measured RF return loss………………………………..60 IX.

(11) Fig. 3.34. Fig. 3.35. Fig. 3.36. Fig. 3.37. Fig. 3.38. Fig. 3.39. Fig. 3.40. Fig. 3.41. Fig. 3.42. Fig. 3.43. Fig. 3.44. Fig. 3.45. Fig. 3.46. Fig. 3.47. Fig. 3.48.. Simulated and measured LO return loss………………………………..60 Simulated and measured IF return loss….……………………………...61 Measured Isolation…..………..………………………………………...61 Measured Power Conversion Gain at RF= 8GHz…..…………………...61 Measured IIP3 curves at RF= 8GHz…………….……………………..62 Simulated and measured P1dB……………………..…………………...62 Simulated and measured IIP3...………………………………………...62 Principle of SSB mixer: frequency summation.……………………....65 Principle of SSB mixer: frequency difference.………………………...66 Lower side-band suppression.…………………………………………...67 LSB remove…....…….………………………………………………….67 Upper side-band suppression..…………………………………………67 USB remove.………………………………..…………………………...68 UWB SSB mixer architecture.…………………………………………68 Schematic of double balanced mixer.………………………….……...69. Fig. 3.49. Fig. 3.50. Fig. 3.51. Fig. 3.52. Fig. 3.53. Fig. 3.54. Fig. 3.55. Fig. 3.56. Fig. 3.57. Fig. 3.58. Fig. 3.59. Fig. 3.60. Fig. 3.61. Fig. 3.62. Fig. 3.63. Fig. 3.64. Fig. 3.65. Fig. 3.66. Fig. 3.67. Fig. 3.68. Fig. 3.69. Fig. 4.1. Fig. 4.2.. Schematic of CGCS Balun.……….……………………………………70 Phase difference of 3.96 GHz and 7.92 GHz.…………………………...70 Amplitude difference of 3.96 GHz and 7.92 GHz.…………………….70 Phase difference of 528MHz, 1.056GHz, 1.584GHz, and 2.112GHz...71 Amplitude difference of 0.528, 1.056, 1.584, and 2.112GHz……….71 Die bonded to the PCB.………………………………………………...72 PCB layout………………………..….…………………………………72 The chip layout of SSB mixer……..….………………………………72 Microphotograph of SSB mixer…..…………………….……………..73 Output waveform of band 7..…………………………………………....73 Output spectrum of band 7.…………………………………………….73 Output waveform of band 13.….…………………………………….....74 Output spectrum of band 13…………….……………………………....74 Measurement setup of SSB mixer.……………………………………..75 The quadrature hybrid of 528MHz.…………………………………....75 The quadrature hybrid of 3960MHz.………………………………….75 The quadrature hybrid of 7920MHz.……….…………………………75 Output spectrum of band 1……………………………………...…....75 Output spectrum of band 2……..………….……….………………..76 Output spectrum of band 7.….………………………………………76 Output spectrum of band 10.……………………………………….…76 NMOS-pair cross-coupled LC VCO.…………………………….79 PMOS-pair cross-coupled LC VCO.……………………………...80 X.

(12) Fig. 4.3. Fig. 4.4. Fig. 4.5. Fig. 4.6. Fig. 4.7. Fig. 4.8. Fig. 4.9. Fig. 4.10. Fig. 4.11. Fig. 4.12. Fig. 4.13. Fig. 4.14. Fig. 4.15. Fig. 4.16. Fig. 4.17. Fig. 4.18. Fig. 4.19. Fig. 4.20. Fig. 4.21. Fig. 4.22. Fig. 4.23. Fig. 4.24. Fig. 4.25. Fig. 4.26. Fig. 4.27. Fig. 4.28. Fig. 4.29. Fig. 4.30. Fig. 4.31. Fig. 4.32. Fig. 4.33. Fig. 4.34. Fig. 4.35. Fig. 4.36. Fig. 4.37. Fig. 4.38. Fig. 4.39. Fig. 4.40.. NMOS-pair & PMOS-pair cross-coupled LC VCO.….…………80 NMOS & PMOS pair LC VCO.……………………..……………81 Current-reuse LC VCO by Seok-Ju Yun [38].……………………81 Current-reuse LC LC VCO by Zheng Wang [39].…………….…81 Voltage-biased VCO with noise filter.…………………………….83 Proposed 24 GHz VCO 01...……………………………………...84 Main LC tank and 2nd LC tank………………………..…………85 Simulated results of main and second harmonic LC tanks.……………85 Simulated result of total LC tank………………………………………85 Layout of the proposed VCO 01..………………………………………86 EM consideration...…………..……………………………………….…86 Output spectrum at 24GHz…………………………………………….87 Phase noise of the VCO at 24GHz.…………………………………...87 Transient response of the VCO.………………………………………87 Control voltage versus output frequency.……………………………88 Control voltage versus output power..………………………………88 Simulated phase noise results for each technique.……………….…88 Proposed 24 GHz VCO 02………………………………………….91 T-Structure filter consists of LC.…………………………………...92 Main LC tank and T structure filter……………….………………92 Simulated result of magnitude of the S parameter.………………92 Layout of the proposed VCO 02.……………………………………93 EM consideration.…………….………………………………………94 Output spectrum at 24GHz.……………………………………….…94 Phase noise of the VCO at 24GHz.……………….……………….94 Transient response of the VCO.…………………..…………………...95 Control voltage versus output frequency.………………………………95 Control voltage versus output power.…………………………………95 Simulated phase noise results for each technique.……………………96 Simulated summary of phase noise reduction technique…………….…97 Proposed PLL architecture………………………………………….…98 VCO core schematic………………..………………………………….99 Block diagram of the Prescaler.……………………………………...99 Schematic of a CML latch.…………………………………………100 Schematic of prescaler.………………………………………………100 Block diagram of divider-by-256.……………………………………101 Schematic of master-slave divider..……..……………………….…102 Schematic of TSPC divider……..………………………………….102 XI.

(13) Fig. 4.41. Fig. 4.42. Fig. 4.43. Fig. 4.44. Fig. 4.45. Fig. 4.46. Fig. 4.47. Fig. 4.48. Fig. 4.49. Fig. 4.50. Fig. 4.51. Fig. 4.52. Fig. 4.53. Fig. 4.54. Fig. 4.55. Fig. 4.56. Fig. 4.57. Fig. 4.58. Fig. 4.59. Fig. 4.60.. Schematic of conventional PFD.…………………………………...103 Schematic of precharge-type PFD.…………………………………103 Schematic of conventional CP.……………………………………104 Schematic of modified CP.….………………………………………104 Schematic of second order loop filter.………………………….…105 Output spectrum at 24GHz……….………………………………….106 Phase noise of the VCO at 24GHz.………………………………...106 Transient response of the VCO.………………………………………106 Control voltage versus output frequency.……………………………107 Control voltage versus output power…………………………………107 Spectrum after prescaler…………………………………………….…108 Spectrum after each divider……….………………………………….109 The SIMULINK model for PLL architecture simulation…..……...110 Lock time simulation by Matlab simulink.…………………………110 Settling time simulation by Matlab simulink.………………………111 PLL output1 return loss……………………….……………………111 Spectrum of the PLL’s output as locking.…….…………………112 Transistor level simulation of lock time.……………………….…112 Initial and steady state of control voltage……………………….112 The layout of 24 GHz PLL………………………………………...113. XII.

(14) Chapter 1 Introduction. Chapter 1 Introduction. 1.1 Motivation Recently the wireless communication becomes more and more popular. The wireless communication systems must be portable, low cost, high performance, highly integration, low power and small size. All of these constraints combine to make the design quite challenging. One approach to reach the requirements for wireless communication is CMOS technology. The CMOS circuits have many drawbacks such as noisy and low current driving capability. But with the rapid scaling of CMOS process technologies, it has dramatically improved CMOS performance and achieving frequency of gigahertz. In addition, CMOS offers low power and highly integration. For these reasons, many papers of CMOS RF circuits have been published. Based on the CMOS RFIC advantages of integrated with baseband circuits, more transceiver circuits are realized by using CMOS process. Therefore, CMOS RFIC becomes a new trend for the wireless communication system. The goal of this thesis is to research the radio frequency circuits in CMOS process technology. In this thesis, we focus on mixer, voltage-controlled oscillator (VCO), and phase-locked loop (PLL). A modified mixer is used to minimize the nonlinear distortion. The main problem of VCO is to improve phase noise. We will describe how to improve it in later chapters. PLL has played an important role in 1.

(15) Chapter 1 Introduction. wireless communication receivers. PLL is used in many different applications such as clock and data recovery, synchronization, frequency synthesis, modulator, and demodulator. The PLL often consumes a large percentage of the total power in wireless communication receivers. Hence, a CMOS PLL with on-chip LC-tank VCO will be discussed in this thesis.. 1.2 Research Results in RFIC Design The research results in RFIC design are as below table. This thesis is focus on these circuits. These circuits are simulated using Agilent ADS and fabricated in tsmc 0.18μm RF CMOS process.. Tapeout Number. Circuit Name. 2. Chip Size (mm ). A Wideband Down-Conversion Mixer in 0.18-μm CMOS Technology for Ultra-wideband Applications. 0.70 Ⅹ 0.58. T18-95C- 117. A UWB Single-Sideband Mixer for Frequency Synthesizer. 0.62 Ⅹ 0.69. T18-95D- 57. A Wideband CMOS Down Conversion Mixer with Broadband Active Balun. 0.85 Ⅹ 0.57. T18-95E- 116. Design of 24GHz VCO for Collision Avoidance Radar. 1.03 Ⅹ 0.92. T18-96A- 41. A 24GHz Current-Reuse CMOS Differential LC-VCO. 0.90 Ⅹ 0.93. T18-96A- 114. Design of 24GHz PLL. 1.25 Ⅹ 1.15. T18-95B-49. 1.3 Thesis Organization This thesis is organized into 5 chapters. This chapter is the first one. In Chapter 2, we will introduce the fundamentals of mixer, voltage-controlled oscillator, and phase-locked loop. Chapter 3 is a main chapter that has the implement of the wideband mixer and broadband active balun. This chapter encompasses the detailed analysis of the proposed circuits. The simulation and measurement results will be included. Chapter 4 is focus on design of the voltage-controlled oscillator and phase-locked loop. Also, the simulation results will be included. At last, the conclusion is made in chapter 5.. 2.

(16) Chapter 2 General Backgrounds. Chapter 2 General Backgrounds. In this chapter, we will introduce the fundamentals of direct conversion receiver, mixer, active balun, voltage-controlled oscillator, phase-locked loop, and 24GHz radar system.. 2.1 The Direct Conversion Receiver Because of the rapid growth in demand for broadband wireless communications, wireless local area networks (WLAN) are becoming more attractive not only to exchange large amount of data locally but also as access points for the cellular infrastructure. The superheterodyne has been the architecture of choice for wireless transceivers for many years. On the other hand, due to the increase of the integration level of RF front-ends, alternative architectures, targeting reduced power consumption and minimization of the number of off-chip components, have been considered, in the recent past. Among them, the direct conversion receiver (DCR) or zero-IF receiver has increasingly gained widespread attention due to its potentially of low power consumption, lower complexity, low manufacturing costs, and easy integrating with the baseband circuits [1]-[5]. Fig. 2.1 shows the block diagram of the direct conversion RF front-end, where the LO frequency is equal (or approximate) to input carrier frequency and the LO will translate the center of the desired signal to zero IF or low IF. 3.

(17) Chapter 2 General Backgrounds. Mixer. LPF. Baseband ADC. I. RF Filter. I. LNA 90. VCO 0. LPF. Baseband ADC. Q. Q. Mixer. Fig. 2.1.. Block diagram of direct conversion receiver architecture.. The most important advantage of the direct conversion receiver is that the intermediate frequency (IF) passband filter can be neglected and replaced by a low pass filter. Low pass filter is much easier to integrate in standard semiconductor technology. However, some issues which do not exist or are not serious in the heterodyne architecture become critical in the direct conversion receiver. These drawback include DC offset, flicker noise, even order distortion, I/Q mismatch, and so on. Among these the DC offset generated by self-mixing is the most critical. The DC offset is caused by carrier leakage from the local oscillator to the mixer input and to the antenna as shown in Fig. 2.2. Interferer leakage will also cause a DC offset at the mixer output as shown in Fig. 2.3. To overcome the drawback of DC offset, the improving isolation between LO and RF ports is important. The second-order intermodulation distortion (IMD2) is a fundamental problem, because the second-order intermodulation term interferes the reception of the wanted signal as shown in Fig. 2.4. In a perfectly balanced Gilbert cell mixer, the IMD2 is a common-mode signal and therefore does not a serious problem. However, due to the mismatch of device, the balance between the negative and positive branch of the mixer is degraded and the IMD2 becomes a problem. About I/Q mismatch, if the modulation is complex modulation, the I/Q mismatch can equal to image interferer. This mismatches between the amplitudes of the I and Q signal corrupt the constellation of the down converted signal. Therefore influences the bit error rate. Finally, flicker noise or l/f-noise may be a problem in the mixer and subsequent filter because the signal is converted directly to baseband.. 4.

(18) Chapter 2 General Backgrounds. RF Filter. LNA. Mixer. Baseband ADC. LPF. coswt. Fig. 2.2.. RF Filter. LNA. LO signal leakage.. Mixer. LPF. Baseband ADC. coswt. Fig. 2.3.. A strong interferer signal leakage.. LNA IM2. LNA IM3 Mixer IM2. Interferer Desired channel coswt. Fig. 2.4.. Even order distortion.. 2.2 Mixer Fundamentals 2.2.1 Principles of Mixer The mixer is an essential building block in the receivers, which is responsible for frequency up-conversion and down-conversion. It is also an important component associated with the linearity of the front-end receivers. The first stage of mixer must have high linearity to handle the large input signals from LNA without significant intermodulation. Nonlinearity causes many problems, such as cross modulation, 5.

(19) Chapter 2 General Backgrounds. desensitization, harmonic generation, and gain compression, but even-order nonlinearity can be easily reduced by differential architecture. However, odd-order nonlinearity is difficult to be reduced, especially the third-order intermodulation distortion (IMD3). IMD3 is the dominant part of the odd-order nonlinearity. Mixer is a three ports circuit, which are the RF port, the LO port and the IF port. It is a multiplication of two signals which are the RF signal amplified from the low noise amplifier and the signal from the local oscillator (LO) to achieve the function of frequency transformation. This is depicted by equation (2.1). Then the RF signal is down-converted to the intermediate frequency (IF).. ( A cos ω1t )( B cos ω2t ) =. AB ⎡cos (ω1 + ω2 ) t + cos (ω1 − ω2 ) t ⎤⎦ 2 ⎣. (2.1). From the equation (2.1), the multiplication of two signals at the frequencies of ω1 and ω2 together produce signals at the sum (ω1+ω2) and difference (ω1-ω2) frequencies. The amplitudes are proportional to the RF and LO amplitudes. The multiplications in the time domain would result in convolutions in the frequency domain. Thus, the mixer can responsible for frequency translation. In equation (2.1), signals at the frequency of (ω1+ω2) can be easily filtered out because they are far away from desired frequency in the frequency domain. The signals at the frequency of (ω1-ω2) are our desired outputs. In circuit implementations, the multiplication can be achieved by passing the input signal A cos ω t from RF through a switch driven by another signal B cos ω t from LO. If the LO amplitude is constant, any amplitude modulation in the RF signal is transferred to the IF signal. The most important parameters for determining the performance of a mixer are power conversion gain, and linearity.. We will describe these parameters in the. subsequent contents.. 2.2.2 Performance Parameters 2.2.2.1 Conversion Gain One of important parameters of mixer’s characteristics is conversion gain, which is defined as the ratio of the desired IF output to the value of the RF input as shown in equation (2.2). In general, the conversion gain of the mixer has two types: one is voltage conversion gain and the other is power conversion gain.. 6.

(20) Chapter 2 General Backgrounds. Conversion Gain =. The desired output IF power The input RF power. (2.2). Assuming input a sinusoidal signal and the output would include signals at integer multiples of the frequencies of the input signal as equation (2.3). In equation (2.3), the terms with the input frequency are called the fundamental signal, and the higher order terms are called the harmonics. The harmonics would cause performance degradations. VOUT (t ) = α1 ( A cos ωt ) + α 2 ( A cos ωt ) + α 3 ( A cos ωt ) + ...... 2. = α1 ( A cos ωt ) +. α 2 A2 2. 3. (1 + cos 2ωt ) +. α 3 A3 4. ( 3cos ωt + cos 3ωt ) + ....... (2.3). The output function of mixers is a compressive function of input levels. When the input level grows sufficiently high, the output eventually saturates and the conversion gain begins decreasing. If α3 holds a negative value, this phenomenon will happen. At small values of input level A, the second term is negligible and the gain remains constant. The gain starts decreasing when the input level gets large as shown in equation (2.4). Gain = α1 +. α 3 A2 4. (2.4). 2.2.2.2 Linearity The mixers are assumed to be linear and time-invariant. The linearity is a significant parameter in the mixer design. Here we will introduce two parameters of linearity: P1dB and IIP3. The IF output is proportional to the RF input signal amplitude ideally. However, as the input signal becomes large, the output signal fails to exhibit this characteristic. We use the value departing the ideal linear curve 1 dB as the referenced point, 1 dB compression point, shown in Fig. 2.5. The dashed line in Fig. 2.5 shows our desired output characteristics. The solid line shows the real characteristic. The 1dB compression point characterizes the input level where the output level is 1dB less than our desired output level. A higher 1dB compression point stands for a better linearity performance. The linearity of a mixer can also be evaluated by intermodulations. The two-tone third-order intercept is often used to characterize mixer linearity. Ideally, each of two. 7.

(21) Chapter 2 General Backgrounds. different RF input signals will be translated without interacting with each other, and we can only gain the desired IF signal from the output port. However, practical mixers will always exhibit some intermodulation effects. This is because that two or more different frequencies of input signals will degrade the linear region of the system. The third intercept point (IP3) is measured with two tone test. Two tones are closely placed and injected as input simultaneously. If we consider the region where the input level is small, the output characteristic is approximately linear. The third-order intercept is the intersection of these two curves as illustrated in Fig. 2.6 which is the extrapolation of the signal line and the third-order harmonic line. The higher intercept, the more linear.. IF output power 1dB. A 1dB. RF input power. Fig. 2.5. P1dB.. IF output power IF power 3rd intercept point 3rd intermodulation product RF input power. Fig. 2.6. IIP3.. 2.2.2.3 Isolation Another important parameter of mixer is isolation, which shows the interaction among RF, IF and LO ports. The isolation between each two ports of the mixer is 8.

(22) Chapter 2 General Backgrounds. important. The LO to RF feedthrough is means the LO leakage to the LNA and (or) leakage to the antenna. The RF to LO feedthrough allows strong interferers in the RF path to interact with the LO driving the mixer. The LO to IF feedthrough is also important. If substantial LO signal exists at the IF output, the following stage may be desensitized. The feedthrough can be reduced largely by use double balanced mixers. The RF to IF isolation means the signal in the RF path directly appears in the IF. In the homodyne receivers, this is a critical issue with respect to the IMD2 problem.. 2.2.3 Mixer Architecture The implementation of CMOS down-conversion mixer can be passive or active. The simple passive mixer is shown in Fig. 2.7. It is usually using MOS transistor as a switch to modulate the RF signal by LO signal and down convert to IF band. Because passive mixer operates in the linear region, it has high linearity and excellent IIP3. But it provides poor conversion gain and noise figure. The simple active mixer is presented in Fig. 2.8. The active mixer provides better conversion gain than passive mixer. Its conversion gain is decided by the product of the input conductance gm and load impedance to suppress the noise contributed by the subsequent stages. But the linearity of an active mixer is worse than that of a passive mixer. LO. RF. IF. Fig. 2.7.. Passive mixer.. IF. LO RF. Fig. 2.8.. Active mixer. 9.

(23) Chapter 2 General Backgrounds. The Gilbert cell topology is a typical type used in active mixers. The advantages of this topology are the high conversion gain, low LO power, and low offset voltage. The Gilbert cell mixer consists of three stages: transconductor stage, switching stage, and load stage. The linearity of Gilbert mixer is dominated by the transconductor stage as shown in Fig. 2.9.. Load stage. LO +. LO + LO -. RF -. RF +. Fig. 2.9. Switching stage. Transconductor stage. The prototype of the CMOS Gilbert mixer. The function of three stages is described as follow. RF input stage is a differential pair that converts the RF voltage to current. The transconductance of this stage directly affects the linearity and the gain of the mixer. LO switch stage usually applies two differential pairs as modulated switch to construct double balanced structure. To achieve the goal that this two differential pairs completely switch the input power of the LO port must be larger. The value of the LO port also affects the conversion and the noise figure of the system. The output stage is load stage. If the switching stage is ideal switches, the linearity of Gilbert mixer is dominated by the transconductor stage. Third-order input intercept point (IIP3), second-order input intercept point (IIP2), and input 1-dB compression point (P1dB) are the important parameters of linearity. IIP3 and IIP2 are the effects of intermodulation terms in the nonlinear circuits. P1dB is the ceiling of the input power. To improve linearity in Gilbert mixer, many methods have being used such as adding source degeneration resistors below the gain stage [24], bisymmetric Class-AB input stage [23], multiple gated transistor [22], and common-source and common-emitter RF transconductors [25]. 10.

(24) Chapter 2 General Backgrounds. 2.3 Active Balun Fundamentals Double balanced Gilbert mixer needs balanced RF, LO, and IF signals for its optimum operation such as higher conversion gain, good isolation, better dynamic and static offsets, and help improve the second and third order intermodulation rejection [6]–[8]. Therefore, it needs to provide differential signals into double balanced Gilbert mixer. Differential balun (or phase splitter) circuits are the critical block to generate a pair of differential output signals which have balanced amplitude and phase from a single-ended input. There are passive and active baluns in RFICs. Passive components have been used to implement the balun. Passive balun consume no DC power. But the LC networks need many spiral inductors and MIM capacitors. It is unsuitable in integrated circuits due to larger physical size. Since LC networks are narrow band and area consuming, it limits the use of passive baluns. Active baluns are wideband and compact size. It can be used in integrated circuits. Active baluns techniques have been reported in past research. Several types of active balun topologies have already been proposed. There are three configurations normally employed for implementation of active balun circuits: single FET circuits [9],[10], common-gate common-source (CGCS) circuits [11]–[13], and differential amplifier circuits [7],[14]–[17]. The challenge in the active balun design is to maintain the 180O phase difference and 0dB gain difference at high frequency. The common-source single-FET balun is the simplest as shown in Fig. 2.10. Input signal into the gate, ideally the output signals at the drain and source will be out of phase by 180 degrees and have equal amplitude. The common-source single-FET balun has too much phase difference as a result of circuit parasitics. A common-gate cascaded with a common-source circuit provides equal amplitudes split with 1800 phase difference. The CGCS structure provides adequate isolation and accurate phase difference as shown in Fig. 2.11. For a differential topology, an RF signal applied at the input of one of the differential transistors and thereby providing an 1800 phase shift and equal amplitude between the two output signals as shown in Fig. 2.12. .. 11.

(25) Chapter 2 General Backgrounds. Output 1 Input. 180 degree out of phase. Output 2. Fig. 2.10.. Common source topology.. 180 degree out of phase. Output 1. Output 2. Input. Fig. 2.11.. Common gate cascaded with common source.. Output 1 Output 2. Input. 180 degree out of phase. Fig. 2.12.. Differential topology.. There are three simple types of differential to single-ended balun. First, a differential amplifier balun as shown in Figure 2.13. The gain of balun is determined by transconductances, output resistor and degeneration resistor R1. The degeneration resistor introduces noise and consumes some voltage headroom, but its advantage is that improves linearity of the balun. A multi-tanh doublet type balun is shown in Figure 2.14. The push-pull balun consists of a common source and the common drain as shown in Figure 2.15. The degeneration resistor R3 influences the gain. The resistor R2 is included for output impedance matching. 12.

(26) Chapter 2 General Backgrounds. R1. Fig. 2.13.. R1. Differential amplifier balun.. Fig. 2.14. Multi-tanh doublet balun.. R2. R3. Fig. 2.15.. Push-pull balun.. 2.4 Voltage-Controlled Oscillator 2.4.1 Principles of VCO Voltage controlled oscillator is essential building block in communication systems. The VCO is used as local oscillator to up-conversion or down-conversion 13.

(27) Chapter 2 General Backgrounds. signals. The phase noise is the main critical parameters for VCO. Therefore, how to get better phase noise is the most important. Oscillator can transfer DC power to AC power. Oscillator is an energy transfer device. For steady oscillation, the self-oscillating system must be satisfied Barkhausen’s criteria: H ( jω0 ) = 1 and ∠H ( jω0 ) = 00 (or 1800 of dc feedback is negative). There are two types of analysis methods: positive feedback and negative resistance. In the design of oscillator, the important performance parameters are phase noise, output power, tuning range, and thermal stability. Among these parameters, the most important is the phase noise. Phase noise will influence the signal quality in receiver as shown in Fig. 2.16. When a strong unwanted adjacent channel signal and a weak wanted signal input receiver, worse phase noise will interfere other signal and intermodulation to IF. This interfere the weak wanted signal. Thus, phase noise is the most important in VCO design.. Fig. 2.16. Phase noise in receiver. LC tank voltage-controlled oscillator and ring oscillator are the two most popular circuits in VCO design. LC tank voltage-controlled oscillator has better phase noise, but tuning range is narrow. Ring oscillator has wider tuning range, but phase noise is worse. We will introduce these two types as following section.. 2.4.1.1 LC Tank Voltage-Controlled Oscillator The concept of LC tank VCO is using negative resistance of active circuit to cancel the resistance of LC tank as shown in Fig. 2.17. Fig. 2.18 shows series transfer to parallel. Fig. 2.19 shows its equivalent resonant model. called negative-Gm oscillator.. 14. LC tank oscillator is.

(28) Chapter 2 General Backgrounds R1. Active Circuit. Resonator. Fig. 2.17.. R2. Negative resistance and LC tank resistance.. Fig. 2.18.. L. Fig. 2.19.. Series to parallel.. C. R. Equivalent resonant model.. The negative resistance is produced from cross-coupled pair which is positive feedback. In Fig. 2.20, we can calculate the impedance seen at the drain of M1 and M2. The impedance is. Rin = − 2. gm. . Generally speaking, the phase noise of PMOS-cross. coupled pair is better than NMOS-cross coupled pair. Rin. M1. Fig. 2.20.. M2. Input impedance of NMOS cross-coupled pair.. 15.

(29) Chapter 2 General Backgrounds. Fig. 2.21 shows the complementary cross-coupled pair. Compare with NMOS-cross coupled pair or PMOS-cross coupled pair in the same power consumption, the gm of complementary cross-coupled pair is larger. Larger gm means faster switching. The rise-time and fall-time of output waveform are more symmetric and the phase noise is better.. M3. M4 V control. M1. M2. Fig. 2.21. Complementary cross-coupled pair.. 2.4.1.2 Ring Oscillator Fig. 2.22 shows the ring oscillator. It is cascade of N stages with an odd number of inverters is placed in a feedback loop. The period of ring oscillator is equal to 2NTd and the oscillation frequency is. f0 =. 1 2 NTd. . There are three advantages of the. ring oscillator: high integrated with PLL, smaller die size than LC-tank VCO, and full output voltage swing.. Fig. 2.22.. Ring oscillator.. 16.

(30) Chapter 2 General Backgrounds. 2.4.2 Performance Parameters 2.4.2.1 Phase Noise An ideal output spectrum of oscillator has only one impulse at the fundamental frequency as shown in Fig. 2.23(a). In an actual oscillator, the frequency spectrum consists of an impulse exhibits skirts around the carrier frequency as show in Fig. 2.23(b). These skirts are called phase noise due to the influence of several kinds of noises. The noise sources such as shot noise, flicker noise and thermal noise. These noises are caused by the resistors, capacitors, inductors, and transistors. Noise injected into an oscillator by noise sources may influence the frequency and the amplitude of the output signal. These phenomenon are called AM, PM and FM noises.. Output Power. Ideal Oscillator. L(Δf ). Pout. 1Hz. fC. Wc (a). Fig. 2.23.. f C + Δf. f. (b). Output spectrum of ideal and actual oscillators.. Fig. 2.24 shows the Lesson’s phase noise model. We can express by. ⎡ 1 FkT ⎪⎧ ⎡ ω ⎤ 2 ⎪⎫⎤ ⎡ Δω 3 ⎤ 1/ f o L(Δω ) = 10 log ⎢ ⎥ ⎨1 + ⎢ ⎬⎥ ⎢1 + ⎥ Δω ⎥⎦ ⎢⎣ 2 Ps ⎩⎪ ⎣ 2QΔω ⎦ ⎭⎪⎥⎦ ⎢⎣. (2.5). This equation is from the curve fitting after measured results of VCO. Therefore,. Δω1/ f 3 is from measured results.. 17.

(31) Chapter 2 General Backgrounds. L(Δw). 1/ f. 3. 1/ f Δw1 / f 3. Fig. 2.24.. 2. ⎡ 1 FkT ⎤ 10 log ⎢ ⎥ ⎣ 2 Ps ⎦. w0 / 2Q. log(Δ w ). Lesson’s phase noise model.. If the output waveform is odd-symmetry, It can suppress 1 / f noise effetely.. This will lower Δ w1 / f . From equation (2.5), increase Q factor of LC tank and output 3. power can improve phase noise.. 2.4.2.2 Frequency Tuning Range Frequency variation is an important parameter when designing VCO. Because a CMOS oscillator must be designed with a large tuning ranges to overcome process variations. The simplest way to do so is with a varator such as diode varator and MOS varator. The NMOS cross-coupled pair VCO has higher tuning range than double cross-coupled VCO topology for equal effective tank transconductance. When control voltage change, the bias voltage of transistor will also change. S parameter and Γin will change according to dc current variation. This will cause output frequency shift. This is called pushing effect. To avoid pushing effect, we can use high quality resonator to reduce the pushing effect. We can also using regulator to overcome pushing effect such as band gap circuits. Loading effect is another problem. When loading change, its impedance is also change. This will cause output frequency shift. This is called load pulling effect. To avoid this problem, we can use buffer circuit to overcome load pulling effect.. 2.4.3 Noise Model of VCO Phase noise is the most important parameter in the VCO design. There are two models: Leeson’s model and Hajimiri model. Lesson has developed a time invariant model to describe the noise of oscillators. Hajimiri proposed a linear time varying phase noise model. The below sections will introduce these two phase noise model. 18.

(32) Chapter 2 General Backgrounds. 2.4.3.1 Time Invariant Model In this section, phase noise analysis is described by using time invariant model. Time invariant means whenever noise sources injection, the phase noise in VCO is the same. In other words, phase shift of VCO caused by noise is the same in any time. Therefore, it’s no need to consider when the noise is coming. Suppose oscillator is consists of amplifier and resonator. The transfer function of a bandpass resonator is written as H ( jω ) =. jω (1/ RC ) (1/ LC ) + jω (1/ RC ) − ω 2. (2.6). The transfer function of a common bandpass is written as H ( jω ) =. jω (ωo / Q) ωo + jω (ωo / Q) − ω 2. (2.7). 2. Compare equation (2.6) with (2.7). Thus,. ωo = 1/ LC The frequency ω = ωo + Δω. Q=ωo RC. and. (2.8). which is near oscillator output frequency.. If ωo  Δω , we can use Taylor expansion for only first and second terms. Hence H ( jω ) ≈ 1 +. 2 j (ωo / Q). ⋅ Δω. (2.9). The close-loop response of oscillator is expressed by G ( jω ) =. − j (ωo / Q) 1 ≈ 1 − H ( jω ) 2 ⋅ Δω. (2.10). When input noise density is Si (ω ) , the output noise density is 2. So (ω ) = Si (ω ) G (ω ) = FkT (. ωo. 2QΔω. )2. (2.11). The above equation is double sideband noise. The phase noise faraway center frequency Δω can be expressed by ⎡ 2 FKT L(Δω ) = 10 log ⎢ ⎣⎢ Ps. 2 ⎛ ωo ⎞ ⎤ ⋅⎜ ⎟ ⎥ ⎝ 2QΔω ⎠ ⎥⎦. (2.12). where Ps is the output power. From equation (2.12), increasing power and higher Q factor can get better phase noise. Increasing power means increasing the power of amplifier. This will decrease noise figure (F) and improve phase noise. From equation (2.12), we can briefly understand phase noise. But the equation 19.

(33) Chapter 2 General Backgrounds. and actual measured result are different. The VCO spectrum is shown as Fig. 2.24. The phase noise equation can be modified as ⎡ 2 FKT L(Δω ) = 10 log ⎢ ⎢⎣ Ps. 2 ⎪⎧ ⎛ ωo ⎞ ⎪⎫ ⎛ ω1/ f 3 ⋅ ⎨1 + ⎜ ⎟ ⎬ ⎜⎜1 + Δ Δω ω 2 Q ⎝ ⎠ ⎩⎪ ⎭⎪⎝. ⎞⎤ ⎟⎟ ⎥ ⎠ ⎥⎦. (2.13). The above equation is called Leeson’s model.. 2.4.3.2 Time Variant Model In this section, we use the Hajimiri model to explain the phase noise. At first, we assume that an impulse current injects into a lossless LC tank as illustrated in Fig. 2.25. If the impulse happens to coincide with a voltage maximum as shown in top of Fig. 2.26. The amplitude increase ΔV=ΔQ/C, but the timing of the zero crossings does not change. An impulse injected at any other time displaces the zero crossings as shown in bottom of Fig. 2.26. Hence, an impulsive input produces a step in phase, so that integration is an inherent property of the impulse to phase transfer function. Because the phase displacement depends on when the impulse is applied, the system is time-varying.. i(t) δ (t − τ ). i(t). L. C. t. Fig. 2.25. Impulse current injects into LC tank. V out. ΔV. τ. t. (a ) V out. ΔV. τ. t. (b ). Fig. 2.26. Waveforms for impulse excitation.. 20.

(34) Chapter 2 General Backgrounds. Hajimiri proposed a linear time-varying phase noise model which is different from the Lesson’s model. The impulse response can be written as hφ (t ,τ ) =. Γ(ωoτ ) u (t − τ ) qmax. (2.14). where qmax is the maximum charge displacement across the capacitor and u(t) is the unit step. The function Γ ( x ) is called the impulse sensitivity function (ISF), and is a frequency and amplitude independent function that is periodic in 2π. Once the ISF has been determined, we may compute the excess phase through use of the superposition integral. Hence. φ (t ) =. ∞. ∫. t. 1. hφ (t ,τ )i (τ )dτ =. ∫ Γ(ω τ )i(τ )dτ o. qmax. −∞. −∞. (2.15). This equation can be expanded as a Fourier series: Γ(ωoτ ) =. c0 ∞ + ∑ cn cos(nωoτ + θ n ) 2 n=1. (2.16). where the coefficients cn are real and θ n is the phase of nth harmonic of the ISF. We assume that noise components are uncorrelated, so that their relative phase is irrelevant, we will still ignore θ n . Equation (2.16) can be rewritten as 1 ⎡ c0 φ (t ) = ⎢ qmax ⎣ 2. ⎤ i d c i n d τ τ τ ω τ τ ( ) ( ) cos( ) + ⎥ ∑ n o ∫ ∫ n=1 −∞ −∞ ⎦ ∞. t. t. (2.17). Equation (2.17) allows us to compute the excess phase caused by an arbitrary noise current injected into the system, once the Fourier coefficients of the ISF have been determined. Now we consider the injection of a sinusoidal current whose frequency is near an integer multiple m of the oscillation frequency, so that i(t ) = I m cos [ (mωo + Δω )t ]. (2.18). Substituting (2.18) into (2.17) where Δω  ωo and n=m. We can simplify Equation (2.17) as φ (t ) ≈. I m cm sin( Δω t ) 2 qmax Δω. Vout (t ) = cos [ωot + φ (t ) ]. Substituting (2.19) into (2.20). Suppose 21. (2.19) (2.20). I m cm < 1 . Therefore, the sideband 2qmax Δω.

(35) Chapter 2 General Backgrounds. power relative to the carrier is given by ⎛ I c ⎞ PSBC (Δω ) ≈ 10 log ⎜ m m ⎟ ⎝ 4qmax Δω ⎠. 2. (2.21). In general, a noise signal can be separated into two type noise source: white noise and flicker noise. First, input an noise current only with the white noise and its in 2 noise power spectral density is Δf . The total single sideband phase noise spectral. density in dB below the carrier per unit bandwidth is given by ⎛ in 2 ∞ 2 ⎞ ⎜ ∑ cm ⎟⎟ Δf m = 0 ⎜ CSSB ( Δω ) ≈ 10 log 2 ⎜ 4qmax Δω 2 ⎟ ⎜⎜ ⎟⎟ ⎝ ⎠. (2.22). According to Parseval’s theorem. Thus, ∞. ∑c m =0. 2 m. =. 1. π. 2. 2π. ∫ Γ( x). dx = 2Γ 2 rms. (2.23). 0. Therefore we can use quantitative analysis to analyze the phase noise sideband power due to the white noise source as following equation ⎛ in 2 2 ⎞ Γ rms ⎟ ⎜ Δf ⎟ L(Δω ) ≈ 10 log ⎜ 2 ⎜ 2q max Δω 2 ⎟ ⎜⎜ ⎟⎟ ⎝ ⎠. where qmax = CVmax ,. Vmax is the largest amplitude of VCO, and. (2.24). in 2 4kT = Δf R. .. Substituting these relations into (2.24). We have ⎛ 4kT 2 ⎛ ω ⎞ 2 ⎞ L(Δω ) ≈ 10 log ⎜ Γ rms ⎜ o ⎟ ⎟ ⎜ Ps ⎝ QΔω ⎠ ⎟⎠ ⎝. (2.25). If input noise of VCO is 1/f noise, the power spectral density is written as. i 2 n ,1/ f = in 2. ω1/ f Δω. (2.26). where ω1/ f is the 1/f corner frequency of 1/f noise. This equation represents the phase noise spectrum of an arbitrary oscillator in 1/f2 region of the phase noise spectrum. Quantitative analysis for the relationship between the device corner 1/f and the 1/f 3 corner of the phase noise can be illustrated by following equation. 22.

數據

Fig. 2.13.  Differential amplifier balun.
Fig. 2.13. Differential amplifier balun. p.26
Fig. 2.17.    Negative resistance and LC tank resistance.
Fig. 2.17. Negative resistance and LC tank resistance. p.28
Fig. 2.38.    Second order loop filter.
Fig. 2.38. Second order loop filter. p.44
Fig. 3.2.    LC folded cascode mixer with an added resistance.
Fig. 3.2. LC folded cascode mixer with an added resistance. p.52
Fig. 3.9.    Simulated and measured power conversion gain versus RF frequency with  the IF frequency is 50MHz, RF power is -30dBm, and LO power is -5 dBm
Fig. 3.9. Simulated and measured power conversion gain versus RF frequency with the IF frequency is 50MHz, RF power is -30dBm, and LO power is -5 dBm p.55
Fig. 3.10.    Simulated and measured RF return loss versus RF frequency.
Fig. 3.10. Simulated and measured RF return loss versus RF frequency. p.56
Fig. 3.11.    Simulated and measured IF return loss versus IF frequency.
Fig. 3.11. Simulated and measured IF return loss versus IF frequency. p.56
Fig. 3.13.  Simulated and measured P1dB versus RF frequency.
Fig. 3.13. Simulated and measured P1dB versus RF frequency. p.57
Fig. 3.16.    Input impedance matching.
Fig. 3.16. Input impedance matching. p.60
Fig. 3.23.    Simulated phase differences.
Fig. 3.23. Simulated phase differences. p.68
Fig. 3.27.    Die bonded to the PCB.
Fig. 3.27. Die bonded to the PCB. p.71
Fig. 3.34.    Simulated and measured LO return loss versus LO frequency.
Fig. 3.34. Simulated and measured LO return loss versus LO frequency. p.73
Fig. 3.33.    Simulated and measured RF return loss versus RF frequency.
Fig. 3.33. Simulated and measured RF return loss versus RF frequency. p.73
Fig. 3.35.    Simulated and measured IF return loss versus IF frequency.
Fig. 3.35. Simulated and measured IF return loss versus IF frequency. p.74
Table 3.4    Summary of simulation and measurement results

Table 3.4

Summary of simulation and measurement results p.76
Fig. 3.41 shows the block diagram of frequency summation, which consists of  four mixers and two output combiner
Fig. 3.41 shows the block diagram of frequency summation, which consists of four mixers and two output combiner p.78
Fig. 3.42.    Principle of SSB mixer: frequency difference.
Fig. 3.42. Principle of SSB mixer: frequency difference. p.79
Fig. 3.67.    Output spectrum of band 2
Fig. 3.67. Output spectrum of band 2 p.89
Fig. 3.69.    Output spectrum of band 10.
Fig. 3.69. Output spectrum of band 10. p.89
Fig. 4.7.  Voltage-biased VCO with noise filter.
Fig. 4.7. Voltage-biased VCO with noise filter. p.96
Fig. 4.8 shows the proposed VCO. It consists of current-reuse VCO structure,  filtering inductor, main LC tank, and second harmonic LC tank
Fig. 4.8 shows the proposed VCO. It consists of current-reuse VCO structure, filtering inductor, main LC tank, and second harmonic LC tank p.97
Fig. 4.9.    Main LC tank and 2 nd  LC tank.
Fig. 4.9. Main LC tank and 2 nd LC tank. p.98
Fig. 4.14.    Output spectrum at 24GHz.
Fig. 4.14. Output spectrum at 24GHz. p.100
Fig. 4.18.    Control voltage versus output power.
Fig. 4.18. Control voltage versus output power. p.101
Table 4.2.    Summary of the comparison

Table 4.2.

Summary of the comparison p.103
Fig. 4.25.  EM consideration.  20 40 60 80 100 120 140 160 1800 200-100-80-60-40-20-1200 Frequency (GHz)Output (dBm)
Fig. 4.25. EM consideration. 20 40 60 80 100 120 140 160 1800 200-100-80-60-40-20-1200 Frequency (GHz)Output (dBm) p.107
Fig. 4.32.    Simulated summary of phase noise reduction technique.
Fig. 4.32. Simulated summary of phase noise reduction technique. p.110
Fig. 4.44.    Schematic of modified CP.
Fig. 4.44. Schematic of modified CP. p.117
Fig. 4.57.    Spectrum of the PLL’s output as locking.  0 1 2 3 4 5 60.00.20.40.60.81.01.21.4Control Voltage (V) time (usec)  Vctrl transient response
Fig. 4.57. Spectrum of the PLL’s output as locking. 0 1 2 3 4 5 60.00.20.40.60.81.01.21.4Control Voltage (V) time (usec) Vctrl transient response p.125
Fig. 4.59.    Initial and steady state of control voltage.
Fig. 4.59. Initial and steady state of control voltage. p.125

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