Phase-Locked Loop Design

In this design, we have chosen to synthesize directly the 24 GHz signal without frequency multiplication. Despite the difficulties of designing the VCO and the prescaler at so high frequencies, we have chosen this solution to achieve 24 GHz PLL.

Phase-locked loop is a circuit in which the phase of a local oscillator is tracing and locking the phase of a reference frequency. PLL consists of phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, prescaler and frequency divider.

The PLL schematic is shown Fig. 4.33. The phase detector is a precharge-type PFD.

The phase detector output is connected to a charge pump. The latter is followed by a passive type II filter for better rejection at higher frequencies. The VCO output supplies the prescaler and the PLL output. The prescaler is followed by a divider-by-256. The following sections will introduce the details of the proposed PLL architecture.

PFD/CP VCO

Divider /256

Presclaer /2 Fref=46.875

MHz

24 GHz Differential

output Loop Filter

Fig. 4.33. Proposed PLL architecture.

4.3.1.2 Low Power VCO

The VCO is the most important block of the PLL because it works at a high frequency and requires a low phase noise. There are several ways to build a VCO. In this work, we adopted the NMOS-pair cross-coupled LC tank VCO with filtering

inductor and substrate resistors. Here we adopted filtering inductor and substrate resistors to improve phase noise. The VCO schematic is shown in Fig.4.34. The two output buffers employ common source amplifiers for testing purpose. VDD is 0.6V for low power purpose and power consumption of VCO core is 0.8mW.

Vctrl

4.3.1.3 Divide-by-2 Prescaler

Q+

In this work, the prescaler follows the VCO which is operates at 24 GHz. The topology of the static frequency divider including input and output buffers is shown in Fig. 4.35. The divider core consists of a differential CML D-flip-flop (DFF), where the output is inverted and fed back to the data input. The DFF is built of two latches (CML1 and CML2). If CML1 tracks then CML2 latches, and vice versa. As a result, the output of the DFF only changes at rising C+ clock transitions. In any other time the outputs are static. The same applies to the outputs of CML1 in the feedback

configuration. This type of frequency divider is called static frequency divider. The outputs of the two latches provide four phases at 0⁰, 90⁰, 180⁰, and 270⁰ of the divided reference clock. The output buffers are added to drive the 50ohm measurement equipment.

C- C+

Q- Q+

VDD

Vbias D+

D-Fig. 4.36. Schematic of a CML latch.

The circuit schematic of the classical current mode logic (CML) latch is shown in Fig. 4.36. The latch circuit consists of two differential stages. Their current sources are controlled by the clock signals C+ and C-. If C- is high and C+ is low, the input signal D+ and D- appear amplified at the outputs Q+ and Q-. If the C- switches to low and C+ to high voltage levels, the input signals are turned off and then sensed by positive feedback. Resistive loads offer a lower parasitic capacitance than PMOS loads. The peaking inductors increase the bandwidth.

Input from VCO +

Input from VCO -PLL

Differential Output

Output to next stage (I -)

Output to next stage (I +) VDD

Fig. 4.37. Schematic of prescaler.

The prescaler is implemented by using static frequency divider which can provide quadrature outputs as shown in Fig. 4.37. The core divider circuit consists of two current-mode logic (CML) latches and consumes 2.88 mW from a 1.8V supply.

The high division frequency is achieved by employing resistive loads, and inductive peaking in the latches. The presclaer as the first frequency divider in the PLL feedback can reduce the power consumption.

4.3.1.4 Divide-by-256 Divider

The block diagram of divider-by-256 is shown as Fig. 4.38 which is cascaded by one CML and seven TSPC circuits.

CML /2 TSPC /2 TSPC /2 Fin

TSPC /2 TSPC /2 TSPC /2

Fout TSPC /2 TSPC /2

Fig. 4.38. Block diagram of divider-by-256.

The CML divider is using master-slave type as Fig. 4.39. Master-slave divider is differential input and then output four phase signals (0^o, 90^o, 180^o, 270^o). The purpose of divider-by-256 is to produce low frequency signal for compare with reference frequency to lock final frequency. Therefore, we choose the simplest circuit – True Single Phase Clock latches (TSPC). Fig. 4.40 shows the schematic of the improved TSPC. The modified TSPC only need one clock. The advantage is no need inverter clock and deduces circuit complexity. This circuit only needs 9 transistors. Compared to the SCL divider, TSPC has only nine transistors and the number of interconnections between them is highly reduced. Having each transistor a lower interconnection capacitance, the size can be close to the minimum value and than the power consumption is decreased.

CK+

CK-I+ I- Q+

Q-Fig. 4.39. Schematic of master-slave divider.

in

out

Fig. 4.40. Schematic of TSPC divider.

4.3.1.5 PFD

Phase detectors are a comparator which is providing an output signal whose DC component is proportional to the difference in phase between the two input signals.

The simplest type of phase frequency detector (PFD) is shown as Fig. 4.41. The conventional PFD adopted DFF structure. The limitation of its maximum frequency operation and dead zone problem are the drawbacks. Due to the output load, the output signal of the PFD requires a period of time to change. If there is not enough to change the state of the output signals, the function of the PFD will not be accomplished. This phenomenon usually occurs when the phase difference of two input signals is so small that the output pulse width of AND gate is less than the needed rise time. This phenomenon is called dead zone. The dead zone influence locking time and locking status of overall PLL. Without careful design, the PFD will not work properly when the small input phase difference is applied.

Reference

Slave

Up

Down

Fig. 4.41. Schematic of conventional PFD.

The designed PLL adopted precharge-type PFD shown as Fig. 4.42. The phase frequency detector compares the phase and frequency difference between the reference signal and the signal feedback by the frequency divider. Then PFD sends a signal UP or DOWN. The UP signal is high when the input reference signal is operating at a higher frequency than the VCO feedback signal. The charge pump forces current into the loop filter when the UP signal is high. This causes the VCO control voltage to rise. Then it increases the VCO frequency and brings the feedback signal to the same frequency as the reference signal. The DOWN signal is high when the input reference signal is operating at a lower frequency then the VCO feedback signal. The charge pump forces current out of the loop filter when the DOWN signal is high. This causes the VCO control voltage to fall. Then it decreases the VCO frequency and brings the feedback signal to the same frequency as the reference signal.

Compare precharge-type PFD with conventional PFD, precharge-type PFD used less transistors and get smaller chip area. The precharge-type PFD not only reduce the dead zone problem and maximum frequency operation limitation but also lower chip size.

Reference

Slave

Up

Down

Fig. 4.42. Schematic of precharge-type PFD.

4.3.1.6 Charge Pump

Vu

Vd

Cx

Cy Cp

Fig. 4.43. Schematic of conventional CP.

A charge pump (CP) consists of two switched current source that charge into or out of the loop filter according to two logical inputs. Fig. 4.43 illustrates a conventional charge pump driven by a PFD and driving a capacitor. If the divider output is lagging the input of reference. CP activates the top current source. If the divider output is ahead, the bottom current source is activated and then drawing charge from the capacitor. The conventional charge pump has two disadvantages.

First is the mismatch of UP and DOWN current source. Second is the charge sharing effect.

Upb

Down

To Loop Filter

Fig. 4.44. Schematic of modified CP.

The designed PLL adopted CP shown as Fig. 4.44. CP activates the current source according to two logical inputs from PFD. Upb means UP followed by an inverter. This modified CP adopted switch on source. This can reduce charge sharing effect.

4.3.1.7 Loop filter

C1

To VCO Vctrl From

Charge Pump

R2

C2

Fig. 4.45. Schematic of second order loop filter.

In designed PLL, we use a second order loop filter to reduce the ripple. The standard passive loop filter configuration for a current mode charge pump PLL is shown in Fig. 4.45. The PFD’s current source outputs UP or DOWN into charge pump and then into the loop filter. Then LF converts the charge into the VCO’s control voltage. The shunt capacitor C1 is recommended to avoid discrete voltage steps at the control port of the VCO due to the instantaneous changes in the charge pump current output. The impedance of the second order filter in Fig. 4.45 is

( ) ( )

(

) (

)

2

1 2 2 1 2

1 s C R

Z s s C C R s C C

= +

+ + (4.7)

4.3.2 Simulated Results