Current Sensing and Slope Compensation

The current sensing circuit is one of the most important building blocks in current-mode control. There are many current sensing circuits available [47]-[54].

Among them we choose the current-conveyor-based sense-FET current sensing [48]-[53], [71] because it has some good features as follows:

1. It dose not need the extra pin-out and external component.

2. Its quasi-lossless characteristic could enhance the efficiency [52].

3. Matching devices, instead of RDS (ON) of MOSFET or passive component such as resistors, are used to improve accuracy (reported higher than 94% accuracy [48], [49]).

4. It can operate in low voltage [49] and has improved noise immunity [53].

5. It can be easily compensated [53] and has high speed response [53].

Fig. 3.7 Current-conveyor-based sense-FET current sensing.

The current sensing circuit is shown in Fig. 3.7. The second generation negative current conveyor (CCII-) [71] is enclosed in the dashed box. In our current sensing circuit design, we use the second generation current conveyor (CCII-) instead of the first generation current convey (CCI) used in [48]-[51]. The CCII has no current flow in terminal Y, thus eliminates the unused power dissipation and extra circuits.

According to the principles of CCII- [71], (3.8) and (3.9) were shown as follows:

And the relationship of the sensed current and the inductor current can be determined by the aspect ratio of M1 and M2. As a result, accurate current information is obtained for the control loop of the current-mode control.

When dealing with current-mode control, there is a well known instability problem for duty ratio greater than 50% [46]. An artificial ramp acts as slope compensation must be added to the sensed current signal to suppress the sub-harmonic oscillation of the converter. How to generate a compensation ramp and add it to the sensed current signal is another issue. Conventionally, both the output of current sensing and the compensation ramp are expressed in “voltage” form [47]-[54].

We need a summing amplifier to add the compensation ramp (Vramp) to the sensed current signal (V ) as shown in Fig. 3.8 (a) [47].

Fig. 3.8 (a) Adding compensation ramp and sensed inductor current signal.

(a) Summing amplifier.

Fig. 3.8 (b) Adding compensation ramp and sensed inductor current signal.

(b) Use two V-to-I converters and adding the current signals by a resistor.

Another solution is to convert the current information (Visense) and compensation

ramp (Vramp) to “current” form by V-to-I converters, respectively. Then we add these two current together and get the summing voltage through a single resistor as shown in Fig. 3.8 (b) [48], [49]. These methods need multi-converts with complex circuits, and correspondingly, inducing more distortion to the desired signal.

To solve the above problem, we propose a simple and effective circuit as shown in Fig. 3.8 (c). Because the output signal Isense of the current-conveyor-based sense-FET current sensing mentioned above is in current form, it does not need a V-to-I converter. On the other hand, the compensation ramp can be generated by charging a capacitor with a constant current and discharging it with clock pulses. In Fig. 3.8 (c), we leave out another V-to-I converter and directly connect the capacitor C_S to a resistor Rf. One end of the resistor Rf is grounded. Isense and a constant current IC flow into the top of CS and Rf, respectively. The capacitor CS and resistor Rf were grounded periodically by clock pulses. And we have the summing voltage Vsum at the top of Cs. We can calculate the Vsense and Vsum as follows:

Where t is the time elapsed from the end of clock pulse in each cycle. Except the desired sum of current information and compensation ramp, here we have an extra term “Ic × Rf” in Vsum. This extra term is a constant value and can be used as a DC bias to avoid Vsum falling into the nonlinear region of error amplifier output [54]. For different applications of converter design, we can simply adjust the values of CS and Rf to change the compensation slope or current gain to have the desired result.

Fig. 3.8 (c) Adding compensation ramp and sensed inductor current signal.

(c) Proposed summing circuit.

3.3.4 Over-Current Protection

Over-current protection is very important in power supply design for safety reason. One of the benefits of current-mode control is cycle-by-cycle current limitation. However, because of the minimization of the inductor and the higher slope of current ramp, the switching frequency goes higher. As a result, the over-current protection needs higher speed in response to ensure safety.

The conventional over-current protection compares the sensed current signal (in voltage) with a reference voltage [53], [55]. If the sensed signal is higher than the threshold, it turns off the main switch (In our case the main switch is the high side PMOS) with an over-current signal as shown in Fig. 3.9 (a). The comparator delay was undesirable. In traditional voltage comparator design, for most circuit topology, the basic way to increase response speed is to increase operating current [56].

However, it is at the expense of power consumption and also conversion efficiency.

Moreover, when the operating current goes higher, the speed of traditional voltage comparator will saturate due to the increase of parasitic capacitance and even larger operating current cannot help either.

Fig. 3.9 (a) Over-current protection circuit.

(a) Conventional over-current protection circuit.

To solve this problem, we propose a new over-current protection circuit as shown in Fig. 3.9 (b). As mentioned in the preceding section, the Isense is in current form. We utilize this characteristic of current sensing circuit and use a single transistor to achieve over-current protection. Note that the bias circuit located in left-down of Fig. 3.9 (b) can be any simple bias circuit used by other circuits in the converter to generate a bias voltage Vb. From (3.4) and (3.5), we know that when

( )

) .)(

( 2

1

1 OX GS t

M sat D

sense V V

L C W I

I > = μ⋅ − (3.14)

the drain voltage increases dramatically and the speed is determined by the excess current and parasitic capacitance at drain node. Inherently, it operates faster than the conventional voltage comparator. Moreover, because the current sensing and bias circuits are not newly created parts in the circuit, the quiescent current of the over-current protection circuit is zero. As a result, the simple circuit deals with the comparator response speed and power consumption at the same time.

Fig. 3.9 (b) Over-current protection circuit.

(b) Proposed over-current protection circuit.

This circuit can be easily adjusted to fit various applications. As we know the value of Ibias and the aspect ratio of Mb, we can easily adjust the aspect ratio of M1 to reach the desired current limit. Note that the VDS (sat) (equals to (VGS – Vt)) must be smaller than the logic threshold to avoid M1 operating in triode region, or the current limit will be smaller than the expected value and cannot be well defined.