Electromagnetic Interference (EMI)

×100

NOM DEV

V

V (2.13)

Where VDEV is the maximum deviation from nominal output voltage VNOM at a full load transient. The transient recovery time was defined differently from 1% to 5%

tolerance of the final settling value in different texts. We choose 1% tolerance to evaluate the performance of our work.

2.5.6 Electromagnetic Interference (EMI)

Electromagnetic interference (EMI) is a potential problem for the circuit designer.

The switching process of a regulator produces voltage spikes resulting in EMI that interferes with proper operations of sensitive electronic equipments. The EMI spectrum begins at the switching frequency and often extends over 100 MHz that falls within the frequency bands commonly allocated for communications, such as low-frequency (LF), high-frequency (HF), and very-high frequency (VHF) bands.

One obvious advantage of a fixed-frequency regulator is that the switching frequency and its harmonics are fixed which makes it easier to filter induced EMI.

There are two main EMI specifications that must be checked out, that for conducted noise and that for radiated noise. Usually if a design includes adequate screening and the conducted noise is kept under control, by means of appropriate filters, radiated noise is not too much of a problem.

C HAPTER 3

A M ONOLITHIC C URRENT -M ODE B UCK

C ONVERTER WITH A DVANCED C ONTROL AND P ROTECTION C IRCUITS

3.1 I

Portable battery-operated devices are more and more popular today. For these devices, small size, light weight and long battery run-time are the main demands. The batteries had become a main portion in space and weight of these portable devices. As a result, enhancing the efficiency of power supply and management is very important to minimize the size and weight and to extend the battery run-time. The well-known power management strategy, sleep mode, shuts down the unused partial circuit to effectively reduce the power consumption [44]. Although sleep mode can save the power effectively in stand-by mode, there is no power saving in active mode because it operates with full current. The way of saving the power is to reduce the operating current but this usually reduces the circuit performance such as speed and noise immunity.

We focused on increasing the power efficiency and reducing die size without sacrificing high speed operation. Besides, safety operation is also an important consideration in power supply design. In this chapter, we propose the dynamic partial shutdown strategy (DPSS), current sensing, over-current protection, soft-start and

The DPSS manages the power consumption at active mode to enhance the circuit performance per power consumption. Improvement was obvious, especially in lighter load with the PFM mode control [45].

Moreover, we modified the current sensing and slope compensation circuits in current-mode control [46]-[54] to simplify the design flows of various specifications.

In current sensing circuit, a simple over-current protect comparator is developed. Its response speed is faster than the conventional comparator [53], [55]-[56]. But it consumes no additional quiescent power. With this circuit, the over-current protection, which is essential to voltage regulator, can be designed easily.

Most portable electronic devices have more than one power supply modules.

Anyone of them may be shut down when the circuit supplied by it is unused. However, if we turn on the power supply module and don’t handle the load current demand from next stage properly, the inrush current demand to previous stage will result in impulse voltage drop and affect the circuit operation or shorten the life-time of batteries. On the other hand, inrush current can also cause the output to overshoot [57].

To overcome the induced effects, a soft-start time, usually 1 ~ 10 ms for portable electronic devices, is required at the beginning of the turn-on stage for voltage regulators. During soft-start time, the corresponding voltage regulator charges the output capacitor slowly, and then no inrush current is generated to affect the pre-stage circuit or to cause output overshoot. The conventional method of generating the soft-start time is costly in area [55], [58]-[59] or need the extra pin-out and discrete capacitor [57], [60]-[63]. This method results in increasing in cost, size and weight.

This paper also presents a simple and area-effective circuit to generate soft-start time without the extra pin-out and the discrete capacitor. This circuit has the soft-start time

proportional to the square of silicon area and is suitable for even longer soft-start time (> 10 ms) applications.

Structure of current-mode PWM and PFM control are introduced in Section 3.2 [45], [64]. Circuit implementations of the controller are discussed in Section 3.3.

All the circuits mentioned above are integrated in a monolithic buck converter and implemented in a 0.6 μm CMOS process. It can operate in a wide input range from 2.2 V to 6.0 V. Measurement results are shown in Section 3.4 and conclusion is in Section 3.5.

3.2 S

M

B

C

In this section, we will briefly introduce the structure of current-mode PWM and PFM operation in the developed monolithic buck converter [45], [64].

3.2.1 PWM

At moderate to heavy loads, the converter operates in PWM mode. The block diagram of a simplified current-mode PWM buck converter is illustrated in Fig. 3.1. A clock pulse at the R (reset) input of SR Latch initiates the switching period, causing the latch output Q to be low. The latch output Q goes through Buffer and Dead Time Control to produce both DH and DL low to turn on the high side PMOS transistor and turn off the low side NMOS transistor. While the high side transistor conducts, its current is equal to the inductor current. This current increases in a certain positive slope according to the inductor value and converter voltages. We sense the high side transistor current and compare it with the control voltage VC. When the sensed current

signal becomes higher than control voltage VC, the modulator output will be high to set the SR Latch output Q high. Again the latch output Q goes through Buffer and Dead Time Control to produce both DH and DL high to turn off the high side PMOS transistor and turn on the low side NMOS transistor until next clock pulse. We see the current controlled through the control voltage VC and thus is named current-mode control. On the other hand, a compensation ramp is added to the sensed current signal to suppress sub-harmonic oscillation at duty ratio > 50% [46].

Fig. 3.1 Simplified structure of current-mode PWM control.

3.2.2 PFM

With decreasing load current, the converter automatically switches into PFM mode in which the power stage operates intermittently, based on load demand. Due to

reduced switching activity at power stage, the switching losses are minimized, and the device runs with a minimum quiescent current and maintains high efficiency. The block diagram of a simplified PFM mode buck converter is illustrated in Fig. 3.2.

Fig. 3.2 Simplified structure of PFM control.

The output voltage is monitored with a voltage comparator. As soon as the output voltage falls below the nominal value, the output of the voltage comparator resets the SR Latch. Through Buffer and Dead Time Control the high side PMOS transistor is turned on and the inductor current ramps up. When a current comparator detects that the inductor current reaches the preset peak current, its output sets the SR Latch and turn off the high side PMOS transistor and turn on the low side NMOS transistor. As the inductor current ramps down, a reverse current comparator detects if

Reverse Current Comparator turns off the low side NMOS transistor to prevent drawing energy from output capacitor back to ground. When the output voltage falls below the nominal voltage again, the next cycle is started. As the load current decreases, the time interval between two successive pulses will become larger and vice versa.

3.2.3 Automatic PWM/PFM Mode Switching

There are many algorithms of switching between PWM and PFM. In this work, we use a hysteresis switching algorithm to prevent repeatedly switching between two modes during steady state operation. The algorithm can be described as follows:

1. In PWM mode, as the load current decreases, the inductor current may ramp to zero before the end of each clock cycle. In order to increase the efficiency, the low side NMOS will be turned off when the inductor current ramps to zero. This action prevents the current flowing in reverse direction from output capacitor to ground through inductor and low side NMOS. Thus the converter enters discontinuous conduction mode (DCM). When the converter operates in DCM, it means that the load current is small and we don’t need continuous full-cycle-pulses to sustain it. If the converter operates in DCM for about 20 μs, it will automatically switch to PFM mode.

2. In PFM mode, the peak current of each pulse is preset to a constant value as described above. We monitor the output voltage to determine when the next pulse should be issue. The next pulse will be issue if the output voltage falls below the nominal value. When the load current increases, the output voltage falls faster and the two pulses in succession will become closer. If the output voltage falls below

the nominal value after the peak current is reached and before the current ramps back to zero, it means that we need to issue the next pulse even before the present pulse is completed. In this condition, the load current is large and the output voltage cannot be sustained with this preset current pulse. Thus the converter will enter PWM mode again.

3.2.4 The Proposed Converter

Fig. 3.3 Functional block diagram of the developed monolithic buck converter.

Fig. 3.3 shows the simplified block diagram of the developed converter chip. It uses PWM and PFM control as described above. Key elements such as on-chip soft-start, DPSS, current sensing, modulator and over-current comparator will be

3.3 D

C

C

I

3.3.1 On-Chip Soft-Start Circuit

There are mainly two kinds of conventional soft-start circuits. One is the clock-based soft-start circuit which raises the reference voltage or maximum output current or duty cycle slowly [55], [58]-[59]. In this method, the way to achieve the longer soft-start time (> 1 ms) is to reduce the clock frequency or increase the bit-length of counter. The former one fails to reach the goal of raising the switching frequency to minimize the energy storage elements (such as inductors and capacitors) and to enhance the response speed in switching regulator design. A separate clock can be used for soft-start, but it requires extra die area and power. The latter one, however, consumes large silicon area. Moreover, the clock-based soft-start needs time-to-voltage or time-to-current-limit circuits.

The other soft-start method charges the capacitor with a constant current to generate a steadily rising voltage. This steadily rising voltage can be used as reference voltage during start-up or to limit the duty ratio or output current during start-up [57], [60]-[63]. The soft-start time can be calculated as:

I C V

t_soft−start = _REF× / (3.1)

Note that VREF is the reference voltage or a threshold voltage which determines the end of start-up, C is the capacitor value and I is the charging current.

In previous works [57], [60]-[63], extra pin-out and discrete capacitor were

needed to reach longer soft-start time (> 1 ms). For example, if VREF equals 0.6 V and 1 ms soft-start time is needed with 1 μA charging current, a 1.67 nF capacitor is needed. Our goal is to minimize the capacitor using small charging current. For integration of capacitor on die, the order of capacitor is picofarad. Correspondingly, the charging current is in the order of nanoampere. In [65]-[68], complex bias circuit is needed to generate the bias current in nanoampere order. In addition, transistors must operate in deep sub-threshold region. The I-V characteristic of MOS transistor operates in the deep sub-threshold region is: [69]

)

Where kx depends on process, n ≈ 1.5 and Vt is the threshold voltage of the transistor.

The effectiveness of gate drive voltage (VGS) to drain current (ID) is exponential.

Noise on the gate drive voltage will greatly affect the drain current. So that deep sub-threshold bias is not suitable for a noisy environment like switch-mode power supply with integrated power switches.

In this work, a simple circuit is proposed as shown in Fig. 3.4. Note that, Vb can be generated by a simple bias circuit or the existing bias voltage in the system. In Fig.

3.4, for a general bias circuit,

)

The transistor Mb operates in saturation region.

Fig. 3.4 Soft-start ramp generator.

We can use simple MOS transistor equations in [69]:

Saturation region (VGS > Vt, VDS > VGS - Vt): transistor M1 operates in saturation region. Other series transistors M2 ~ Mn operate in triode region. Therefore, M2 ~ Mn are like the (n-1) linear resistances whose total voltage drop is slightly smaller than (VGS - Vt). For small VDS, we approximate (3.5) to

Then according to Ohm’s law, we have

As a result, the nanoampere order charging current can be achieved easily in today’s technology. For example, if VREF equals to 0.6 V, 1 ms soft soft-start time is available with a 1 nA current to charge the 1.67 pF capacitor. In our design, the soft-start circuit occupies only 56.1 × 65.4 μm² and reaches longer than 1.5 ms soft-start time.

Another advantage of this circuit is that the soft-start time is proportional to the square of the silicon area. According to (3.1), for a fixed reference voltage, the soft-start time is proportional to the capacitor value and reverse proportional to the charging current. In (3.7), the charging current is reverse proportional to the summation of RDS of transistors. Thus we have the soft-start time proportional to the series number of PMOS. If we increase both the capacitor value and the series number of PMOS with the same ratio, the soft-start time is proportional to square of the occupied silicon area. The proposed method can reduce the silicon area dramatically and this circuit does not need extra pin-out and discrete capacitor.

3.3.2 Dynamic Partial Shutdown Strategy (DPSS)

For extension of battery run time of portable devices, dynamic power management uses sleep mode which shuts down unused circuits to save power during stand-by mode [44]. However, in active mode, it cannot save the power consumption because of the full operating current. In this paper, the dynamic partial shutdown strategy (DPSS) controlling the turn off of partial circuits is proposed to save the

power consumption, especially in active mode. During active mode, only the essential parts will be turned on in specific operating situation under DPSS. As a result, the power consumption is minimized and battery run time is extended.

In a switch-mode power supply, the decision of when to turn on or turn off switches was made according to the output voltage and current condition in each switching cycle. When the switch is on, we need to decide when to turn it off; when the switch is off, we need to decide when to turn it on again. According to this characteristic of switch-mode power supply, we can turn off partial circuits which are not needed to decide when the switch should be turned off during “ON” state and vice versa. Since there are digital signals indicating the ON and OFF states of the power switches in the converter, we can use these digital signals to turn on and turn off the partial circuits which are not needed in each state.

Take the proposed converter as an example. In Fig. 3.5 and Fig. 3.6, we use horizontal, vertical and oblique lines to indicate shut down parts. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off. Fig. 3.5 shows circuits operate in PWM mode; and Fig. 3.6 in PFM mode. Note that the soft-start time has been completed and the Soft-Start in Fig. 3.5 and Fig. 3.6 is always shut down.

In PWM mode, when high side PMOS is turned on, the slope of inductor current is positive. So we don’t need to detect reverse inductor current and the Reverse Inductor Current Detector can be turned off. When low side NMOS is turned on and that the slope of inductor current is negative, there is no need to detect the over-current and the Current Sensing and Over-current Comparator can be shut

down.

Fig. 3.5 DPSS in PWM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on.

Since the slope of inductor current is negative, the Over-voltage Comparator cannot do anything more to prevent output voltage from going too high. Thus the Over-voltage Comparator can be shut down. Besides, the next turning on of high side PMOS is decided by clock pulse in constant frequency leading edge modulation [70].

The Saw-tooth Generator, Analog Adder and Modulator can also be shut down.

In PFM mode, the Error Amplifier, Oscillator, Saw-tooth Generator, Analog Adder and Modulator all can be shut down. When high side PMOS is turned on, only

Comparator and Reverse Inductor Current Detector can be shut down. When low side NMOS is turned on, the Current Sensing and Over-current Comparator can be shut down. When both high side PMOS and low side NMOS are turned off, only the Voltage Comparator is active to decide when the high side PMOS should be turned on again.

Fig. 3.6 DPSS in PFM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off.

When using DPSS, care must be taken as dealing with analog signal level between ON and OFF states. For example, if the analog signal level of the Current Sensing is not preset correctly when the Current Sensing is turned off, the Current

Sensing may give wrong information about the inductor current at the beginning of next cycle. This wrong information may result in unstable operation. On the other hand, timing of digital signal is also an important issue. For example, if the Over-voltage Comparator is not turned on slightly before the next cycle, the next pulse may cause the output voltage goes even higher during transient conditions. This high voltage may damage the circuits in load stage.

Simulation results show that in PWM mode, operating current can be reduced from 500 μA to 250 ~ 300 μA, depending on the duty ratio. In PFM mode, operating current can be reduced from 200 μA to 50 μA. The reduced operating current can effectively boost conversion efficiency especially in light load operation. For example, when VIN = 3.6 V, VOUT = 2.5 V and ILOAD = 1 mA, the conversion efficiency is 89%

and 75% with and without DPSS, respectively. Higher input voltage and lower load current will increase the difference. When VIN = 4.2 V, VOUT = 2.5 V and ILOAD = 1

and 75% with and without DPSS, respectively. Higher input voltage and lower load current will increase the difference. When VIN = 4.2 V, VOUT = 2.5 V and ILOAD = 1