4. P RACTICAL D ESIGN AND L AYOUT C ONSIDERATIONS
4.3 L AYOUT C ONSIDERATIONS
4.3.3 On-Resistance of Power Switches
The conversion efficiency is directly affected by the on-resistance of the power switches. For integrated power switches, the on-resistances are tens to hundreds milli-ohm. The width of the power transistor are tens to hundreds milli-meter. The power transistors usually occupy more than 50 % area in an SMPS IC. How to reduce the area occupied by the power transistor without sacrificing the on-resistance is an important topic.
Since the on-resistance of the power transistors are in the same order as the resistance of several squares of metal lines, the metal routing will account for noticeable percentage of the total on-resistance. But the resistance of metal lines used in power transistors cannot be easily calculated due to their irregular shapes. So we write a small program, as shown in the appendix, incorporated with the SPICE simulator to evaluate the on-resistance of different layout of a 2-layer metal process.
The simulation and measurement results are shown in Table 4.1.
Table 4.1 Comparing measurement and simulation results of the on-resistance of the power transistors.
Both of them include the resistance of bond-wires, metal lines, and power transistors. We can see the accuracies of simulation estimation are within 6 %.
Compared with the single transistor emulation and the first-order metal resistance estimation, we can see that the traditional estimation results in –52.2 % ~ 182.2 % error. These errors will greatly influence the design of power transistors. We may suffer from costly larger power transistor and larger switching loss and switching noises. Or we may suffer from higher on-resistance and lower conversion efficiency.
This small program gives us useful estimations for power transistor layout.
From the experience point of view, we bring up three points concerning the on-resistance. These suggestions can be applied to a 2-layer metal process and need some modifications for other processes. First, minimize the length of first layer metal fingers. Since the square resistance of the lower metal layer is usually greater than higher metal layer does, reduce the length of first layer metal fingers will show great reduction of the total on-resistance. Second, use wider and shorter second layer metal plates to reduce the effective number of squares of the metal plates. Although the square resistance of the second layer metal is lower than that of the first layer metal, it can account for a considerable portion of the total on-resistance. Use wider and shorter plates will result in lower resistance. Third, use multiple bond-wires and distribute the bond-pads to a wider range of the layout area of the power transistor. If we increase the number of bond-wires, the resistance of bond-wires can be reduced with increasing cost of the package. Another side effect is that the bond-pads need to occupy silicon area. So we have to trade off between the number of bond-pads and the cost. Distribute the bond-pads to a wider range will reduce the effective number of squares of the top layer metal and the on-resistance can be reduced.
Fig. 4.8 illustrates three examples to explain these suggestions. The power transistors occupy the same area in Fig. 4.8 (a), (b) and (c). In Fig. 4.8 (a), the first layer metal fingers are much longer than the fingers in (b) and (c). The resistance of these longer fingers is larger. The second layer metal plates in Fig. 4.8 (a) and (b) both have more effective number of squares counted from the bond-pads to the other end of the metal plate. They also contribute more resistances. The bond-pads are most deconcentrated in Fig. 4.8 (c). From the above observation, we can conclude that the power transistor in Fig. 4.8 (c) will show the lowest on-resistance than (a) and (b) do.
From our experience, the layout style of Fig. 4.8 (a) and (b) may double the on-resistance although they occupied the same area as (c) does.
Fig. 4.8 Examples of power transistor layout. On-resistance: (a) ≈ (b) > (c)
C HAPTER 5
C ONCLUSION AND F UTURE W ORK
5.1 C
ONCLUSIONIn this dissertation, we discuss about the SMPS for DC-DC power conversion.
Basic topologies of non-isolated DC-DC SMPS are introduced. Safety considerations for power supply design are discussed. The design specifications are also included.
Based on the knowledge of DC-DC SMPS, we developed several new circuit techniques to achieve high conversion efficiency, compact converter size, wide operating range, fast transient response and safety operation. These developed circuit techniques were realized in a monolithic current-mode buck converter. The application of these circuit techniques can be extended to other topologies like boost and buck-boost of SMPS design, especially in integrated circuit power converter design.
5.1.1 On-Chip Soft-Start Circuit
The on-chip soft-start circuit occupies a small silicon area and eliminates the need of extra pin-out. This circuit achieves one to tens of milliseconds soft-start time using series MOS transistors and a small on-chip capacitor. This circuit prevents the inrush current during the start-up of the power module. It provides safety operation and shrinks the converter size in the same time. Another benefit of the proposed circuit technique is that because of its simplicity, it can be easily adopted for any other
power supply IC design.
5.1.2 Dynamic Partial Shutdown Strategy (DPSS)
The DPSS is a power management strategy. By exploiting the switching characteristic of SMPS, we developed this strategy. This strategy eliminates the unwanted waste of operating current and keeps the circuit performance at the same time. The DPSS improves the conversion efficiency especially in light load operation.
Thus the standby time of battery operated devices can last longer by utilizing DPSS.
Combined with the PFM mode, the conversion efficiencies are improved from 62 % ~ 75 % to 84 % ~ 89 % measured in our test chip.
5.1.3 Current Sensing, Slope Compensation and Over-Current Protection
In our design, we choose a quasi-lossless current conveyor based current sensing technique to implement our current-mode control. By exploiting the characteristics of this current sensing technique, we developed the slope compensation circuit and the over-current protection circuit. The proposed slope compensation circuit has reduced circuit complexity than traditional ones thus the silicon area is saved. The signal distortion is also reduced because we eliminate the multi-conversions of signals. The over-current protection is also simpler than traditional ones. The benefits of the over-current protection circuit are reduced silicon area, reduced power consumption and faster response for safety operation. Additionally, these circuits can be easily designed and adjusted. So we can achieve good regulation and wide operating range.
These circuit techniques can also be applied to other topologies for different applications.
Incorporating with other basic protection schemes, the above techniques are integrated into a demo chip. From the measurement results, we can see the effectiveness of these developed techniques.
5.2 F
UTUREW
ORKFor further efficiency improvement, we can investigate the power losses in the SMPS. The switching loss is one of the major losses in the SMPS. We can segment the power MOSFETs into parts for reducing gate drive loss [81]. We can also adjust the gate drive voltage dynamically according to the load condition [82]. These techniques can further improve conversion efficiency in light load operation at a price of increasing cost and circuit complexity.
Another interesting topic is about improving transient response. Although the proposed current-mode converter shows good transient response compared with others, it can not meet the specifications for supplying the high speed CPUs in personal computers. There are several ways to achieve faster transient response. An interesting one is nonlinear control [22], [83]. We may find other ways to control the SMPS to achieve faster response. Another straightforward method is higher switching frequency [21], [84]. This is much depending on the manufacturing process of the semiconductor power switches. Multi-phase design can also help improving transient response, but the cost is increased proportional to the number of phases they provide [21]-[22], [85]. Other purposed techniques also have their own disadvantages [86]-[90]. Except these developing techniques, we may try to find another way to achieve our goal in the future.
in frequency spectrum that is high. Adding some random jitter may reduce the height of this tone, but the spectrum may spread into a wider range. Which one of them generates less interference to other circuits can be investigated in the future. If the spread spectrum is the answer, how to inject a random jitter but not affect the stability of the converter is another interesting topic.
R
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