S TRUCTURE OF THE M ONOLITHIC B UCK C ONVERTER

In this section, we will briefly introduce the structure of current-mode PWM and PFM operation in the developed monolithic buck converter [45], [64].

3.2.1 PWM

At moderate to heavy loads, the converter operates in PWM mode. The block diagram of a simplified current-mode PWM buck converter is illustrated in Fig. 3.1. A clock pulse at the R (reset) input of SR Latch initiates the switching period, causing the latch output Q to be low. The latch output Q goes through Buffer and Dead Time Control to produce both DH and DL low to turn on the high side PMOS transistor and turn off the low side NMOS transistor. While the high side transistor conducts, its current is equal to the inductor current. This current increases in a certain positive slope according to the inductor value and converter voltages. We sense the high side transistor current and compare it with the control voltage VC. When the sensed current

signal becomes higher than control voltage VC, the modulator output will be high to set the SR Latch output Q high. Again the latch output Q goes through Buffer and Dead Time Control to produce both DH and DL high to turn off the high side PMOS transistor and turn on the low side NMOS transistor until next clock pulse. We see the current controlled through the control voltage VC and thus is named current-mode control. On the other hand, a compensation ramp is added to the sensed current signal to suppress sub-harmonic oscillation at duty ratio > 50% [46].

Fig. 3.1 Simplified structure of current-mode PWM control.

3.2.2 PFM

With decreasing load current, the converter automatically switches into PFM mode in which the power stage operates intermittently, based on load demand. Due to

reduced switching activity at power stage, the switching losses are minimized, and the device runs with a minimum quiescent current and maintains high efficiency. The block diagram of a simplified PFM mode buck converter is illustrated in Fig. 3.2.

Fig. 3.2 Simplified structure of PFM control.

The output voltage is monitored with a voltage comparator. As soon as the output voltage falls below the nominal value, the output of the voltage comparator resets the SR Latch. Through Buffer and Dead Time Control the high side PMOS transistor is turned on and the inductor current ramps up. When a current comparator detects that the inductor current reaches the preset peak current, its output sets the SR Latch and turn off the high side PMOS transistor and turn on the low side NMOS transistor. As the inductor current ramps down, a reverse current comparator detects if

Reverse Current Comparator turns off the low side NMOS transistor to prevent drawing energy from output capacitor back to ground. When the output voltage falls below the nominal voltage again, the next cycle is started. As the load current decreases, the time interval between two successive pulses will become larger and vice versa.

3.2.3 Automatic PWM/PFM Mode Switching

There are many algorithms of switching between PWM and PFM. In this work, we use a hysteresis switching algorithm to prevent repeatedly switching between two modes during steady state operation. The algorithm can be described as follows:

1. In PWM mode, as the load current decreases, the inductor current may ramp to zero before the end of each clock cycle. In order to increase the efficiency, the low side NMOS will be turned off when the inductor current ramps to zero. This action prevents the current flowing in reverse direction from output capacitor to ground through inductor and low side NMOS. Thus the converter enters discontinuous conduction mode (DCM). When the converter operates in DCM, it means that the load current is small and we don’t need continuous full-cycle-pulses to sustain it. If the converter operates in DCM for about 20 μs, it will automatically switch to PFM mode.

2. In PFM mode, the peak current of each pulse is preset to a constant value as described above. We monitor the output voltage to determine when the next pulse should be issue. The next pulse will be issue if the output voltage falls below the nominal value. When the load current increases, the output voltage falls faster and the two pulses in succession will become closer. If the output voltage falls below

the nominal value after the peak current is reached and before the current ramps back to zero, it means that we need to issue the next pulse even before the present pulse is completed. In this condition, the load current is large and the output voltage cannot be sustained with this preset current pulse. Thus the converter will enter PWM mode again.

3.2.4 The Proposed Converter

Fig. 3.3 Functional block diagram of the developed monolithic buck converter.

Fig. 3.3 shows the simplified block diagram of the developed converter chip. It uses PWM and PFM control as described above. Key elements such as on-chip soft-start, DPSS, current sensing, modulator and over-current comparator will be