C ONCLUSION

A compact high efficiency monolithic current-mode buck converter is presented in this chapter. Novel features including on-chip soft-start, dynamic partial shutdown strategy, current-sensing, slope compensation and over-current protection circuits are demonstrated. These techniques reduce pin-outs and external components, upgrade efficiency, reduce circuit complexity and silicon area, ease design effort, ensure safety and can be applied to a wide operating range. The experimental results show that these novel features work well and the converter achieves very good performance at many aspects. The proposed converter is suitable especially for mobile devices that require high efficiency, small size and safety operation.

Fig. 3.12 Simulated waveforms of input current and output voltage during start-up with 2.5 Ω load (about 1000 mA at steady-state).

Fig. 3.13 (a) (b) Measured input current and output voltage during start-up. From top to bottom: Channel 3 is chip enable, Channel 1 is output voltage and Channel 4 is input current.

(a) No load. (b) 12.5 Ω load (about 200 mA at steady-state).

Fig. 3.13 (c) (d) Measured input current and output voltage during start-up. From top to bottom: Channel 3 is chip enable, Channel 1 is output voltage and Channel 4 is input current.

(c) 5 Ω load (about 500 mA at steady-state).

(d) 2.5 Ω load (about 1000 mA at steady-state).

Fig. 3.14 (a) Measured conversion efficiency.

(a)VIN = 3.6 V and VOUT = 2.5 V.

Fig. 3.14 (b) Measured conversion efficiency.

(b)VIN = 4.2 V and VOUT = 2.5 V.

Fig. 3.15 Steady-state waveforms of PFM mode operation. From top to bottom: Channel 1 is output ripple voltage (AC coupled), Channel 4 is inductor current and Channel 2 is switch node LX.

(a) 10 mA load.

(b) 20 mA load.

Fig. 3.16 Steady-state waveforms of the output ripple voltage (Channel 1, AC coupled) and the switch node LX (Channel 2) in PWM mode.

(a) Duty cycle > 50%.

(b) Duty cycle < 50%.

Fig. 3.17 500 mA step load-transient response. Channel 1 is output voltage (AC coupled) and Channel 2 is output current (step from 200 mA to 700 mA and from 700 mA to 200 mA).

Fig. 3.18 Over-current protection test. From top to bottom: Channel 1 is output voltage (DC coupled), Channel 4 is inductor current and Channel 2 is switch node LX.

(a) Normal operation with 2.5 Ω (about 1000 mA) load. (VOUT = 2.5

V)

(b) The converter is over-loaded (RLOAD = 1 Ω). The peak inductor current is limited to 1.28 A and the output voltage falls from 2.5 V to about 1.2 V.

(c) Increasing the load demand (RLOAD = 0.5 Ω) causes output voltage to fall to about 0.6 V but the peak inductor current is still limited to 1.28 A.

(d) Further load demand (RLOAD = 0.33 Ω) causes output voltage to fall to about 0.4 V but the peak inductor is still limited to 1.28 A.

Table 3.2 Summary of performance

Table 3.3 Performance comparison

C HAPTER 4

P RACTICAL D ESIGN AND L AYOUT

C ONSIDERATIONS

4.1 I

Most integrated circuits process signals rather than power. For power IC designers, there are many practical design and layout considerations different to the conventional signal processing (analog and digital) ICs. Since we deliver power to others, the current flow and power consumptions are usually large. How to ensure safety operation is one of the designer’s task. How to gain the lowest RDS(ON) of the power transistors and use the smallest area is one of the major issues. In typical SMPS IC design, the RDS(ON) of the power transistors are usually several tens to hundreds of milli-ohm. When the resistance of a transistor switch is as low as the resistance of several squares of metal lines, to scale down the RDS(ON) is not only about enlarging the width of the power transistor. But we need to consider the resistance of metal routings. The switching noise is another big issue especially in SMPS ICs. We usually have huge power transistors that carry hundreds or thousands of milli-ampere of electric current and the power transistors continuously switch in hundreds of kilo-hertz in SMPS ICs. The switching noise is quite large. The ground bounces generated by the parasitic inductance of the bond wires are also a big issue. Since the current is discontinuous in the power switch of SMPS, the slope of current variation versus time is very large at every on/off state transition of power transistors. The

ground bounces caused by the parasitic inductance is proportional to the slope of the current variation versus time:

dt L di

V_inductor = _parasitic (4.1)

Improperly design will raise the bounce voltage to several volts. The control signals may totally be destroyed and the SMPS IC will not work. Dead time control of the power transistors is also important. The above issues are not only concerning about the function of the SMPS ICs but also concerning about the performance like conversion efficiency and stability of the SMPS ICs. These practical issues will be discussed in this chapter.

4.2 D

C

4.2.1 Protection Functions

The protection functions are important in power supply design as described in section 2.4. We need to make sure the power supply will not destroy itself and the devices supplied by it in abnormal conditions. We had discussed about the inrush protection and over-current protection of the demo chip in chapter 3. Now we will briefly discuss about over-temperature protection, over-voltage protection and short-circuit protection in our design. These protection functions are also integrated in the monolithic current mode buck converter described in chapter 3.

The temperature sensor is a simple bipolar transistor. For a bipolar device we know that the VBE has negative temperature coefficient [76]. We can use this characteristic of bipolar devices to generate the over-temperature alarm as shown in

Fig. 4.1. When the temperature is higher than the safety threshold of our design, the over-temperature signal will be issued and the power transistors will be turned off immediately. Thus the heat energy will not accumulate further. An important issue should be noted that the temperature sensor must be placed as close as possible to the heat generator center (usually the power transistors) to eliminate the temperature gradient effect in the chip. But the temperature sensor cannot be placed too close to the switching power transistors since the substrate of the power transistors usually have great noise and bouncing signals on it. These noise and bouncing signals may cause false over-temperature alarms and interrupt the power supply.

Fig. 4.1 Over temperature detector.

The over-voltage protection can be easily implemented using a voltage comparator. When we detect that the output voltage is greater than the tolerance of the specification, the over-voltage signal will be issued to turn off the power transistors.

Thus the output voltage will stop going higher. In buck converters, sometimes the over-voltage condition is caused by short circuit of the high side power switch. Thus we may need to turn on the low side power transistor to force the output voltage to go down. Considering the above case, the low side power transistor must have lower on-resistance than the high side power transistor does.

The short-circuit protection is important in power supply design. Take the buck converter as example. As shown in Fig. 4.2, when the output is short to ground, i.e.

V_OUT = 0, the ramping down slope of inductor current will approach zero. When the high side power transistor is turned on, the inductor current is going higher and keeps its value even the low side transistor is turned on in the later half of the cycle. As we turned on the high side switch, the inductor current will going higher and scarcely going down. So we cannot repeatedly turn on the high side power switch without inductor current accumulation. Thus we cannot prevent the inductor current going higher and higher by only sensing the current flowing in high side power transistor.

This time we need to sense the low side current and keep the low side power transistor turned on until the current is lower than a safety threshold. Another simpler approach is lower down the switching frequency when the output voltage is lower than a safety threshold. In this approach, the accumulation of the inductor current can be eliminated by the longer on time of the low side power transistor. Care must be taken when using this approach. The turn on time of low side power transistor must have enough margins to ensure safety operation.

Fig. 4.2 The inductor current waveform of a buck converter when VOUT is short to ground.

4.2.2 Dead Time Control

Dead time control is important in SMPS IC design. Improper design may cause efficiency loss. The body diode of the power transistor will be turned on during dead time. The effective resistance of body diode is usually much larger than the power transistors. For integrated power transistors, the conduction of body diode may cause huge substrate current. The substrate current may cause latch-up or affect the functions of the controller. But if the dead time is too short, the shoot-through current in the power transistors will cause great efficiency loss and switching noise. There are many approaches to control the dead time [77]-[79]. Many of them use complex circuits but still cannot ensure exact controlling of dead time. In our design, we use a simple circuit to implement dead time control. This approach still cannot exactly control the dead time according to the load condition, but it can provide relative good control over process and temperature variations.

Fig. 4.3 Dead time control using biased inverters to sense the gate voltage of power transistors.

As shown in Fig. 4.3, the gate voltage of power transistors is sense by a biased CMOS inverter. The PMOS of the sensing inverter has the matching characteristics with the high side power PMOS, but the NMOS in the inverter is a long channel transistor. For the low side sensing inverter, the NMOS has the matching characteristics with the low side power NMOS but the PMOS is a long channel transistor. As the VGS of the power transistor goes below the threshold voltage VT of the transistor, i.e. the power switch is turned off, the sensing inverter issues the release signal and the other power switch can be turned on. Thus we can eliminate the shoot-through current of the power transistors. If we can shorten the delay from the sensing inverter to the gate of the other power switch, the dead time can be shortened and the extra loss caused by the body diode conduction can be minimized. We can use another sensing inverter to ensure that the low side NMOS turned on after the VLX

goes low. Thus we can track the load condition in a limited way. Since the power transistors are very large, the layout of dead controller is also important. The layout issues will be discussed in the next section.

4.3 L

C

The layout style can greatly influence the performance of analog ICs. For SMPS ICs, most layout issues are concerning the power transistors. Proper layout can reduce the switching and bouncing noise caused by the switching power transistors. The influence of these noises to the control circuits can also be reduced. Since the power transistors are usually very large, the gate capacitances and parasitic resistances of the power transistors are also a considerable problem. The propagation time of the on/off signal through the whole power transistor can affect the operation of dead control and current sensing. The RDS(ON) of the power transistor is an important specification. How

to efficiently use the silicon area to get the lowest RDS(ON) possible is a real problem.

In this section, we will deal with these problems.

4.3.1 Grounding of SMPS ICs

In mixed-signal IC design, we need to consider how to deal with “analog ground” and “digital ground” [76]. In SMPS IC design, we have a “power ground” in addition to the “analog ground” and “digital ground”. Take the buck converter for example, the current flow through the power ground is in a pulse shape as shown in Fig. 4.4. The height of the current pulse is depending on the load conditions. The slopes of the current versus time during on/off transitions are hundreds milli-ampere over several nano-second. According to (4.1), if we assume the parasitic inductance of the bond-wire and the pin lead of the package is about tens nano-henry, the ground bounce caused by the current pulse can be hundreds milli-volt to several volts.

Fig. 4.4 Current waveforms of the power ground and the input of a buck converter that cause bouncing at both power ground and VIN.

If we connect the analog ground to the power ground on the chip, the analog signal including the reference level would be totally destroyed. If we connect the digital ground to the power ground, the level of analog to digital interface will also suffer great influence. The digital gates controlled by the analog parts may issue wrong pulses. The wrong signal will propagate through the consecutive gates and generate more wrong actions. From this point of view, if we divide the power ground and the digital ground at the very tail of the whole controller, the effect of ground bounce will be minimized. So we can connect only the power transistors to the power ground. But this connection will cause another problem. When the power ground bouncing, the voltage level of power ground may be negative to digital ground and the difference may be larger than the turn on threshold of the power transistor as shown in Fig. 4.5. Thus the power switch may conduct current when it should be turned off. The high side power switch and the low side power switch will form a short path between input and ground. Since the RDS(ON) of power switches are very small, the shoot-through current will be very large. The input voltage will suffer abnormal drop and the efficiency will be degraded.

Fig. 4.5 Ground bouncing of “power ground” that cause false conduction of the power transistor.

To avoid this condition, we can connect the last buffer stage, which directly drives the power transistors, to the power ground. If the power ground bounces to a negative voltage, the gate of power transistor will be pulled as low as the bouncing voltage would be. Then the effect of ground bounce can be minimized. In addition to ground, the bouncing will happen at input or output node of the converter according to the converter topology. The solution of the ground bounce of a buck converter can be extended to solve these problems.

4.3.2 Gate Routing of Power Transistors

The gate widths of the power transistors in SMPS ICs are usually tens to hundreds milli-meter. The turn on/off delay of the power transistors will be much longer than typical digital gates. This long delay time will affect the slope of current versus time of the current pulses, the dead time control and the current sensing.

As described in previous section, the slope of current versus time of the current pulses is very large and may cause serious ground bounce. There are two ways to reduce the magnitude of the ground bounce. One of them is to reduce the parasitic inductance of the bond-wires and the package. The other is to reduce the slope of the current versus time of the current pulse. Since reduction of the parasitic inductance of the package is beyond the scope of our topic, we will try to reduce the slope of the current versus time of the current pulse. Now we can utilize the long turn on/off delay to reduce the bouncing effect. As shown in Fig. 4.6, we can route the gate of the power transistor as S-shaped. The on/off signal will propagate through the gate of the power transistor along the S-shaped gate. The power transistor will be turned on/off from one end to the other sequentially. The on-resistance of the power transistor will

between power transistors, and the slope of current versus time of the current pulse can be reduced. Thus we can reduce the magnitude of the bouncing. But if the turn on/off delay is too long, we will suffer from both shoot-through current and body diode conduction. Both of them will degrade the conversion efficiency and may cause additional switching noises. When body diode conduction occur, the slope of the current versus time of the current pulses cannot be further reduced because there exists another relative low impedance way to conduct inductor current. So we must keep the propagation path in a reasonable length and carefully avoid these unwanted effects.

Fig. 4.6 S-shaped gate routing of power transistor for reducing ground bounce.

This long turn on/off transition time will also affect the dead time control since we are sensing the gate voltage of the power transistors as described in section 4.2.2.

If we want to avoid the shoot-through current, we need to ensure the sensed power transistor is turned off before we can issue the turn on signal to the other power transistor. From this point of view, we should sense the gate voltage at the tail of the gate routing. But if the delay time from the sensed turn off signal to the succeeding turn on signal is too long, the body diode conduction will occur. So we must keep the

delay time of sensed turn off signal to the succeeding turn on signal as short as possible.

Fig. 4.7 Improving accuracy of current sensing by Kelvin connection.

Another effect of the long turn on/off transition time is about current sensing. For accurate current sensing, our goal is to keep the proportionality of the sensed current to the current flow in the power transistor. So we need to bias the current sensing transistor to the same biasing condition of the power transistor. But the power transistor is very large and the propagation time of the gate voltage is long. We need to connect the gate of the current sensing transistor to the tail of the gate routing of the power transistor to ensure the sensed signal will not be affected by the switching activity. A very short blanking time can be inserted to eliminate the unwanted current peak at the beginning of a sensing cycle. In addition, since the current flows through the current sensing transistor, we can connect the drain side of the current sensing transistor using Kelvin connection as shown in Fig. 4.7 [80]. The accuracy of the current sensing circuit will be enhanced.

4.3.3 On-Resistance of Power Switches

The conversion efficiency is directly affected by the on-resistance of the power switches. For integrated power switches, the on-resistances are tens to hundreds milli-ohm. The width of the power transistor are tens to hundreds milli-meter. The power transistors usually occupy more than 50 % area in an SMPS IC. How to reduce the area occupied by the power transistor without sacrificing the on-resistance is an important topic.

Since the on-resistance of the power transistors are in the same order as the resistance of several squares of metal lines, the metal routing will account for

Since the on-resistance of the power transistors are in the same order as the resistance of several squares of metal lines, the metal routing will account for