Dynamic Partial Shutdown Strategy (DPSS)

For extension of battery run time of portable devices, dynamic power management uses sleep mode which shuts down unused circuits to save power during stand-by mode [44]. However, in active mode, it cannot save the power consumption because of the full operating current. In this paper, the dynamic partial shutdown strategy (DPSS) controlling the turn off of partial circuits is proposed to save the

power consumption, especially in active mode. During active mode, only the essential parts will be turned on in specific operating situation under DPSS. As a result, the power consumption is minimized and battery run time is extended.

In a switch-mode power supply, the decision of when to turn on or turn off switches was made according to the output voltage and current condition in each switching cycle. When the switch is on, we need to decide when to turn it off; when the switch is off, we need to decide when to turn it on again. According to this characteristic of switch-mode power supply, we can turn off partial circuits which are not needed to decide when the switch should be turned off during “ON” state and vice versa. Since there are digital signals indicating the ON and OFF states of the power switches in the converter, we can use these digital signals to turn on and turn off the partial circuits which are not needed in each state.

Take the proposed converter as an example. In Fig. 3.5 and Fig. 3.6, we use horizontal, vertical and oblique lines to indicate shut down parts. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off. Fig. 3.5 shows circuits operate in PWM mode; and Fig. 3.6 in PFM mode. Note that the soft-start time has been completed and the Soft-Start in Fig. 3.5 and Fig. 3.6 is always shut down.

In PWM mode, when high side PMOS is turned on, the slope of inductor current is positive. So we don’t need to detect reverse inductor current and the Reverse Inductor Current Detector can be turned off. When low side NMOS is turned on and that the slope of inductor current is negative, there is no need to detect the over-current and the Current Sensing and Over-current Comparator can be shut

down.

Fig. 3.5 DPSS in PWM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on.

Since the slope of inductor current is negative, the Over-voltage Comparator cannot do anything more to prevent output voltage from going too high. Thus the Over-voltage Comparator can be shut down. Besides, the next turning on of high side PMOS is decided by clock pulse in constant frequency leading edge modulation [70].

The Saw-tooth Generator, Analog Adder and Modulator can also be shut down.

In PFM mode, the Error Amplifier, Oscillator, Saw-tooth Generator, Analog Adder and Modulator all can be shut down. When high side PMOS is turned on, only

Comparator and Reverse Inductor Current Detector can be shut down. When low side NMOS is turned on, the Current Sensing and Over-current Comparator can be shut down. When both high side PMOS and low side NMOS are turned off, only the Voltage Comparator is active to decide when the high side PMOS should be turned on again.

Fig. 3.6 DPSS in PFM mode. Blocks with horizontal lines are shut down when high side PMOS is turned on. Blocks with vertical lines are shut down when low side NMOS is turned on. Blocks with oblique lines are shut down when both power transistors are turned off.

When using DPSS, care must be taken as dealing with analog signal level between ON and OFF states. For example, if the analog signal level of the Current Sensing is not preset correctly when the Current Sensing is turned off, the Current

Sensing may give wrong information about the inductor current at the beginning of next cycle. This wrong information may result in unstable operation. On the other hand, timing of digital signal is also an important issue. For example, if the Over-voltage Comparator is not turned on slightly before the next cycle, the next pulse may cause the output voltage goes even higher during transient conditions. This high voltage may damage the circuits in load stage.

Simulation results show that in PWM mode, operating current can be reduced from 500 μA to 250 ~ 300 μA, depending on the duty ratio. In PFM mode, operating current can be reduced from 200 μA to 50 μA. The reduced operating current can effectively boost conversion efficiency especially in light load operation. For example, when VIN = 3.6 V, VOUT = 2.5 V and ILOAD = 1 mA, the conversion efficiency is 89%

and 75% with and without DPSS, respectively. Higher input voltage and lower load current will increase the difference. When VIN = 4.2 V, VOUT = 2.5 V and ILOAD = 1 mA, the results are 88% and 72% with and without DPSS, respectively. When VIN = 3.6 V, VOUT = 2.5 V and ILOAD = 0.5 mA, the results are 84% and 62% with and without DPSS, respectively.