Design of current-driven pixel with poly-Si TFT

With high mobility, high transconductance and implementation capability of p-channel device, poly-Si TFT technology is beneficial for current-driven AM-OLED to compensate the threshold voltage and mobility variations due to non-uniform grain size and time-related electrical stress. The schematic of pixel electrode circuit based on SI memory as well as the timing diagram are shown in Fig. 5-2. The operation of the pixel electrode circuit operates can be defined into programming and reproduction periods. In the programming period, the scan line signal is HIGH to turn on T1 and T2, then the input data current IDATA flows through the transistors T1, T4, and OLED to the ground. Since the drain and gate electrodes of T4 are connected together by T2, the gate voltage of T4, VG4, is automatically charged to a suitable value for the flow of this current and then stored in storage capacitor CST, as shown from Eq. 5-1 to Eq. 5-3 where µFE, COX, W and L are field-effect mobility, capacitance of gate oxide per meter square, width and length of TFT.

(a) (b)

Fig. 5-2. (a) Schematic diagram of 4-T current-driven pixel electrode circuit. (b) Timing chart of pixel operation. ( (1) programming and (2) reproduction period )

( )

L C W V

V

I_{DATA 4 GS4 TH} ² _{4 FE OX} ⁴ 2

,

β

µ

β

=

Eq. 5-1

Therefore the overdrive voltage is

4

4 _{TH DATA}

β

GS V I

V − =

Eq. 5-2

Since the source voltage of T4 is equivalent to the OLED voltage VOLED, the T4 gate voltage is

OLED TH

DATA

G I V V

V ₄ =

β

Eq. 5-3

The voltage VG4 is variable and can be different from pixel to pixel and from time to time, according to the desired current flow and the magnitude of the VTH shifts of both OLED and T4 of the addressed pixel. If an OLED and/or T4 threshold voltage variation appears, VG4 will always be set to ensure the desired OLED current corresponding the precise data current supplied by external driver. In this manner, the OLED current can be maintained to the set-value, no matter how large the VTH shift is for the driving TFT and the OLED.

When the pixel electrode circuit is deselected and the scan line signal is LOW,

both the T1 and T2 are OFF and the pixel operates in reproduction period. At the same time, the T3 is ON due to the opposite polarity of the charge carriers, allowing the current flowing from T3 to T4. Because the gate voltage tracks the threshold voltage of T4, the effect of VTH variation is practically cancelled in this circuit and the constant current ensures a minimum variation of the gray scales. Consequently the threshold voltage shifts of TFTs in this circuit will not have a major impact on the output current and display luminance.

An important issue of this current-driven pixel is a mismatch between the input diving current and output OLED current. Ideally the relationship between these two currents should be linear, however, there are a number of factors resulted in non-linearity in this transfer characteristic and limit the useful current range and thereby also the gray scales. It should be noted that transistor T4 must operate in the saturation mode either during the programming or reproduction periods. In other words, nonlinearity between the IDATA and IOLED will appear as the T4 operates in the undesirable non-linear mode. This is understandable because only in the saturation mode, the transistor can act as a current source in which the current is only dependent on the gate-to-source voltage. In practical, the T1 and T3 are not ideal switches, hence the IDATA and IOLED passing them can generate voltage drops that drive T4 to operate in linear mode. In programming period, a voltage drop between drain and source electrodes of T1 results from the IDATA. The T1 source voltage TS1 equivalent to T4 drain voltage TD4 is smaller than T1 drain voltage TD1. Because no current will pass through T2, the turn-on resistance is like an ideal switch, the T4 gate voltage VG4 is equal to T1 drain voltage VD1. Based on above reasons, the VD4 can be a bit lower than VG4 and T4 may probably work in linear region, consequently, resulting in output current deviation. In order the ensure T4 working in saturation region in programming

period, the overdrive voltage should be defined as following.

The turn-on voltage of scan line is usually set to Vdd which is high enough to make sure the T1 and T3 work in deep linear region. The data current passing through T1 is

( )

Taking account of Eq. 5-5, the non-ideal effect of T1 can be derived as following equation.

It is evident that during the programming period, the size of T1 should be deliberated designed based on Eq. 5-9 to prevent the T4 operation in linear region.

In reproduction period, the non-ideal switch T3 possessing a certain quantity of turn-on resistance can result in a voltage drop as an IOLED passing through it. The drain voltage of T4, VD4,cannot be maintained to Vdd and the decrease of VD4 can force T4 to work in linear region. The design criterion for the reproduction period is

similar to that of programming period and derived as following.

For ensuring T4 operating in saturation region,

TH

Assuming IDATA=IOLED and substituting Eq. 5-3 and Eq. 5-10 into Eq. 5-11, respectively, we obtain

The Eq. 5-12 reveals the design condition of T3 which can keep the T4 operating in saturation region when pixel is in reproduction period.

8 10 12 14 16 18 20

Fig. 5-3. Minimum required β and geometric size of T1 as a function of turn-on voltage of scan line at various width of T4.

The higher turn-on voltage of scan line which is usually identical to Vdd is used,

the smaller necessary size of T1 can be introduced. As shown in Fig. 5-3, a higher voltage applied to the gate electrode of TFT can induce larger channel and result in lower turn-on resistance than a smaller voltage. In other words, the high Vdd can reduce the voltage drop across the drain and source electrodes of T1, moreover, ensuring the operation of T4 in saturation region. Besides, increasing the T4 size from 5 to 30 µm is useful to reduce the T1 size as well. The large T4 can conduct the IDATA

with low gate voltage due to the high transconductance. Consequently, it is difficult to drive T4 into saturation region on account of the voltage drop of T1. In addition, as an OLED material with high quantum efficiency is used, the low IDATA is necessary to achieve adequate display luminance. Therefore, the low IDATA is helpful to reduce the required transconductance and size of T1, because the gate voltage of T4 and the voltage drop of T1 are simultaneously decreased, as shown in Fig. 5-4. In contrast, higher T4 gate voltage is required when decreasing the T4 size at high data current condition so that T4 hardly operates in saturation region, consequently, the T1 size should be increased to maintain the T4 operation in saturation region.

For the aspect of β3, the influence of Vdd and T4 size should be taken into account in pixel design. For a given condition, the transconductance and size of T3 is gradually decreased as the Vdd increases, as shown in Fig. 5-5. In the reproduction period, the higher Vdd can make the drain voltage of T4 distant from the gate voltage so that T4 can be driven into deep saturation region regardless of T3 turn-on resistance, therefore, the size of T3 can be reduced. In terms of the influence of T4 size, the size of T3 should be increased as the T4 size becomes larger. Since the T3 is serially connected to T4 in the reproduction period, its equivalent circuit is similar to two series resistors. In this condition, the decreased T4 resistance associated with the increased T4 size may be much lower than T3 resistance, hence, forcing T4 to operate

in linear region. In order to prevent an operation in linear region, the T3 size should be increased so as to make the resistance of T3 and T4 compete with each other.

0 1 2 3 4 5 6 7 8 9

Fig. 5-4. Minimum required β and geometric size of T1 as a function of input data current I

at various width of T4.

8 10 12 14 16 18 20

Fig. 5-5. Minimum required β and geometric size of T3 as a function of turn-on voltage of scan line at various width of T4.

The high IDATA which induces a large drain-to-source voltage of T3 can decrease the T4 drain voltage. In the meanwhile, the T4 gate voltage becomes higher in large

IDATA condition so that T4 is situated in linear region and causes output current nonlinearity. The design trend is toward the large T3 size when a high IDATA is required, as shown in Fig. 5-6. The large T3 possessing a small resistance which can avoid large voltage drop across the drain and source electrode is helpful to raise the drain voltage of T4 and mitigate the possible operation in linear region. The above equations and analyses are derived by using the basic MOS physical model and can be used as guidelines when designing the current-driven AM-OLED pixels. From these results, the trade-off between the TFT size and supplied voltage or driving current is easily quantified so as to achieve a maximum pixel performance.

0 1 2 3 4 5 6 7 8 9

0.1

1 µ_FE=100 cm²/sec-V

COX=50 µF/m² V_OLED=5 V V_TH=1 V Vdd=12 V L=5 µm

5µm 15µm

β 3 (µF/sec-V)

I_DATA (µA)

Width of T4=30µm

Corresponding T3 width (µm)

Fig. 5-6. Minimum required β and geometric size of T3 as a function of input data

current I

at various width of T4.