Chapter 2 OLED - Organic Light Emitting Device
2.8 Factors that reduce and prevent the degradation in OLEDs
It is possible to reduce the degradation process as the organic materials with higher power efficiency have been developed. Various types of doping of the organic materials can result in higher power efficiency and longer lifetime [44]. As mentioned before, the triplet excited states are able to emit light instead of heat through phosphorescent doping, [37] which can not only yield a higher power efficiency but also reduce the time spent in the excited state. In the excited state, the molecules can be considered more reactive and can cause a degradation of the emitting layer due to unwanted chemical reactions. The reduction of triplet excited states would also lead to less heat generated and consequently to a better lifetime of the device.
Multi-layer structure can also bring a longer lifetime [24]. Depending on layers order designed, the lifetime can be possibly extended. The emitting layer plays a great role by affecting the lifetime as a result of its position. The addition of a hole
transporting layer enhances the lifetime by function as a stabilizer for the flow of holes and also in an overall better power efficiency due to more recombinations. Both transporting layers not only function as transport medium but also in some case function as buffer layers preventing humidity and oxygen to diffuse into the active emitting layer.
Due to the fact that OLEDs degrade under high temperatures, cooling is another effective method in order to achieve a longer lifetime. How the displays are fabricated is a factor in the desire of enhancing the lifetime, the process can be undertaken in vacuum or under great pressure or in some cases at low pressure, depending on materials used. During manufacturing the conjugated polymers and the small molecules are very sensitive to UV-light in combination with humidity. The fabrication has to be precise because the structure asymmetry and varying thickness of the layers are sources for local heating which can lead to damages on the display.
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Chapter 3
Addressing scheme for OLED displays
A display is an array of controllable pixels and the number of which depends on the dimension and resolution required by a particular application. For example, specifications of desktop monitor may emphasize higher visual performance, such as higher spatial resolutions and higher pixel content. The addressing of a large number of pixels in an array is an important issue in the display technology. Among the five addressing schemes used in electronic display [1], matrix addressing is the most suitable for OLED-based display system. In a matrix addressed display, pixels are arranged in rows and columns, and each pixel is electrically connected between one row electrode and one column electrode. The matrix addressing where active switch devices are added to the pixels are called active-matrix (AM) addressing. While the array without any active component in the pixels is termed as passive-matrix (PM) addressing.
3.1 Passive-matrix addressing
A passive-matrix array consists of two sets of electrically isolated conducting electrodes arranged orthogonally with an OLED to form the pixel at each intersection, and connected to the external drivers that supply the necessary voltage and timing sequence.
Fig. 3-1(a) and (b) show the electrical schematic and functional
cross-sectional diagram of a PM-OLED, respectively. Normally, the display is scanned or multiplexed row by row from the top to the bottom at a rate that is sufficient to produce flicker-free images (> 60Hz). To turn on a pixel, a certainvoltage needs to be decreased across the OLED material. The row electrode delivers a fraction of this voltage, and the column electrode provides the remainding.
(a) (b)
Fig. 3-1. (a) Schematic diagram of passive-matrix OLED panel. (b) Cross-section view of passive-matrix OLED structure.
A pixel receiving only part of the full voltage will be off. This row-at-a-time mode is chosen to maximize the pixel duty factor (defined as the percent of the total time each pixel is driven into the ON state by the column signal). The pixel duty factor of such a row-scanned array is 1/Ns, where Ns is the number of scan electrodes. Since the selected pixel must be driven with a pulsed voltage signal at a duty cycle, instantaneous luminance L0 should be high enough to achieve an average display luminance Ld:
d s L N
L0 = ⋅
Eq. 3-1
Even the EL response time of small-molecule OLED has been found to be < 1 µs [2], sufficient for most pulse-driven passive matrix, the number of rows in an array may limit the average display luminance [3][4]. However, this PM addressing approach limits the contrast and restricts the format of the display to smaller pixel counts [5]. For example, an instantaneous luminance should be about 10000 cd/m2 to achieve an
average luminance of 100 cd/m2 for a passive-matrix display with 100 rows, In addition, this approach requires patterning of both the row and column electrodes, which is difficult if the most common electron injecting materials (Al-Li, MgAg) is used as the column electrode. Besides, the high driving voltage and the instantaneous driving current corresponding to the high instantaneous-luminance requirement can also lower the OLED power conversion efficiency and OLED lifetime.
3.2 Voltage-type active-matrix addressing
Active-matrix addressing overcomes the crosstalk limitation of passive-matrix by integrating switching devices at the cross point of the row (scan or gate) and column (data) lines, and thereby isolating the off pixels from these select voltage lines. The TFT active-matrix array designs are commonly optimized using computer simulations to analyze electrical performance based on statistically extracted TFT and fabrication process parameters. While this approach is the most accurate way to predict the statistical mean and variance in display performance, it is more instructive to carry out a simple, physically based parameter analysis to identify functional dependencies, performance limits, and minimum requirements. The analysis presented here is applicable to any kind of TFT processing technology.
Using an active-matrix addressing can solve the image contrast and column electrode pattering concern of passive-matrix addressing. In the AM addressing, a transistor is placed at each pixel to separate the effect of the data line (column electrode) voltage and the scan line (row electrode) voltage on the voltage across the OLED material. A common cathode material (MgAg, Al-Li) is used to eliminate the need of patterning the electron injecting electrode. Within AM-OLED designs, a variety of pixel architectures have been proposed [6]. Different pixel architectures may
contain different numbers of transistors per pixel. The simplest design uses one transistor per pixel which is similar to the pixel circuit for AM-LCD, as shown in Fig.
3-2. A single transistor design approach has the advantage of increased contrast by
isolating the data line and scan line from OLED compared to a passive matrix design, and will have a higher yield than other designs containing more than 1 TFT per pixel.However, in this approach the voltage signal in storage capacitor CST is leaking out through OLED even the TFT TSW is OFF, so that the luminance cannot be kept constant during entire frame time. Therefore, each pixel is needed to pulse ON for a duty factor 1/Ns of the frame time. This requires the instantaneous OLED current to be much higher than the average current, which still leads to faster degradation of the OLED material.
(a) (b)
Fig. 3-2. (a) Conventional single-transistor-single-capacitor (1T-1C) pixel circuit for AM-LCD. (b) 1T-1C pixel circuit for AM-OLED using OLED instead of LC.
The pixel circuit for AM-OLED must have a function to generate the stable driving current for the OLED throughout one frame period to avoid the high current pulse native to the single TFT design. A pixel design involving two transistors using n-channel TFTs is shown in Fig. 3-3(a). When a scan line is selected, the voltage
signal VDATA from data line is written via the switching transistor TSW to the gate of the driving transistor TDV. The written voltage VDATA is thereby retained in CST for a complete frame period. Driving transistor TDV operates in the saturation regime where the OLED driving current has little dependence on the source-to-drain voltage. This pixel circuit allows the pixel to deliver a small current during the entire frame period.
(a) (b)
Fig. 3-3. Double-transistor-single-capacitor configuration of AM-OLED pixel circuit with (a) n-channel driving TFT (T
DV) and (b) p-channel T
DV.
Though the average current through the OLED material is the same, the peak current is greatly reduced which leads to increased brightness and OLED material lifetime.
The OLED driving current IOLED generated by n-channel TDV is
( )
22 1
th OLED DATA
DV DV OX FE
OLED V V V
L C W
I =
µ
⋅ ⋅ ⋅ − −Eq. 3-2
where µFE, COX, WDV, LDV, VOLED and Vth are the field-effect mobility, gate oxide capacitance per unit area, channel width, channel length, OLED cross voltage and TFT threshold voltage, respectively. With n-channel TDV configuration, designing data voltage VDATA should take consideration of the OLED voltage. In other word, the VDATA includes not only the over-drive voltage of TDV but also the OLED cross
voltage so that the voltage swing is large. The pixel circuit can also be implemented with p-channel TFT as shown in Fig. 3-3(b). Since the most commonly used technologies for conventional AM-LCD are a-Si and poly-Si TFTs, both of them are compatible with large area glass substrate processes, which is necessary to fabricate displays at reasonable cost. Poly-Si TFT technology was chosen for AM-OLED display because of its higher mobility and greater stability compared with a-Si TFT. In addition, poly-Si TFT technology has ability to provide p-channel devices for not only pixel circuits but also integrated drivers. The performance of p-channel TFT is typically lower than that of n-channel TFT made from the same material. However, as p-channel TFT is used as driving transistor TDV in pixel design, the gate-to-source voltage of TDV is related to the gate node and Vdd electrode and the driving current can be expressed as:
( )
2According to this configuration, the OLED turn-on voltage is of little significance to the driving current, therefore the voltage swing can be reduced. The OLED driving current as a function of data voltage in n-channel and p-channel TDV
configurations are shown in Fig. 3-4. As discussed above, the swing of VDATA for n-channel TDV is 4V in order to achieve the maximum driving current or 1.7 µA, almost a factor of three larger than that of p-channel TDV. Although the n-channel TFT has higher mobility than p-channel TFT, the large data voltage swing increases the high transient power consumption as well as the long charge-up time for the pixel circuit. Besides, the degradation of OLED material may affect the OLED threshold voltage and then change the gate-to-source voltage of TDV, consequently, resulting in the luminance variation. Due to the native property of p-channel TFT, the stable luminance can be achieved by the voltage-to-current conversion of TDV regardless of
OLED degradation. The small data voltage swing can speed up the programming time and reduce the power consumption. Nevertheless, it should be noted that the resistance against to the noise must be high enough when design the gray levels of AM-OLED because the small voltage swing leads to the small voltage step between each gray level.
Fig. 3-4. OLED driving current as a function of input data voltage at different types of T
DV: (a) n-channel T
DV, (b) p-channel T
DV.
3.3 Definition of operation point
Since the pixel circuit with p-channel TFT in Fig. 3-4(b) can be similarly analyzed as the n-channel TFT in Fig. 3-4(a), the following discussion only focuses on the pixel electrode circuit with n-channel TFT. The ID–VDS characteristics of an n-channel TFT are shown schematically in Fig. 3-5, along with the load line resulting from the OLED I–V characteristics. The knees in the ID–VDS curves between the linear and saturation regimes are at VDS=VGS-Vth, and the saturation current
is
( )
2 of the TFT respectively [7]. The criterion for the operation in the saturation regime isOLED th
GS V Vdd V
V − ≤ − , i.e.
(
DV DV)
OX FE
OLED
OLED C W L
V I
Vdd ≥ + ⋅
µ 2
Eq. 3-4
where IOLED is the OLED drive current required to achieve full brightness, and VOLED
is the corresponding OLED voltage. A low Vdd is desirable to achieve low-panel power consumption and to make the technology suitable for portable, battery-powered applications. The power penalty due to the introduction of TDV is ∆P=VOLED Vdd. For a pixel driven to full brightness, ∆P=1+
(
2IOLEDµ
FE⋅COX ⋅(
WDV LDV) )
Vdd . The channel width of TDV, i.e. WDV, is limited by the pixel dimension, channel length LDV is limited by short channel effects; COX is determined by the oxide layer thickness and material properties, and depends on the channel material.Fig. 3-5. Operation point calculation according to the loading line of TFT and OLED.
The average current necessary to produce a bright display (100cd/m2) is approximately 10mA/cm2[8]. If we assume a pixel size of 150µm x 150µm, an OLED driving current of 2.25µA is necessary. Assuming a TFT operating in saturation region,
the required field-effect mobility can be calculated according to
(
DV DV2)
OX(
GS th)
2OLED
FE W L C V V
I
= −
µ
Eq. 3-5
To achieve the proper current levels using small device geometry i.e. WDV/LDV=2, and a thin gate oxide layer, a high mobility is required. Since amorphous silicon cannot be used because of mobility less than 1 cm2/V-s and therefore cannot deliver enough current, polysilicon based transistors becomes the better choice for AM-OLED’s. It is important to note that the quantum efficiency of OLED material is substantially improved in recent days. As a result, the mobility requirement is much less and, strictly from a drive current perspective, a-Si TFTs may be adequate.
3.4 Pixel voltage error due to parasitic capacitance of TFT
The switching TFT TSW in the pixel operates as an analog switch, whereby, when the gate of the TFT in turn-on, it is desired that the TFT can accurately transfer a precise data voltage to the CST and the gate of TDV. The available precision of charging up the total pixel capacitance to the data voltage depends on many factors, most of which are physical dimensions related to the fabrication and layout design process. The TFT parasitic capacitances CGD and CGS are determined by the overlay area between the drain and gate electrodes, and the source and gate electrodes, respectively. The smaller the channel length, the larger the parasitic capacitance can be formed from overlap area. Therefore, the TFT parasitic capacitance is minimized by making the area of the drain, source, and gate electrodes as small as possible or by increasing the thickness of oxide insulation layer.
The design of TSW is similar to that of the switching transistor in AM-LCD [9][10]. Assume that the gate voltage of TSW is VG-SW=VH when a scan line is addressed, and
the voltage on the data line is VDATA. At the end of the charging period, the pixel capacitance, CPIX (the sum of the storage capacitance CST, the CGD, and the CGS of TDV), stores charge CPIX·VDATA, while the CGS of TSW stores charge CGS-SW(VDATA-Vth).
When VG is brought to zero, the CPIX and CGS-SW form a voltage divider of transfer ratio CGS−SW
(
CGS−SW +CPIX)
. During the holding period, the voltage at the gate of TDV (also the storage node) can be expressed as⎥⎦
To have VG-DV≈VDATA during this period, it is important that CPIX>>CGS-SW, therefore necessitating a separate storage capacitance. Even with a large CST, VG-DV is still small than VDATA due to the CGS during the holding period. To eliminate this difference, the CST can be connected to the previous scan line instead of ground to form the “CST on
To have VG-DV≈VDATA during this period, it is important that CPIX>>CGS-SW, therefore necessitating a separate storage capacitance. Even with a large CST, VG-DV is still small than VDATA due to the CGS during the holding period. To eliminate this difference, the CST can be connected to the previous scan line instead of ground to form the “CST on