Chapter 5 Current-Driven AMOLED with Fully Integrated Drivers
5.4 AM-OLED with integrated current-type data driver
5.4.3 High-performance current memory
The switch current memory has been widely used in digital-to-analog converter and analog sampled-data signal processing applications [8][9], since they exhibit superior tolerance to device parameter variations. One of the fundamental factors limiting an accuracy of the switch current (SI) memory is the charge injection occurring when the transistor turns off [10]. The amount of charge a TFT carries in its channel when the gate voltage applied can be expressed as
(
GS TH)
OX
ch W L C V V
Q ≈ ⋅ ⋅ −
Eq. 5-13
As the TFT turns off, this charge is released from the channel to the source and drain terminals and affects the voltage at both these terminals. The voltage offset appears as a nonlinear term at source and drain terminals because Qch is interrelated to the source and drain voltages. The accuracy of SI memory depends upon how to protect the critical gate voltage because the variation of gate voltage can lead to a different reproduced current from the input current. The low sensitivity to the charge injection mechanism of SI memory can be realized by several methods such as:
1) the usage of complementary switch for the partial cancellation of the charge injection.
2) the usage of large capacitance for the reduction of the voltage offset at critical node.
The first method eliminates the charge injection in terms of the carriers that cancels each other due to the opposite polarities (such as those from n-channel and p-channel TFTs in the complementary switch). However the required additional clock signals increases the amount of connecting wire and control logic as well as complicates the control system. Besides, the parasitic capacitance of connecting wire may induce the clock signals miss-alignment and lose the capability of charge injection cancellation. The other is to increase the storage capacitance to restrain the effect of the charge injection. Nevertheless, the larger storage capacitance requires more charging time to establish the gate voltage during the sampling period, consequently, decreasing the operating frequency.
In this dissertation, a current mirror based SI memory restraining charge injection with one control signal is proposed and designed. The experiment results of SI memory implementation using poly-Si TFT process are also presented.
5.4.3.1 Circuit description
Proposed SI memory designed with current mirror is capable of protecting the critical gate voltage against charge injection. In SI memor circuit, the TFT T0, T1 and T2 build the current mirror, and T3, T4 and T5 act as the switches, as shown in Fig.
5-12. Two capacitors, C
ST1 and CST2, are used as storage capacitors. The proposed SI memory operates in two mode: sampling and reproducing.Vdd
Fig. 5-12. Schematic diagram of proposed SI memory. The circuit samples the current signal in the interval 0 < t < t
1. The circuit reproduces the sampled current in the interval t
1< t < t
2.
1) Sampling mode (Scan = Vdd): The SI memory is connected to external current source by T4. The drain-to-gate voltage of T2 is adjusted roughly to generate the current IT1. Then IT1 sets the the gate voltage of T0 to an appropriate value for generating the current IT0 as the same as the input current.
2) Reproduction period (Scan = ground): The SI memory is connected to the loading by T5 and has a capability of sinking the approximately equivalent current from the loading. T1, T2, and T3 make contribution to functionally protect the critical gate voltage of the SI memory. As the scan signal turns off transistor T3, thereby, the circuit is driven into reproducing mode. The charge carriers stored in the channel of T3 is released and redistributes to the gate of T2 (node A). Therefore, the charge carriers injecting into the storage capacitor results in the gate voltage variation of T2 (∆VA). A parameter gm·VGS, with the transconductance gm defined in saturation region as
is one of the important parameters of the TFT in the voltage-controlled curent source circuit. The current IT1 deviates from the input current due to the gate voltage variation of T2 (∆VA) of gm2‧∆VA as shown in Eq. 5-15, where gm2 is transconductance of T2.
A m
T g V
I = ⋅∆
∆ 1 2
Eq. 5-15
The current IT1 through T1 is changed by charge injection mechanism so that the voltage at node B is also altered as follow
1
As long as T1 and T2 are locally matched, Eq. 5-17 can be simplified as
12
The ratio of ∆VB to ∆VA observed from the theoretical analysis is only dependent upon the geometric size of TFT. At such condition, W/L ratio of T1 should be enlarged to allow ∆VB/∆VA as small as possible. Thus the charge injection mechanism cannot directly affect the critical gate voltage so that the proposed SI memory can effectively achieve the accurate reproducing current by optimizing the size of TFT.
Therefore, not only the small capacitance is acceptable for the proposed SI memory design, but the response time of the SI memory is also improved by reducing the size
of storage capacitance.
5.4.3.2 Experiment
The prototype of the proposed SI memory has been designed and evaluated by taking advantage of the simulation program Synopsis H-SPICE with the Rensselaer Polytechnic Institute (RPI) Troy, NY, poly-Si TFT model [11][12].
Table 5-2 lists the
parameters used in designing the SI memory. Besides, the laser annealing poly-Si TFT technology is used to fabricate the proposed SI memory shown in Fig. 5-13(a).Table 5-2. Parameters for SI memory design.
Device
W/L for T0, T2, T3, T4, T5 (µm) 7/5
W/L for T1 (µm) 7/5, 15/5, 30/5, 50/5 Loading circuit Pixel liked active loading
Cs (fF) 100, 200, 400, 800
µn (cm2/V-sec) 77.4
µp (cm2/V-sec) 85
Supply Signal
Vdd, logic-High (V) 10
Ground, logic-Low (V) 0
Input current (µA) 0.1 ~ 12
The dirct measurement of critical gate voltage of SI memory has severe limitation due to the small storage capacitor of 100 fF. The parastic capacitance of measurement probe, usually several pico-farad, greatly affects the measurement accuracy of the probed node when the falling rate of the critical voltage is high. An additional unit gain operation amplifier can be used to circumvent the problem and to be a better monitor of critical gate voltage. The operation amplier possesses the excellent driving
capability to track the input voltage precisely, therefore, suitable for the interface with measurement system. The pixel-liked circuit is designed as an active loading for SI memory. The entire measurement system diagram is shown schematically in Fig.
5-13(b).
Fig. 5-13. (a) Photograph of porposed SI memory fabricated by LTPS-TFT process. (b) Diagram of SI memory measurement system.
The critical gate node B isolated from switch T3 in proposed SI memory is not perturbed by charge injection directly, as previously discussed. Furthermore,
12
indicates that the increase of geometric size of T1 is beneficial for reducing the critical gate voltage error without using large capacitance. The characteristics of voltage error versus input current with different size of T1 were measured and are illustrated in Fig.
5-14. It is evident that the minor critical gate voltage error is achieved by increasing
T1 size from 7 to 50 µm. Moreover, large storage capacitor still shows great resistance to charge injection, as confirmed in Fig. 5-15. However, the critical gate voltage error still increases as the input current becomes smaller, as shown in Figs. 5-14 and 5-15.As a result, transistors T1 and T2 driven in sub-threshold region of weak current are
more sensitive to the charge injection.
Voltage Error on C ST (V)
Input Current (µA) CST=100 fF
Simulation Measurement
Fig. 5-14. Voltage error at node B in proposed SI memory with different T1 geometric size.
Voltage Error on C ST (V)
Input Current (µA)
W(T1)=7um Simulation Measurement
Fig. 5-15. Voltage error at node B in proposed SI memory with different capacitance.
The conventional SI memory is also implemented with poly-Si TFT process for the comparison of the influence of charge injection with proposed SI memory. The critical gate voltage error at node B for each SI memory was measured in the same
testing condition. Noticeable charge injection casued voltage error can be seen in measurement reults of the conventional SI memory, as shown in Fig. 5-16. The voltage error in the conventional SI memory is around 0.4 to 0.5 V when using a capacitor of 100 fF. By contrast, the voltage error in proposed SI memory with the same capacitance is of less than 0.25 V, almost one half smaller than that of the conventional SI memory. The capacitor of at least 400 fF is necessary to reduce the charge injection induced voltage error less than 0.2 V in the conventional SI memory, therefore, limits the response time of the SI memory.
0 2 4 6 8 10 12
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Voltage Error on C ST (V)
Input Current (µA)
W(T1)=7um
Conventional (Cst=100fF) Conventional (Cst=200fF) Conventional (Cst=400fF) Conventional (Cst=800fF) Proposed (Cst=100fF) Proposed (Cst=200fF) Proposed (Cst=400fF) Proposed (Cst=800fF)
Fig. 5-16. Measured voltage error at node B in both conventional and proposed SI memories with W/L ratio of 7/5.
Critical gate voltage error of less than 0.1 V can be achieved by means of increasing the W/L ratio of T1 up to 30/5 in proposed SI memory with capacitance of 100 fF, as plotted in Fig. 5-17. However, the capacitance of conventional SI memory should be raised to 800 fF so as to accomplish the equivalent voltage error. The above data confirms that the proposed SI memory reveals outstanding resistance to the effect of charge injection even under the usage of the capacitance of 100 fF.
0 2 4 6 8 10 12
Voltage Error on C ST (V)
Input Current (µA)
Fig. 5-17. Measured voltage error at node B in both conventional and proposed SI memories.
Fig. 5-18. Simulation results of response time of both SI memory.
The response time of both conventional and proposed SI memory is evaluated by SPICE program as the isolated critical gate node is difficult to detect directly, as revealed in Fig. 5-18. The response time of proposed SI memory with capacitance of 100 fF is lower than 0.16 µsas the width of T1 varies from 7 to 50 µm. The aforementioned results indicate that the capacitance of more than 400 fF is requisite
for the approximate voltage error in the conventional SI memory. Thus, the larger capacitance results in the response time of more than 0.7 µs, a factor of 4 times higher than that of proposed SI memory.
The experimental results of both conventional SI memory and proposed SI memory are summarized in Table 5-3. The large capacitance of 800 fF in conventional SI memory merely achieves the equivalent voltage error of 0.1 V as that of proposed SI memory with 100 fF capacitance and W/L ratio of 30/5, nevertheless, at the expense of a factor of 4 increase in the response time of proposed SI memory.
However, the area consumption of the proposed SI memory is approximately 1.2 times larger that that of the conventional SI memory due to the usage of 5 TFTs and 2 capacitors. Besides, the power consumption of proposed SI memory is in a factor of three higher than that of conventional SI memory on account of the constant current conducted in T1 and T2 in proposed SI memory.
Table 5-3. Comparison of conventional and proposed SI memory with equivalent voltage error of 0.1 V.
Conventional SI memory Proposed SI memory
Required capacitance (fF) 800 100
W/L of T1 (µm/µm) 7/5 30/5
Response time (µsec) > 0.7 0.13
Layout area (µm2) 7500 9200
Power consumption at 15k Hz
operating freqneucy (mW) 23 68