Chapter 6 Current-Scaling Pixel Electrode Circuit for AM-OLED
6.4 Simulation results and discussion
6.4.4 Scan line delay in high resolution display
The key factor to realize a large size and a high resolution display is to overcome the long resistance-capacitance (RC) time constant of the bus lines of which the resistance and capacitance are proportional to the size and the resolution of display
panel. A large RC time constant can cause cross-talk and flicker effects due to the insufficient pixel charging across the large display area. Since the bus line resistance is due to intrinsic resistance of bus lines materials and capacitance is associated with overlap capacitance of intersections and TFTs, the RC time constant of scan line TRC-SCAN can approximately be estimated by following equation:
[ ]
where H, NH, C□, R□, Z and COV are display width, horizontal resolution, capacitance per meter square, sheet resistance, pixel pitch to bus line width ratio and TFT gate-to-drain/source overlap capacitance. According to Eq. 6-8, it is expected that a larger panel size and a higher display resolution will cause a longer TRC-SCAN which can affect the data programming precision. For C□=150 µF/m2, COV= 0.2 nF/m, and Z=30, TRC-SCAN as a function of display diagonal was calculated for UXGA resolution and for different metallurgy, e.g. copper (R□=0.075 Ω/sqr), aluminum (0.1 Ω/sqr) and molybdenum (1.0 Ω/sqr), Fig. 6-8(a). The scan pulse width TSCAN shown as the solid line in Fig. 6-8(a) is also evaluated for 60 Hz frame rate and for different vertical resolutions. In general, TSCAN should be ten times larger than TRC-SCAN to prevent the data programming error. Therefore, based on this simple calculation, a high-resistance material such as molybdenum will limit the display size to about 12 inch with UXGA resolution. A low-resistance material such as aluminum or copper is capable of reducing TRC-SCAN in large size display up to 35 inch or higher to acceptable value.
0 10 20 30 40
0 500 1000 1500 2000 2500
Csqr = 150 µF/m2
0 500 1000 1500 2000 2500
scan line from Cu
Fig. 6-8. (a) Dependence of scan line RC time constant (T
RC-SCAN) on display diagonal and the relationship between scan pulse width (T
SCAN) and resolution. (b) Data programming time (T
PROG) as a function of panel resolution with a scan line made from Cu.
For AM-OLED, not only the TRC-SCAN but also the data programming time (TDATA) is important. TDATA is directly related to the data line capacitance CDATA, storage
capacitance CST and the programming current IDATA and can be approximated by the
Since the CST is much smaller than CDATA, it can be neglected to simplify the calculation. In Eq. 6-9, VDATA denotes the voltage at CST generated by the IDATA, and NV is the vertical resolution which can be obtained from NH and aspect ratio of display. The constants Cn, CE, and CV depend on the refractive index and the emission spectrum of the OLED material. Besides, L is the OLED luminance and η is device quantum efficiency. It should be noted that the TDATA in Eq. 6-9 is independent of the display size, and IDATA is increased when the pixel area is increased to compensate for large CDATA resulting from the increase of display size. In order to compare the proposed pixel electrode circuit with the conventional pixel circuit and to evaluate its performance, TPROG is defined as TRC-SCAN + TDATA to describe the total time requirement for accurate data programming. Fig. 6-8(b) shows TPROG of proposed pixel as a function of display size for VDATA=5 V, Cn=1.1, CE=0.44 V-1, CV=427 lm/W, L=100 cd/m2, η=5%, C□=150 µF/m2 and RSCALE=20, along with the TPROG of conventional pixel for RSCALE=1. Without current scaling function (RSCALE=1), a VGA display requires TPROG of 60 ~ 70 µs to charge up the conventional pixel electrode circuit which is two times higher than a specific TSCAN of display with VGA resolution.
Therefore, conventional pixel circuit is not applicable for a large size and a high resolution display device. By contrast, the proposed pixel circuit with the current scaling function can reduce the TPROG significantly when a large IDATA is used.
Furthermore, as display resolution increases, the TPROG for UXGA resolution
(1600x1200) is of 8 ~ 9 µs which is lower than a specific TSCAN of 10 µs even for display diagonal of 40 inch. In summary, the proposed pixel electrode circuit with cascade storage capacitance and build-in current scaling capability can allow to achieve a high resolution and a large size current-driven AM-OLED.
6.5 Summary
We proposed a pixel electrode circuit based on poly-Si TFT technology and current driving scheme for speeding up the data programming time. We have shown that this circuit can achieve a high current scale-down ratio by a cascade structure of storage capacitors instead of increasing the size of TFT. In the proposed circuit, the ON-state data current of a factor of 10 larger than OLED current in OFF-state can be achieved. In contrast to the conventional current-driven and the current-mirror pixel electrode circuits, our pixel circuit can achieve the widest range of IAVG for IDATA
ranging from 0.1 to 10 µA, hence, both the current scaling function and the reasonable power consumption can be easily accomplished without substantially sacrificing the pixel aperture ratio. Furthermore, the threshold voltage variation of all TFT can also be compensated by the proposed circuit. The effects of device geographic size mismatch and temperature increase on pixel electrode circuit have been analyzed, and it has been concluded that they are within acceptable range of operation. The calculation of scan line delay and the required programming time indicated that the proposed pixel shows admirable capability to improve the data programming time.
Even though the higher resolution limits the pixel pitch, the proposed pixel can be easily integrated with the top emission OLED without any aperture ratio restriction.
Consequently, this new pixel electrode circuit has great potential for applications in a large size, a high resolution poly-Si TFT AM-OLEDs.
References
1. A. Yumoto, M. Asano, H. Hasegawa, and M. Sekiya, “Pixel-driving methods for large-sized poly-Si AM-OLED displays,” in Proc. Int. Display Workshop, 2001, pp. 1395–1398.
2. J. Lee, W. Nam, S. Jung, and M. Han, “A New Current Scaling Pixel Circuit for AMOLED,”
in IEEE Electron Device Lett., vol. 25, no. 5, May 2004, pp. 280-282.
3. T. Sasaoka, M. Sekiya, A. Yumoto, J. Yamada, T. Hirano, Y. Iwase, T. Yamada, T. Ishibashi, T. Mori, M. Asano, S. Tamura and T. Urabe, “A 13.0-inch AM-OLED Display with Top Emitting Structure and Adaptive Current Mode Programmed Pixel Circuit (TAC),” in Symp.
Dig. 2001 SID, 2001, pp. 384-387.
4. M. S. Shur, H. C. Slade, T. Ytterdal, L. Wang, Z. Xu, K. Aflatooni, Y. Byun, Y. Chen, M.
Froggatt, A. Krishnan, P. Mei, H. Meiling, B.-H. Min, A. Nathan, S. Sherman, M. Stewart, and S. Theiss, “Modeling and Scaling of a-Si:H and Poly-Si Thin Film Transistors,” Mat. Res. Soc.
Symp. Proc., vol. 467, 1997, pp. 831-842.
5. M. S. Shur, H. C. Slade, M. D. Jacunski, A. A. Owusu, and T. Ytterdal, “SPICE Models for Amorphous Silicon and Polysilicon Thin Film Transistors,” J. Electrochem. Soc., vol. 144, no.
8, 1997, pp. 2833-2839.
6. C.-Y. Chen and J. Kanicki, “High-performance a-Si:H TFT for large-area AMLCDs,” in Proc. 26th Eur. Solid State Dev. Reas. Conf.,1996, pp. 1023–1031.
7. Y. Hong, J. Nahm, and J. Kanicki, "100 dpi 4-a-Si:H TFTs Active-Matrix Organic Polymer Light-Emitting Display" in IEEE J. Select. Topics Quantum Electron., vol. 10, no. 1, Jan/Feb 2004, pp.16-25.
8. S. Lee, A. Badano, and J. Kanicki, “Monte Carlo modeling of the light transport in polymer light-emitting devices on plastic substrates”, IEEE J. Select. Topics Quantum Electron., vol. 10, 2004, pp. 37-44.
9. H. Aoki, "Dynamic Characterization of a-Si TFT-LCD Pixels," in IEEE Trans. Electron Devices, vol. 43, no. 1, Jan, 1996, pp. 31-39.
10 . N. Lustig. J. Kanicki, R. Wisnieff, and J. Griffith, “Temperature Dependent Characteristics of Hydragenated Amorphous Silicon Thin-Film Transistors,” Mat. Res. Soc.
Symp. Proc., vol. 118, 1988, pp. 267-272.
Chapter 7
Functionality testing for AM-OLED
7.1 Introduction
TFT array inspection and yield management are important to ensure the reliability of AMLCD, AMOLED and other active-matrix display applications [1][2]. In-line testing of TFT array in manufacturing processes is beneficial for yield improvement because the faulty TFT array can be repaired or scrapped before encapsulation, and external driver assembly. Likewise, utilizing TFT array testing for failure analysis can detect the location of the faults and identify the categories of faults in TFT array.
In conventional AMLCD industry, several inspection technologies have been developed and applied for TFT array testing: 1) the voltage imaging scheme [7], 2) the electron beam scheme [8], and 3) the charge sensing scheme [9]. The voltage imaging and electron beam schemes can inspect all TFT devices on entire substrate regardless of the circuitry configuration but only a few kinds of faults can be detected. Besides, demands of high stability of the instruments and long working time also limit the performance of them. Although the charge sensing scheme requires a large number of contact pins, direct contact and measurement can perform the speedy functional testing and evaluate more parameters of the TFT than the others.
The conventional AM-OLED pixel circuit does not provide for fully functional testing with charge sensing scheme as the AM-LCD pixel does [10], unless an additional component can be added-in. We propose the modified pixel circuit with cooperating charge sensing scheme to measure the characteristics of TFT and detect
defects. The proposed TFT array testing scheme is simulated and demonstrated to be a good tool for managing the yield of the array process of AM-OLED’s.
7.2 Full function testing for AM-OLED pixels 7.2.1 Schematic of pixel circuit
A conventional 2-transistor (2-T) pixel circuit, in which the transistor TSW acts as a switch and the transistor TDV controls the driving current of the pixel, is encircled by dash line in Fig. 7-1(a). Following TFT array processes, organic material is deposited onto the substrate by evaporation or ink-jet printing processes to form the OLED, denoted by the diode symbol in Fig. 7-1.
(a) (b)
Fig. 7-1. (a) 2-T pixel circuit for AM-OLED TFT array testing and (b)layout view of the modified pixel circuit.
However, before the OLED process is performed, the ITO anode of each pixel circuit
is in a floating state so that not only the source voltage of TDV can not be confirmed, but also no path is available for conducting the driving current. The incomplete pixel circuits limit the testability of the TFT array.
A Capacitor-on-Gate (COG) structure which forms an additional testing capacitor (CTEST) is proposed to improve the testability of the AM-OLED pixel electrode circuits. This CTEST ensures the circuit completeness and prevents the floating status of anode before OLED material deposited onto the TFT array. One electrode of CTEST is connected to the source of TDV, and the other is connected to the scan line, as schematically shown in Fig. 7-1 (a). The function of pixel as well as the characteristics of TDV can be examined by utilizing this CTEST. A layout example of 2-T pixel electrode circuit with proposed COG structure is drawn in Fig. 7-1(b) where shows that an additional CTEST is drawn below the scan line electrode, consequently, no much additional area is needed to form the CTEST.
7.2.2 Detection circuit & operation of functional testing
The pixel, functioning like a sample and hold circuit, is driven to sample analog data and store them until the following sampling period. Also, by connecting the pixel to a detection circuit, the stored data can be retrieved. The principle that underlies the proposed charge sensing scheme is to write and read the charges of the pixel. An operational amplifier, configured as an integrator, is used as a detection circuit to receive the charges from the pixel. The detection circuit constructed by an integrator with virtual ground configuration can maintain the voltage of 0V at the input of detection circuit while the testing is performed. TSW and TDC in the pixel circuit must be examined individually because of the functional differences. For testing either TSW
or TDV, (1) writing, (2) holding and (3) reading periods must be achieved sequentially.
The details of testing approach for TSW and TDV is illustrated in following sections.
7.2.3 Functional testing for T
SWThe functions of TSW and CST in AM-OLED pixel circuit are similar to that in AM-LCD pixel. Since the charge in CST is directly controlled by data line signal, the detection circuit, in which the switch SW1 is used to initialize the output voltage, is connected to the data line of the pixel through a switch SW2. The simplified equivalent circuit and corresponding waveforms for testing TSW are shown in Figs.
7-2(a) and (b), respectively. In the T
SW testing, a constant voltage is supplied to VCOMelectrode as a reference and Vdd electrode is connected to ground. The operation of pixel circuit is only controlled by data line and scan line.
VData
ΔV
(1) (2) (3)
Running time VScan n
Vout
(a) (b)
Fig. 7-2. (a) System diagram with charge detection circuit and (b) the timing diagrams for T
SWtesting. ( (1) Writing, (2) holding, and (3) reading period )
When in writing period (1), the signal at scan line n is HIGH to turn on the TSW
and the SW2 connects the data line to an external power supply which can provide
testing charge QST =VData⋅(CST ||CGS−SW) to storage capacitor CST as a positive voltage. In the meanwhile, the SW1 connects the output and negative input of amplifier together to initial the output voltage of 0V. In the following holding period (2), the signal at scan line n becomes LOW to turn off the TSW. When TSW is OFF, the resistance of which must be large enough to prevent significant leakage from CST to data line. Therefore the charge QST is maintained in CST for the entire holding period.
Now considering the reading period (3), the SW2 switches the data line from power supply to the detection circuit and the SW1 is open to actuate the detection circuit. After that, the scan line signal turns TSW on once again and the charge in CST is released and redistributed into the detection circuit due to the zero voltage at data line.
While collecting the charge QST across the feedback capacitor CINT, the detection circuit is still holding the data line at 0V simultaneously, therefore no charge is lost.
After the charge is collected, the output voltage of the integrator is decreased by an offset voltage ∆VOut, defined as ∆VOut =−QST /CINT, is proportional to the amount of charge QST stored in CST. Therefore, holding more charges in CST makes the output more negative after detection because of the negatively configured integrator.
7.2.4 Functional testing for T
DVTDV works as a voltage-to-current converter to provide a stable current signal to OLED during whole frame period. Variations of TDV characteristics directly influence output current and result in brightness non-uniformity and inferior image quality.
Therefore the functional testing for TDV is more important than TSW. Since TDV is modulated by the voltage signal at storage node and the testing charge is from Vdd electrode, the detection circuit should be connected to Vdd instead of data line and thereby collect the charge in CTEST. The simplified equivalent circuit and
corresponding waveforms for testing TDV are shown in Fig. 7-3(a) and (b), respectively.
(a) (b)
Fig. 7-3. (a) System diagram with charge detection circuit and (b) the timing diagrams for T
DVtesting. ( (1) Writing, (2) holding, and (3) reading period )
During writing period (I), the switch SW1 connects the pixel electrode circuit to VTEST and SW2 connects VOUT to the negative input of operational amplifier to initial the detection circuit. At this time, the output voltage VOUT is 0V. In the meanwhile, the data line signal VDATA turns TDV on and a testing voltage VTEST is stored in CTEST
through TDV. According to the charge conservation principle, the charge stored at nodes A and VDD in writing period can be derived as following equations in which CGS and CGD denote the gate-to-drain and gate-to-source parasitic capacitance.
SCAN the accumulative electron in the channel of TDV. Therefore the charge held in TDV can be expressed as
) voltage of TDV, respectively.
When pixel electrode circuit changes to the holding period (II), VDATA is low and turns off TDV so that the VTEST is kept in the CTEST. At this time, SW1 switches the pixel electrode circuit to the detection circuit, nevertheless, SW2 still keeps VOUT and negative input of OP-AMP connected together. Because the detection circuit maintains the initial state, the charge QVDD-I flowing into the detection circuit is removed without disturbing VOUT. It should be taken into account that the charge injection mechanism of TDV will affect the stored charge in CTEST when VDATA
changes from high to low. Since the gate voltage is removed so that the channel charge QDV-I is no longer maintained and will redistribute into the drain and source of TDV. It is assumed that one half of QDV-I flows into the drain and the other half flows into the source in order to derive equations simply. Moreover, an additional charge induced by CST at node A and the other half of QDV-I also flow into detection circuit and is cancelled out. Hence, the charge at VDD, A and TDV in holding period (II) becomes:
The data line signal VDATA turns on TDV once again as the pixel electrode circuit works in reading period (III) and SW2 is open to enable the charge detection circuit as well. When VDATA changes from low to high, an additional amount of charge will be induced by CST, Cgs2 and Cgd2 at nodes VDD and A, and will result in the non-zero
voltage at VDD and A. However the detection circuit constructed by virtual ground configuration of the integrator maintains the voltage of 0V at the VDD and A while the detection circuit is connected to the pixel electrode circuit. Hence the charge at nodes A and VDD are collected by detection circuit until the voltage at both nodes becomes 0V. After pixel electrode circuit returns to steady state, the charge at VDD and A can be expressed as:
Furthermore, the channel charge of TDV is induced again by VDATA, as shown in following equation.
Since SW2 switches to open before the reading period, the detection circuit starts to collect the charge and an amount of which can be derived from the difference of total amount of charge between holding and reading period.
) The output voltage of the integrator is decreased of an offset ∆VOUT, as plotted in
Fig. 7-3 after the charge is collected in reading period. ∆V
OUT, defined as ∆VOUT = -QTotal/CINT, where CINT is the capacitance used in the integrator, is related to the amount of charge stored in CTEST. The integrator is negatively configured, so holding more charge in CTEST makes the output more negative after detection.7.3 Simulation results and discussion 7.3.1 Simulation environment
The simulation was performed by Synopsis H-SPICE simulation tool. The characteristics of ID-VG of TFT used for simulation are demonstrated in Fig. 7-4(a) in which the subthreshold slope (S.S.) for each curve is listed. In order to imitate the RC loading of the practical panel, the parasitic resistance and capacitance of conducting wires are taken into account, as shown in Fig. 7-4(b). Other parameters, such as geometric size of TFT, mobility, threshold voltage, storage and test capacitance, and driving voltage, are also listed in Table 7-1. In simulation, the ideal operational amplifier with an open loop gain of 106 is used to design the charge detection circuit.
The resistance RINT and capacitance CINT of charge detection circuit are designed with a value of 100kΩ and 10pF, respectively.
-5 0 5 10 15
Fig. 7-4. (a) I
D-V
Gcharacteristics of TFTs and (b) the equivalent schematic diagram used for SPICE simulation.
Table 7-1. Parameters used for simulation
Pixel size (um2) 66 x 198
W/L of TSW(µm) 7/5
W/L of TDV(µm) 10/5 ~ 50/5
Vth of N-TFT (V) 1.0
µ of N-TFT (cm2/s-V) 77.1
CST (fF) 100 ~ 1000
CTEST (fF) 10 ~ 90
RINT (Ω), CINT (pF) 100k, 10p
Rpara(Ω), Cpara(F) of data line 623, 1.74p Rpara(Ω), Cpara(F) of scan line 7000, 1.4p Rpara(Ω), Cpara(F) of Vdd line 360, 3p
VScan (V) 0, 15
VData (V) 3 ~ 13
Vdd (V) 0 ~ 15
VCOM(V) 15
7.3.2 Results of T
SWand T
DVtesting
The increases of VDATA and CST result in the corresponding increase of offset voltage when testing the TSW, as shown in Fig. 7-5. As the above discussion, the offset is proportional to QST/CINT, consequently, the more charges can be stored in CST, the larger offset voltage is measured. The geometric size of TDV also affects the offset voltage while testing TSW, as shown in the inset of Fig. 7-5. The VDATA written into CST can induce the channel of TDV and result in an additional parasitic capacitance CDV. The stored charges can be written as:
DATA DV
SW GD ST
ST C C C V
Q '=( || − + )⋅ Eq. 7-11
Therefore, the larger the geometric size of TDV is, the larger offset voltage can be detected. As a result of the ground shorted to the VDD electrode, various size of CTEST
Therefore, the larger the geometric size of TDV is, the larger offset voltage can be detected. As a result of the ground shorted to the VDD electrode, various size of CTEST