Functional testing for T DV …

TDV works as a voltage-to-current converter to provide a stable current signal to OLED during whole frame period. Variations of TDV characteristics directly influence output current and result in brightness non-uniformity and inferior image quality.

Therefore the functional testing for TDV is more important than TSW. Since TDV is modulated by the voltage signal at storage node and the testing charge is from Vdd electrode, the detection circuit should be connected to Vdd instead of data line and thereby collect the charge in CTEST. The simplified equivalent circuit and

corresponding waveforms for testing TDV are shown in Fig. 7-3(a) and (b), respectively.

(a) (b)

Fig. 7-3. (a) System diagram with charge detection circuit and (b) the timing diagrams for T

DV

testing. ( (1) Writing, (2) holding, and (3) reading period )

During writing period (I), the switch SW1 connects the pixel electrode circuit to VTEST and SW2 connects VOUT to the negative input of operational amplifier to initial the detection circuit. At this time, the output voltage VOUT is 0V. In the meanwhile, the data line signal VDATA turns TDV on and a testing voltage VTEST is stored in CTEST

through TDV. According to the charge conservation principle, the charge stored at nodes A and VDD in writing period can be derived as following equations in which CGS and CGD denote the gate-to-drain and gate-to-source parasitic capacitance.

SCAN the accumulative electron in the channel of TDV. Therefore the charge held in TDV can be expressed as

) voltage of TDV, respectively.

When pixel electrode circuit changes to the holding period (II), VDATA is low and turns off TDV so that the VTEST is kept in the CTEST. At this time, SW1 switches the pixel electrode circuit to the detection circuit, nevertheless, SW2 still keeps VOUT and negative input of OP-AMP connected together. Because the detection circuit maintains the initial state, the charge QVDD-I flowing into the detection circuit is removed without disturbing VOUT. It should be taken into account that the charge injection mechanism of TDV will affect the stored charge in CTEST when VDATA

changes from high to low. Since the gate voltage is removed so that the channel charge QDV-I is no longer maintained and will redistribute into the drain and source of TDV. It is assumed that one half of QDV-I flows into the drain and the other half flows into the source in order to derive equations simply. Moreover, an additional charge induced by CST at node A and the other half of QDV-I also flow into detection circuit and is cancelled out. Hence, the charge at VDD, A and TDV in holding period (II) becomes:

The data line signal VDATA turns on TDV once again as the pixel electrode circuit works in reading period (III) and SW2 is open to enable the charge detection circuit as well. When VDATA changes from low to high, an additional amount of charge will be induced by CST, Cgs2 and Cgd2 at nodes VDD and A, and will result in the non-zero

voltage at VDD and A. However the detection circuit constructed by virtual ground configuration of the integrator maintains the voltage of 0V at the VDD and A while the detection circuit is connected to the pixel electrode circuit. Hence the charge at nodes A and VDD are collected by detection circuit until the voltage at both nodes becomes 0V. After pixel electrode circuit returns to steady state, the charge at VDD and A can be expressed as:

Furthermore, the channel charge of TDV is induced again by VDATA, as shown in following equation.

Since SW2 switches to open before the reading period, the detection circuit starts to collect the charge and an amount of which can be derived from the difference of total amount of charge between holding and reading period.

) The output voltage of the integrator is decreased of an offset ∆VOUT, as plotted in

Fig. 7-3 after the charge is collected in reading period. ∆V

OUT, defined as ∆VOUT = -QTotal/CINT, where CINT is the capacitance used in the integrator, is related to the amount of charge stored in CTEST. The integrator is negatively configured, so holding more charge in CTEST makes the output more negative after detection.

7.3 Simulation results and discussion 7.3.1 Simulation environment

The simulation was performed by Synopsis H-SPICE simulation tool. The characteristics of ID-VG of TFT used for simulation are demonstrated in Fig. 7-4(a) in which the subthreshold slope (S.S.) for each curve is listed. In order to imitate the RC loading of the practical panel, the parasitic resistance and capacitance of conducting wires are taken into account, as shown in Fig. 7-4(b). Other parameters, such as geometric size of TFT, mobility, threshold voltage, storage and test capacitance, and driving voltage, are also listed in Table 7-1. In simulation, the ideal operational amplifier with an open loop gain of 10⁶ is used to design the charge detection circuit.

The resistance RINT and capacitance CINT of charge detection circuit are designed with a value of 100kΩ and 10pF, respectively.

-5 0 5 10 15

Fig. 7-4. (a) I

D

-V

G

characteristics of TFTs and (b) the equivalent schematic diagram used for SPICE simulation.

Table 7-1. Parameters used for simulation

Pixel size (um²) 66 x 198

W/L of TSW(µm) 7/5

W/L of TDV(µm) 10/5 ~ 50/5

Vth of N-TFT (V) 1.0

µ of N-TFT (cm²/s-V) 77.1

CST (fF) 100 ~ 1000

CTEST (fF) 10 ~ 90

RINT (Ω), CINT (pF) 100k, 10p

Rpara(Ω), Cpara(F) of data line 623, 1.74p Rpara(Ω), Cpara(F) of scan line 7000, 1.4p Rpara(Ω), Cpara(F) of Vdd line 360, 3p

VScan (V) 0, 15

VData (V) 3 ~ 13

Vdd (V) 0 ~ 15

VCOM(V) 15

7.3.2 Results of T

SW

and T

DV

testing

The increases of VDATA and CST result in the corresponding increase of offset voltage when testing the TSW, as shown in Fig. 7-5. As the above discussion, the offset is proportional to QST/CINT, consequently, the more charges can be stored in CST, the larger offset voltage is measured. The geometric size of TDV also affects the offset voltage while testing TSW, as shown in the inset of Fig. 7-5. The VDATA written into CST can induce the channel of TDV and result in an additional parasitic capacitance CDV. The stored charges can be written as:

DATA DV

SW GD ST

ST C C C V

Q '=( || ₋ + )⋅ Eq. 7-11

Therefore, the larger the geometric size of TDV is, the larger offset voltage can be detected. As a result of the ground shorted to the VDD electrode, various size of CTEST

does not affect the offset voltage in TSW testing because no charge is stored in CTEST.

2 4 6 8 10 12 14

Fig. 7-5. Offset voltage versus data voltage at different storage capacitance C

ST

in T

SW

testing. The inset shows the effect of width of T

DV

(W-T

DV

) in T

SW

testing.

The function of TDV can also be inspected by writing and reading the charges in CTEST with proposed testing scheme. The testing charges are written into CTEST

through the VDD electrode, and the ON-OFF state of TDV is controlled directly by a digital data signal of 13v and 0v. The simulation result plotted in Fig. 7- 6 demonstrates that the additional CTEST actually improves the testability of TDV. On the other hand, the offset voltage is less than that of TSW testing because of the small CTEST which can minimize the delay of scan line signal. In contrast, the offset voltage can not be detected in the pixel without CTEST even though the TDV is functioning perfectly in simulation.

The offset voltage in TDV testing is also related to the geometric size of TDV. The larger size of TDV leads to larger parasitic capacitance CDV and keeps an additional amount of charge within it. At CTEST of 30fF, increase of the size of TDV results in the shift of the simulated curve, as shown in the inset of Fig. 7- 6, consequently implying that the digital VDATA in TDV testing induces the constant CDV as the width of TDV is

fixed regardless of the VDD voltage.

Fig. 7- 6. Offset voltage versus V

DD

voltage at different C

TEST

in T

DV

testing. The inset shows the effect of width of T

DV

varied from 10 to 50um in T

DV

testing.

7.3.3 Threshold voltage, leakage current, and subthreshold slope

Data collected by the charge detection circuit can be used to evaluate the characteristics such as threshold voltage and leakage current of the pixel with specific driving conditions. Leakage current induced by process variations causes the charge in CST leak out even though the TSW is turn-off, ultimately, affecting the gray level of pixel. In the above discussion, the write-in data are hold in storage capacitance for a certain period between the writing and reading process. The write-in data voltage probably decreases during the holding period due to the leakage current of TSW. The degree of leakage current of TSW can be monitored by the offset voltage with various holding period Thold, as expressed in Eq. 7-12.

INT

The simulation is conditioned by connecting an ideal current source of 10p to 1nA

between source/drain nodes of TSW to simulate the leakage current. The simulation result reveals that the longer holding time is performed, the smaller offset voltage can be detected, as shown in Fig. 7-7.

10^-7 10^-6 10^-5 10^-4 10^-3 10^-2 10^-1

Fig. 7-7. Offset voltage versus holding time at leakage current varied from 10

^-11

to 10

^-9

A in T

SW

testing. The inset demonstrates the transfer curve of TFT for V

th

evaluation.

For the panel operation, TDV is used to convert the voltage into current hence the variation of the threshold voltage of TDV must be sufficiently small to ensure the uniform brightness. When testing TDV, the transfer characteristic of TDV, plotted in the inset of Fig. 7-7, can be derived by scanning various voltages to both the data line and the VDD electrode and measuring the offset voltage in turn. The simulated offset voltage curve is similar to the transfer curve of an ideal MOSFET device. The linear region of the simulated offset voltage curve can be distinguished from the saturation region. Therefore, the threshold voltage can be simply derived from the intersection of two asymptotes. The threshold voltage obtained by this functional testing scheme is an approximated value due to numerous parasitic resistance and capacitance, yet, can

be used to monitor the threshold variation in large.

2 4 6 8 10 12 14

0.02 0.03 0.04 0.05 0.06

0.04 0.08 0.12 0.16 0.20

TSW testing TDV testing

Offs et Vo lt a g e ( V )

Offset Voltage (V)

Input Voltage (V)

S.S.=0.21 S.S.=0.61 S.S.=0.21 S.S.=0.61 C_ST=100fF, C_TEST=30fF

Fig. 7-8. Offset voltage versus input voltage at different subthreshold swing (S.S.) from 0.21 to 0.61 V/dec in T

DV

and T

SW

testing.

An important parameter, subthreshold slope (S.S.), indicates how effectively the TFT can be turned off when gate to source voltage is decreased below threshold voltage. In TFT process, the increase of grain boundary trap densities or the random grain size and orientation makes the subthreshold slope increase. Usually, the variation of subthreshold slope can be used to monitor the uniformity of characteristics of TFT. In the proposed pixel circuit, a significant influence of subthreshold slope can be found while performing the pixel testing. A decrease of offset voltage of about 5mV in TDV testing is shown in Fig. 7-8 when subthreshold slope varies from 0.21 to 0.61 V/dec. The reason is that large subthreshold slope attributed to the increase of grain boundary trap densities results in the weak inversion in channel region of TFT, thus the less charge can be retrieved. However, in TSW

testing, the decrease of offset voltage is not evident because the channel charge

difference is caused by the negligible variation of subthreshold slope. On the other hand, in TDV testing, the small CTEST is beneficial to observe the effect of subthreshold slope as well as the uniformity of characteristics of TDV.

7.4 Issues of time constant and aperture ratio

The additional CTEST directly increases the resistance-capacitance (RC) time constant TRC of the scan line and decreases the aperture ratio of the pixel, even though the CTEST can enhance the testability of TDV. Although CTEST is geometrically formed below the scan line, as shown in Fig. 7-1(b), the contact hole that connects CTEST to ITO occupies an extra area of 200 um², consequently, slightly decreases the aperture ratio from 43.1% to 41.4%.

In order to evaluate the TRC of the scan line, the parasitic resistance and capacitance of a scan line per pixel (Rscan, Cscan) are set to be 13.2Ω and 2.6fF, respectively for the pixel without CTEST. In the proposed pixel circuit, Cscan increases from 2.6 to 72.6fF as CTEST of 10, 30, 50, and 70fF are used. Besides, the frame rate of 30Hz is used to calculate the turn-on period of the scan line (Tscan-on) for the comparison between TRC and Tscan-on.

TRC is much smaller than Tscan-on for the conventional panel without CTEST. Even though in high resolution such as 1280xRGBx1024 (SXGA), TRC is merely 1.55% of Tscan-on, as shown in Fig. 7-9. However, TRC is increased when the proposed pixel is implemented into a panel. For example, in the resolution such as 480xRGBx360, CTEST of 70fF increases TRC to 1.98us, 28 times larger than that of conventional panel.

However, TRC to Tscan-on ratio of 2.15% is still smaller than 5% which is a generally acknowledged limitation in display panel design. In other words, from small to moderate resolution, CTEST can be useful for testability enhancement without seriously

impacting on the programming time of the signal. Unfortunately, if the dot resolution is from VGA to SXGA, TRC is dramatically increased by CTEST of 70fF from 3.53 to 14.13us, almost 5.1 to 43.4% of Tscan-on. The long TRC results in slow switching behavior of TSW as well as inaccurate data write-in. In order to reduce TRC, an intuitive approach is to use a small CTEST in the pixel circuit, however, the accuracy of charge detection is limited.

0.0 2.0x10⁵ 4.0x10⁵ 6.0x10⁵ 8.0x10⁵ 1.0x10⁶ 1.2x10⁶ 1.4x10⁶

Fig. 7-9. T

scan-on

and T

RC

/T

scan-on

versus dot resolution of display panel.

Using high conductivity material such as aluminum to fabricate the scan line instead of molybdenum is another approach to reduce TRC. The sheet resistance of aluminum is 70m Ω/square, merely 7% of that of molybdenum. In contrast with molybdenum, the scan line made by aluminum can achieve the lower Rscan of 0.924Ω in proposed dimension. TRC to Tscan-on ratio as a function of dot resolution with aluminum scan line is also plotted in Fig. 7-9. Evidentially, the scan line of aluminum dramatically reduces the TRC to Tscan-on ratio to 3% even in SXGA resolution.

Therefore, CTEST of up to 70fF can still be utilized to ensure the accuracy of TFT array

inspection.

7.5 Summary

An effective charge sensing scheme and corresponding pixel circuit were designed to enhance the testability of TFT array of AM-OLED. By using an additional CTEST, the function of all devices such as TFT and storage capacitance can be examined with electrical signal before the OLED process is performed. The proposed functional testing scheme can be performed without any mechanical motion during testing, and an in-situ measurement can be taken in real time with high stability. Two side effects: an increase of RC time constant can be restrained by using aluminum as bus line material; while the reduction of aperture ratio is within acceptable for operation. The simulated and calculated results presented herein including leakage, time constant, and threshold voltage, are useful in identifying the causes of array defects on the panels in situ. Furthermore, the array testing can be integrated into the in-line process as a batch job.

References

[1] R. L. Wisnieff, L. Jenkins, R. J. Polastre and R. R. Troutman, “In-process testing of thin-film transistor arrays,” in Symp. Dig. 1990 SID, 1990, p. 190.

[2] F. J. Henley, and G. Addiego, “In-line functional inspection and repair methodology during LCD panel fabrication,” in Symp. Dig. 1991 SID, 1991, p. 686.

[3] F. J. Henley, and H. J. Choi, “Test head design using electro-optic receivers and GaAs pin electronics for a gigahertz production test system,” in Proc. IEEE Int. Test Conf., 1988, p. 700.

[4] M. Brunner, R. Schmid, R. Schmitt, and D. Winkler, “In-process flat-panel-display testing with electron beams,” in Symp. Dig. 1994 SID, 1994, p. 755.

[5] H. P. Hall, and P. R. Pilotte, “Testing TFT-LCD substrates with a transfer admittance method,” in Symp. Dig. 1991 SID, 1991, p. 682.

[6] L. C. Jenkins, R. J. Polastr, R. R. Troutman, and R. L. Winsnieff, “Functional testing of TFT/LCD arrays,” in IBM J. Res. Develop., vol. 36, no. 1, p. 59, Jan. 1992.

Chapter 8

Conclusion

Active-matrix organic light emitting displays with integrated driver circuits using polysilicon thin-film transistor technology have demonstrated the capability for being the next generation display applications. In conjunction with the usage of thermal evaporation or ink-jet printing technologies to fabricate OLED pixel elements, it is possible to achieve thin, compact, lightweight, wide-viewing angle, fast response, flexible and yet low cost full color AM-OLED displays.

Unlike AM-LCDs, the organic EL elements for AM-OLEDs are current driven devices. Since the nature of the fabrication process of poly-Si TFT, variations of the TFT electrical characteristics, such as threshold voltage and mobility, over the entire substrate area is unavoidable. Besides, the native parasitic resistance of electrodes can result in a voltage drop as the OLED driving current passing through the addressing electrodes. Consequently, these characteristic and voltage variations cause a large steady state output current error and non-uniform pixel luminance. In this dissertation, we have successfully developed several key driving and testing schemes to improve the display image quality and the functionality evaluations. The characteristics of pixels and driving circuits were taken into consideration for optimizing the display performance, such as the charge injection, parasitic RC time delay and device degradation, etc. Additionally, from this thesis research, the fabrication processes of poly-Si TFT and OLED were utilized for realizing the AM-OLED panel with proposed electronic circuits and components. Most of all, these driving schemes and components greatly improve the display performance of AM-OLED displays and manufacturing yield control, thus, offering more appealing and competitive

AM-OLED’s.

8.1 AC driving scheme for voltage driven AM-OLED

A two-transistor pixel electrode circuit driven by voltage signal for AM-OLED’s is more attractive because of its high aperture ratio and compatibility with AM-LCD driver technology. Even though the parasitic resistance of addressing wire can lead to a voltage drop as the OLED current passing through it, our proposed voltage type AC driving scheme shows a significant improvement in the display luminance. By using an AC voltage at OLED cathode, the voltage drop at the addressing wire can be easily compensated without modifying the pixel circuit structure.

The normalized luminance of all measured regions of AM-OLED panel was well above 91.6%, for a various duty cycle of the flashing period from 20% to 80% shown experimentally. In contrast, the AM-OLED panel with conventional DC driving scheme shows lower luminance uniformity, due to luminance decays from surrounding to the central area. The lowest luminance measured at the central display region was of only 74.54% of the highest luminance at the surrounding area. Although a higher driving current is needed in the AC driving scheme, the treatment of reversed bias voltage can accelerate the recovery from degradation and lead to an improvement in the J-V characteristics and device lifetime of the OLED. In other words, the higher driving current may degrade OLED performance rapidly, however, the AC driving scheme with proper reversed bias voltage, can alleviate the OLED material degradation.

8.2 Current driven AM-OLED with fully integrated driver

In order to achieve multiple grayscales, circuit designers and process engineers

must address the issue of non-uniform pixel brightness over the display area caused by the non-uniform spatial distribution of threshold voltage in the driving transistor of pixel circuit. In this dissertation, we focus on certain methods and techniques used in designing poly-Si TFT pixel driver circuits to minimize the effect of threshold voltage variation on the display luminance. The key concern in design of current driven pixel circuit is to ensure that the OLED is driven with a specified input current not only during the OLED is addressed but also during the rest of the frame period as well when the OLED is not being addressed. Here we have designed, fabricated, and analyzed a current-driven four-transistor pixel electrode circuit based on poly-Si TFT technology for AM-OLED’s. The pixel circuit proposed here is able to reduce the effect of spatial variation of TFT threshold voltage in comparison with traditional voltage driven pixel circuits. Experimental results indicated that continuous pixel electrode excitation with constant current signal can be achieved during more than 12

must address the issue of non-uniform pixel brightness over the display area caused by the non-uniform spatial distribution of threshold voltage in the driving transistor of pixel circuit. In this dissertation, we focus on certain methods and techniques used in designing poly-Si TFT pixel driver circuits to minimize the effect of threshold voltage variation on the display luminance. The key concern in design of current driven pixel circuit is to ensure that the OLED is driven with a specified input current not only during the OLED is addressed but also during the rest of the frame period as well when the OLED is not being addressed. Here we have designed, fabricated, and analyzed a current-driven four-transistor pixel electrode circuit based on poly-Si TFT technology for AM-OLED’s. The pixel circuit proposed here is able to reduce the effect of spatial variation of TFT threshold voltage in comparison with traditional voltage driven pixel circuits. Experimental results indicated that continuous pixel electrode excitation with constant current signal can be achieved during more than 12

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