The Influence of Mismatch
Chapter 7 Divider
7.1 Architectural Approach
7.1.3 Divide-by-2/3 Architecture
The divide-by-2/3 structures form the basic building blocks of the multi-modulus divider used in the prototype. These structures may be implemented by augmenting a divide-by-2 circuit with gating or multiplexing logic [53]. This section will outline the advantages of the multiplexing method over the gating method in achieving high speed performance with low power consumption.
2/3
IN 2/3 A B OUT
2/3
CON0 CON1 CON2
IN A B OUT
8 + CON0*20 + CON1*21 + CON2*22
Figure 7.2: An 8 modulus divider.
Figure 7.3 illustrates an efficient divide-by-2 structure known as the Johnson counter [52]. The structure consists of two level-triggered latches that are cascaded within a negative feedback loop. Maximum operating speed of this structure is de-termined by the propagation delay of the input of each latch to its respective output when the latch is made transparent by the clock. Specifically, the input period, TIN, must satisfy the relation:
TIN
2 − Ts> delay1 = delay2, where Ts is defined as the setup time of each latch.
To create a divide-by-2/3 circuit, a common approach is to augment the Johnson counter to swallow cycles by gating the feedback signal into one of its latches. Fig-ure 7.4 provides an example of the gating approach where the setting of CON∗ equal to zero leads to the swallowing of a pulse.
A generalized view of this approach is illustrated in Figure 7.5, which lumps the combinational and memory logic required for gating into the Gating Logic block.
The function of this block is to extend the assertion of signal A by one input cycle whenever the control signal is asserted. Since A is propagated to the output, this leads to the swallowing of an input cycle.
A few points are in order
1. Proper timing of signal A is typically achieved with latches that are clocked syn-chronously with the Johnson counter latches, leading to a significant increase
7.1. ARCHITECTURAL APPROACH 99
LATCH 1
D Q
clk Q
IN
OUT LATCH 2
D Q
clk Q IN
OUT
IN OUT
TIN
delay2 delay1
Register
Figure 7.3: A divide-by-2 circuit implemented as a Johnson counter.
D Q
Q
D Q
Q
Register A Register B
CON*
IN
OUT
Figure 7.4: Example of divide-by-2/3 implementation using gating logic.
in the number of components operating at the high input frequency over the divide-by-2 structure. This leads to high load capacitance on the high speed input, which requires a larger buffer from the VCO, thus increasing power dis-sipation.
2. The maximum operating speed of the divide-by-2/3 structure is less than the basic divide-by-2 topology since the gating logic adds to the propagation delay from the output of latch 2 to the input of latch 1. Referring to Figure 7.5, the input period must satisfy the relation:
TIN
2 − Ts > delay2+ delay3, which is longer than that of the divide-by-2 circuit.
A OUT
LATCH 1
D Q
clk Q
IN
OUT LATCH 2
D Q
clk Q
IN
OUT
IN GATING
LOGIC CON
A
TIN
CON
delay1 delay2
delay3
Figure 7.5: A divide-by-2/3 core circuit implemented by gating the feedback in a Johnson counter.
An alternative method of realizing the divide-by-2/3 structure is to multiplex the output of the divide-by-2 circuit. Figure 7.6 illustrates this approach. In this case, the control signal selects either ΦA or ΦB from the Johnson counter to produce the output signal. Cycles can then be swallowed by properly shifting from one phase to the other, i.e. ΦA to ΦB and vice-versa.
This technique has the following advantages over the gated approach:
1. The operating speed of the structure can be set as high as the divide-by-2 circuit allows since it is not impeded by extra delays
2. The MUX circuitry operates at half the input frequency
3. The capacitive load presented to the input is the same as that of the divide-by-2 structure.
It should be noted that the multiplexed structure requires care in its design to assure that the two phases of its differential input, ΦAand ΦB, are close to 180 degrees apart.
Otherwise, jitter will occur in the transition times of OUT as it switches between ΦA and ΦB. (The time between transitions of OUT will not be a multiple of the input period, TIN, if ΦA and ΦB are not 180 degrees apart.)
The operating frequency of the MUX circuitry can be further reduced by applying the phase shifting principle to a divide-by-2 circuit with a 4 phase output. Figure 7.7 illustrates that this type of divider can be cascaded with a standard divide-by-2 structure to produce a divide-by-4/5 circuit. Explaining, one of four phases from the 4 phase divider is directed to the output at any given time, and input cycles are
7.1. ARCHITECTURAL APPROACH 101
LATCH
D Q
clk Q
IN
OUT LATCH
D Q
clk Q IN
OUT
IN
LOGICMUX
CON
CON
OUT OUT
OUT
FA
FB
FA FB
FB FA
Figure 7.6: A divide-by-2/3 core circuit implemented by multiplexing the divided output of a Johnson counter.
swallowed by shifting the output from one phase to another. The figure illustrates a shift from Φ1 to Φ2 to swallow one input cycle.
OUT F
IN IN/2
F F F! F"
OUT
OUT F
IN IN OUT
OUT
CON 4 PHASE
DIVIDE-BY-2 . . .! ."
IN IN DIVIDE-BY-2
IN
IN OUT
OUT
LOGICMUX . . .! ."
OUT OUT IN/2
IN/2
4 cycles 5 cycles
Figure 7.7: A by-4/5 structure implemented by multiplexing a 4 phase divide-by-2 circuit.
The concept illustrated in Figure 7.7 is very useful for implementation of the first divider stage within a dual or multi-modulus divider. Since the operating frequency is reduced at later stages, the first stage presents the strongest challenge in terms of realizing the required speed while maintaining low power consumption. However, to use the divide-by-4/5 stage within a multi-modulus divider, consideration must be given to the fact that its nominal division value is twice that of a divide-by-2/3 structure. A divide structure cascaded after the divide-by-4/5 circuit therefore has half the cycle swallowing resolution than needed to realize a contiguous range of divide values.
Figure 7.8 illustrates the divide-by-4/5/6/7 topology used in the prototype. By following the divide-by-4/5 circuit with at least two divide-by-2/3 sections, the prob-lem of decreased cycle resolution is solved by allowing the divide-by-4/5 circuit to swallow more than one input cycle during one cycle of OUT . Division by 4/5/6/7 is accomplished by designing the divide-by-4/5 circuit such that it swallows 0 to 3 input cycles during each cycle of OUT ; the figure shows the case for which the first stage accomplishes a divide-by-7 operation by swallowing 3 input cycles. The overall divide range of the topology in Figure 7.8 is 16 through 31, which is the same as would be achieved by cascading four divide-by-2/3 sections.
IN
2/3
4/5 2/3
IN A B OUT
A B OUT
AT LEAST 3 CYCLES NEEDED AT NODE A
4/5/6/7
Figure 7.8: Timing diagram of a divide-by-4/5 structure performing a divide-by-7 operation by swallowing 3 input cycles per OUT period.