Chapter 1 Introduction
1.8 Implementation Highlights
Trans. Fil. 1-bit S-D PLL
Data Fout
Comp. Fil.
Compensated Transmit Filter
Figure 1.15: The effect of mismatch.
range of divide values.
Digital S-D Modulator
PFD Loop
Filter N/N+1
Ref Out
1-bit
Data Mod
Mod Data Compensated
Transmit Filter
Figure 1.16: High data rate costs dynamic range.
1.8 Implementation Highlights
To show proof of concept of the proposed compensation method, the system depicted in Figure 1.17 was built using a custom, CMOS fractional-N synthesizer that contains several key circuits. Included are an on-chip, continuous-time filter that requires no tuning or external components, a digital MASH Σ-∆ modulator with 6 output bits that achieves low power operation through pipelining, and a 64 modulus divider that
supports any divide value between 32 and 63.5 in half cycle increments. The inclusion of the external divide-by-2 prescaler allows the CMOS divider input to operate at half the VCO frequency, and changes the range of divide values to all integers between 64 and 127.
1.8 - 1.9 GHz
0.6 m CMOS IC
Digital S-D Modulator
PFD Out
20 MHz
Data
64 Modulus Divider
LoopFilter
2
digital data stream Carrier
frequency
Figure 1.17: Overall System.
Table 1.2 lists the specifications of the prototype frequency synthesizer IC. The power of the proposed system is roughly half that of a DECT system described by Heinen in [15], which is believed to be representative of the lowest power transmitter architecture available at the present time. It should be noted that the spurious noise was measured without an output bandpass filter on the transmitter. The inclusion of this filter should lower the spurious response to less than -80 dBc.
Power consumption 27 mW Maximum Data Rate 2.85 Mbit/s
Carrier Frequency 1.81 GHz to 1.89 GHz Modulation GFSK
Spurious Noise <−60 dBc
Phase Noise <−131 dBc/Hz at 5 MHz offset Table 1.2
Modulator specifications.
The modulation method chosen for the prototype is Gaussian Frequency Shift Key-ing (GFSK). This method is similar to Gaussian Minimum Shift KeyKey-ing (GMSK) [49], the difference being that GFSK allows a tolerance on the modulation index, h. (By definition, h is the ratio of the peak-to-peak frequency deviation of the transmitter output to its data rate.) This tolerance is necessary when using the compensation method since mismatch between the compensation filter and PLL dynamics changes
1.8. IMPLEMENTATION HIGHLIGHTS 37
the frequency deviation of the transmitter output. (An explanation of this phe-nomenon is provided in Chapter 6.) The value of h is 0.5 in the case of GMSK, which causes the phase of the transmitter output to increment or decrement by π/2 radians during each data symbol period. In the case of GFSK as used in DECT, h = 0.5± 0.05.
Although the proposed compensation method is applicable to modulation meth-ods other than GFSK, we will restrict our analysis to this case since it provides a benchmark for our results. Specifically, we will strive to meet the performance stan-dards of DECT; our primary goal will be the achievement of a data rate in excess of 1 Mbit/s with a noise spectral density that is less than -131 dBc/Hz at 5 MHz offset.
In the implementation, the 64 modulus divider and 6 output bit Σ-∆ modulator provide a dynamic range for the compensated modulation data that is wide enough to support data rates in excess of 2.5 Mbit/s. The on-chip loop filter allows an accurate PLL transfer function to be achieved by tuning just one PLL parameter — the open loop gain. A brief overview of each of these components will now be presented.
1.8.1 Divider
To achieve a low power design, it is desirable to use an asynchronous divider struc-ture to minimize the amount of circuitry operating at high frequencies. As such, a multi-modulus divider structure was designed that consists of cascaded divide-by-2/3 sections [50]; this architecture is an extension of the common dual-modulus topology [45, 51–53]. Shown in Figure 1.18 for an 8-modulus example, this divider structure allows a wide range of divide values to be achieved by allowing a variable number of input cycles to be ‘swallowed’ per output cycle. Each divide-by-2/3 stage normally divides its input by two in frequency, but will swallow an extra cycle per OUT period when its control input, Di, is set to 1. As shown for the case where all control bits are set to 1, the number of IN cycles swallowed per OUT period is binary weighted according to the stage position. For instance, setting D0 = 1 causes one cycle of IN to be swallowed, while setting D2 = 1 causes 4 cycles of IN to be swallowed. Proper selection of {D2D1D0} allows any integer divide value between 8 and 15 to be achieved.
The 64 modulus divider that was developed for the prototype system uses a similar principle to that discussed above, but has a modified first stage to achieve high speed operation. Specifically, the implemented architecture consists of a high speed divide-by-4/5/6/7 state machine followed by a cascaded chain of divide-by-2/3 state machines as illustrated in Figure 1.19. The divide-by-4/5/6/7 stage accomplishes cycle swallowing by shifting between 4 phases of a divide-by-2 circuit. Each of the 4 phases is staggered by one IN cycle, which allows single cycle pulse swallowing resolution despite the fact that two cascaded divide-by-2 structures are used. This phase shifting approach, which is also advocated in [53], allows a minimal number of components to operate at high frequencies — the first two stages are simply
divide-D2 = 1 D1 = 1 D0 = 1
(1 per OUT period)
2/3 2/3 2/3
IN A B OUT
D0 D1 D2
Di = 1 Di = 0 2
IN A B OUT
8 + D0*20 + D1*21 + D2*22 Cycles Swallow cycle
Figure 1.18: An asynchronous, 8-modulus divider topology.
by-2 circuits, not state machines. Also, the fact that control signals are not fed into the first divide-by-2 circuit allow it to be placed off-chip in the prototype.
2 2 FF2 F34 F1 4/5/6/7
4 to 1 MUX
D2 D3 D4 D5
OUT
D0
D1 CONTROL
2/3 2/3 2/3
IN 2/3
off-chip
Figure 1.19: An asynchronous, 64 modulus divider implementation.
1.8.2 Loop Filter
The achievement of accurate PLL dynamics is accomplished in the prototype system with the variable gain loop filter topology depicted in Figure 1.20. Surrounding stages relevant to the loop filter description are included and will now be described. The PFD output is a square wave voltage waveform whose duty cycle varies according to the input modulation data. The shaded region corresponds to the approximate duty cycle span that 2.5 Mbit/s would take up in the prototype. A conversion of the PFD output from voltage to current is made by the charge pump, which yields two complementary current waveforms with modulated duty cycles. These current
1.8. IMPLEMENTATION HIGHLIGHTS 39
waveforms are fed into the inputs of an opamp that integrates one current and adds to it a first order filtered version of the other current. The first order pole, wp, is created using a switched capacitor technique, which reduces its sensitivity to thermal and process variations and removes need for tuning the time constant. An important characteristic of the loop filter is that it has a continuous-time output despite the fact that the discrete-time switched capacitor method is used to set its time constant.
C1
Vout C2
C0
clk1 clk2
I -I Charge
Pump PFD F
I -I
Figure 1.20: PFD, charge pump, and loop filter.
Since the loop filter achieves accurate time constants that are insensitive to process and temperature variations, the only parameter that needs to be tuned to obtain accurate PLL dynamics is its open loop gain. In the illustrated topology, gain control is achieved by varying the value of I produced by the charge pump. This leads to the need for a variable current charge pump, which is described later in the thesis.
1.8.3 Σ-∆ structure
A low power, digital Σ-∆ modulator was realized in the prototype by using a pipelin-ing technique to allow reduction of its power supply voltage. The use of this technique relied on the fact that the Σ-∆ could be implemented as a MASH structure [47] since a multiple bit output is required. (A MASH structure of order n requires at least n output bits [47].)
Figure 1.21 illustrates the second order, MASH topology used in the prototype; it consists of cascaded first order sections that contain no surrounding feedback loops.
This structure is pipelined by applying a well known technique that has been used for adders and accumulators [54, 55]. Figure 1.22 illustrates a 3-bit example; the key principle is that registers are inserted in the carry chain of the adder to reduce its critical path. To achieve time alignment between the input and the delayed carry information, registers are also included to skew the input bits. The adder output is realigned in time by performing an “align shift” of its bits as shown. The same approach can be applied to digital accumulators since there is no feedback from higher to lower bits. Since its basic building blocks are adders and accumulators, this technique allows a MASH Σ-∆ modulator of any order to be pipelined.
carry
error
out 1st order S-D
D in
1st order
S-D 1st orderS-D
1 - D error
out out
IN
16-bit
OUT6-bit 20 MHz
20 MHz
Figure 1.21: A second order, digital MASH, Σ-∆ structure.
Co Cin A
B S
D D
D D
D
Co D Cin A
B S
D D
D
D Co D
Cin A
B S
A2[k]
A1[k]
A0[k]
B2[k]
B1[k]
B0[k]
S2[k]
S1[k]
S0[k]
Figure 1.22: A pipelined adder topology.