Analog Phase Comparison Path
9.1 Implementation
This section describes the circuits used to implement the various component blocks in Figure 9.1.
9.1.1 PFD
The requirement of a fifty percent nominal duty cycle at the output of the PFD prevents this component from being implemented by a common tri-state design [60].
The circuit implementation chosen for the PFD, depicted in Figure 9.2, is taken directly from on an extended XOR design described in [44]. Under locked conditions in the PLL, phase comparison is accomplished in the structure through the use of an XOR gate. The phase detection region of the XOR gate is extended to 360 degrees by dividing Ref and Div by two in frequency before sending these signals to its inputs,
9.1. IMPLEMENTATION 127
which leads to a PFD output frequency equaling the reference frequency. When the PLL is out of lock, frequency detection is accomplished by gating the XOR output with the outputs of two cross coupled registers that force the PFD to a high or low value according to the sign of the frequency error between Div and Ref .
D Q SQ D
Q Q R
D Q Q D
Q Q
Ref/2 Div/2 Ref
Div
Shigh
Slow
E
Divide-by-2 Frequency
Detector Phase
Detector
C
Figure 9.2: Schematic diagram of PFD.
To provide more detail of the phase detector portion of the PFD, Figure 9.3 illustrates the DC characteristic of the XOR gate as a function of the phase difference in its input signals. As discussed in [60], the DC output of the XOR gate is a triangular function of the DC value of Φe[k]. Since the effective gain of the XOR corresponds to the slope of its DC characteristic, we see that the gain of the PFD flips between positive and negative values as Φe[k] is changed. Since the stability of the PLL feedback loop is a function of the sign of the PFD gain, the operation of the XOR is seen to vary between stable and unstable regions. In the context of the PLL feedback loop, a positive sign for the phase detector gain will be assumed to yield stable dynamics.
The stable and unstable regions of the XOR gate can be discerned by the value of its output, C, on rising transitions of Ref and Div . In the stable region, C is low when Ref transitions high and is high when Div transitions high. The opposite conditions are true in the unstable region.
The frequency detector portion of the PFD uses the above XOR characteristics to advantage. Specifically, the registers within the frequency detector monitor the value of C at positive transitions of Ref and Div to determine the XOR gate’s current region of operation. If the XOR is in the stable region, which is the case under locked conditions, its output passes directly to the PFD output. If the XOR enters the unstable region, the output of the PFD is set either low or high according to the state diagram shown in Figure 9.4. As indicated in the figure, the PFD output is set high if the Ref transition is the first to occur in the unstable region. Conversely
Ref/2
Div/2
Stable Region Unstable Region
Div & C=1
Ref & C=0 Ref & C=1 Div & C=0
Ref Div
0o 360o 720o
Fref - Fdiv
DC error voltage
C
Figure 9.3: XOR characteristic and associated signals within the PFD.
the PFD output is set low if the Div transition occurs first in the unstable region.
These output values remain constant until the XOR enters back into its stable region.
Figure 9.5 provides an example of the signals that occur in the PFD logic when the frequency of Div is higher than that of Ref . In this case, E correctly directs the VCO to lower its output frequency by virtue of its low average value.
E = 0 E = C E= 1
Ref & C=1 Ref & C=0
Div & C=1
Div & C=0 Shigh Slow
= 1
= 1
Shigh Slow
= 0
= 1 Shigh
Slow
= 1
= 0
Figure 9.4: State transition diagram of the frequency detector portion of the PFD.
9.1. IMPLEMENTATION 129
Ref/2
Div/2
E Shigh
Slow C
Figure 9.5: Example of signals produced from PFD when Div frequency is too high.
9.1.2 Charge Pump
Proper design of the charge pump is critical for the achievement of high data rates since it forms the bottleneck in dynamic range that is available to the modulation signal. Figure 9.6 illustrates the fundamental issues that need to be considered in its design. To avoid distortion of the modulation signal, the variation in duty cycle should be limited to a range that allows the output of the charge pump to settle close to its final value following all positive and negative transitions. Figure 9.6(a) shows the dynamic range available for a well designed charge pump; the nominal duty cycle is fifty percent and the transition times are fast. Figure 9.6(b) demonstrates the reduction in dynamic range that occurs when the nominal duty cycle is offset from 50 percent. This offset is caused by a mismatch between positive and negative currents produced by the charge pump. (The type II PLL dynamics force an average current of zero.) Finally, Figure 9.6(c) illustrates a case in which the charge pump has slow transition times, the result again being a reduction in dynamic range.
The charge pump topology was designed with the above issues in mind, and is illustrated in Figure 9.7. The core component of the architecture is a differential pair (M1 and M2) that is fed from the top by two current sources, I1 and I2, and from the bottom by a tail current, Itail. Ideally, I1 and I2 are equal to I and Itail to 2I, where I is adjusted by a 5-bit D/A that controls the voltage at node VD/A. Transistors M1 and M2 are switched on and off according to E, which ideally causes IIN and IIN to switch between I and −I.
To achieve a close match between the positive and negative currents of each charge pump output, the design strives to set I1 = I2 and Itail = I1 + I2. In the first case, I1 and I2 are implemented as cascoded PMOS devices whose layout is optimized to achieve high levels of device matching. Unfortunately, device matching cannot be used to achieve a close match between Itail and I1+ I2 since they are generated by
0I - I DesignedWell
0
I - I + e Mismatch in Current
- I0
TransientLong Time
I (a)
(b)
(c)
Figure 9.6: Effect of transient time and mismatch on duty cycle range.
I1= I 2I
4I VREF
Cc
Isw Isw
M2 M1
M3
Fss
Fss
IIN
IIN
Charge Pump Core Level Converter
Replica Feedback
Vbias1 VD/A Vbias2
I2= I
Itail= 2I
E' E'
OP1
Figure 9.7: Charge pump implementation.
different types of devices. To circumvent this obstacle, a feedback stage is used to adjust Itail by comparing currents produced by a replica stage. This technique allows Itail to be matched to I1 + I2 to the extent that the replica stage is matched to the core circuit.
The achievement of a low transient time in the charge pump response is obtained by careful design of signal and device characteristics at the source nodes of M1and M2. First, the parasitic capacitance at this node is minimized by using appropriate layout techniques to reduce the source capacitance of M1 and M2, the drain capacitance of M3, and the interconnect capacitance between each of the devices. Second, the voltage deviation that occurs at this node when E switches is minimized. The level converter
9.1. IMPLEMENTATION 131
depicted in Figure 9.7 accomplishes this task by reducing the voltage variation at nodes Φss(t) and Φss(t) to less than 350 mV and setting an appropriate DC bias.
An additional level converter is required between the PFD output, E, and charge pump inputs, E and E since separate supplies are used for the digital and analog sections of the chip. The level converter shown in Figure 9.8 transfers the E signal between these supplies. In addition, this circuitry allows a bit from an on-chip shift register to set the sign of the open loop gain.
sign E
E' E' Analog Supply
Digital Supply
Figure 9.8: Interface circuitry between PFD and charge pump that level converts E from digital to analog supplies, and sets the sign of the open loop gain.
9.1.3 Loop Filter
The on-chip loop filter uses an opamp to integrate one of the charge pump currents and add it to a first order filtered version of the other current. Shown in Figure 9.9, this topology yields a transfer function that is closely approximated as
H(f ) = Kl 1 + jf /fz
jf (1 + jf /fp), fz = 11.6kHz, fp = 127kHz. (9.1) Details of the accuracy of this approximation, as well as its derivation, are presented in the modeling section of this chapter. The open loop gain, Kl, is adjusted by varying the charge pump output current, I. The first order pole, fp, is created using a switched capacitor technique, which reduces its sensitivity to thermal and process variations and removes any need for tuning. Note that, although this time constant is formed through a sampling operation, the output of the switched capacitor filter is a continuous-time signal. Finally, the value of the zero, fz, is determined primarily by the ratio of capacitors C3 and C2 under the assumption that the complementary charge pump output currents are matched.
C1
C3
C2
Vout IIN
IIN
0
0
I - I I - I
clk1
clk2
Vref
clk1 clk2
clk2 clk1
clk1
clk2
C4 Vref
OP2 30 pF
3 pF 120 fF
0.9 uA < I < 3.5 uA 3 pF
Figure 9.9: Loop filter implementation.
A particular advantage of the filter topology is that the rate of sampling C1 and C2 can be set high since it is independent of the settling dynamics of the opamp. As such, clk1 and clk2 are set to the PFD output frequency, 20 MHz, to avoid aliasing problems.
As illustrated in Figure 9.10, the opamp is realized with a single-ended, two-stage topology chosen for its simplicity and wide output swing. Its unity gain frequency was designed to be 6 MHz; this value is sufficiently higher than the bandwidth of the GFSK modulation signal at 2.5 Mbits/s to avoid significantly affecting it. It is recognized that the single ended structure has higher sensitivity to substrate noise than a differential counterpart. However, little would be gained in this case by making it fully differential since the output of the opamp is connected directly to the varactor of an LC based VCO, which is inherently single ended. Fortunately, measured results in Chapter 11 show that substrate noise does not significantly degrade the noise performance of the synthesizer.
The limited dynamics of the opamp prevent it from following the fast transitions of its input current waveforms. To prevent these waveforms from adversely affecting the performance of the charge pump and opamp, the voltage swing that appears at the input terminals of the opamp is reduced to a low amplitude (less than 40 mV peak-to-peak) by capacitors C1 and C4. (The resulting voltage waveform is approximately triangular in nature.) In the case of C1, this capacitor also serves as part of the switched capacitor filter.
A large voltage swing at the input terminals of the opamp would undermine the operation of the charge pump and loop filter circuitry. A high amplitude triangle wave would alter IIN(t) according to the finite output resistance of the charge pump