Chapter 5 PVT Sensors for Micro-Watt DVFS System Design
5.3 Multi-threshold CMOS SC DC-DC Converter
5.3.1 Architecture of Multi-threshold CMOS SC DC-DC Converter
To realize the full energy savings of subthreshold operation, a DC-DC converter supplying ultra-low voltages at high efficiencies is essential. Since the power consumption of the micro-watt load circuits drops exponentially at subthreshold voltages, the DC-DC converter was designed to deliver a maximum of 100μA of load current. This reduced load power demand makes switched capacitor DC-DC conversion an ideal choice for this application. The switched capacitor (SC) DC-DC converter is based on [5.2], and makes use of 15 pF of total on-chip charge transfer (flying) capacitance to provide fix load voltages 200~300mV.
Non- Overlapping
Figure 5.9. Architecture of switched capacitor DC-DC converter
Fig. 5.9 shows the architecture of the DC-DC converter. The converter uses a pulse frequency modulation (PFM) mode of control to regulate the output voltage. A TDC-based comparator clocked by the signal clk is used for this purpose. When the output voltage VOUT is above VREF, the switches are all set to the Φ1 mode. When VOUT falls below VREF, the comparator triggers a Φ2 pulse, which charges up the output load capacitor Cload. The non-overlapping clock generator block prevents any overlap between the Φ1 and Φ2 ON phases. A PFM mode control is crucial to achieving high efficiency for the extremely low power system being built. The switch matrix block contains the charge transfer switches and the charge transfer capacitors.
The external voltage input to the system is 0.5V. The gain setting at no-load provides a voltage ratio output of the input voltage. The switching losses in the
capacitors just settle at the end of a charge transfer cycle. In order to scale switching losses with load power, the charge transfer switches have adjustable widths which are enabled by the signals VOP1, VOP2 as shown in the inset of Fig. 5.10.
The signals VOP1, VOP2 are generated by comparator. When the difference voltage between VOUT and VREF is larger, both the signals VOP1, VOP2 are set to 1.
While VOUT is below VREF, VOP1 is set to 0. When next cycle, the VOUT is still below VREF, VOP2 is set to 0. This helps to decrease the switching power, leading to an increase in efficiency at lower load power levels.
VBAT VOUT
2CB
Ф1
Ф1
Ф2
Ф2
Ф2
3CB VOUT
0.5V
0.2V 0.3V
LVT
HVT LVT
V
BATФ
1Ф
2V
OUTVOP1
VOP2 X1
X2
Figure 5.10. Switch matrix and simplified representation of the switch size control.
The efficiency of DC-DC converter is shown in Fig. 5.11. The converter was able to achieve >60% over a load current range from 10μA to 100μA. However, at very low load power levels (sub-5μW), leakage and other fixed losses in the control circuitry reduce the efficiency of the switched capacitor DC-DC converter [5.5].
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
80.00%
0 50 100 150
Power Efficiency
Load Current(μA) SC DC-DC Converter
Figure 5.11. DC-DC converter efficiency while delivering 300 mV
5.3.2 Delay Line Comparator
As we know, operating speed of the circuit depends on its supply voltage. Higher supply voltage makes the circuit working faster than the lower supply voltage one.
Thus, a comparator can be implemented through this characteristic. Fig. 5.12 shows the circuit of comparator, it composed of two stack-inverter chain and two D Flip-Flop. One of the two stack-inverter chain was connected to VREF as stack nmos gate voltage. The other one was connected to VOUT as stack nmos gate voltage. The two inverter chains input a clock signal (CLK) at the same time. When VREF is greater than VOUT , the below one has slower speed than above one. Therefore, while DFF triggered, Data is still 1, the signal VOP1 is 1. On the other hand, when VREF is less than VOUT , the above inverter chain one has slower speed than below one. Thus, Data will ready before clock trigger DFF. The signal VOP1 is 0, which means VOUT is greater than VREF.
D Q
VREF
CLK
CLK
D Q
VOP2 VOP1
VOUT
Figure 5.12. Delay line comparator
In Fig. 5.12, there is another signal named VOP2. The difference between VOP1 and VOP2 is the number of stack-inverter chain. It raised more inverter as a longer inverter chain. This target is to differentiate the degree of the difference voltage between VREF and VOUT. While VREF is much greater than VOUT, the delay of longer inverter chain which connected to VREF is still shorter than connected to VOUT one, even though it passed more inverter gate. Hence, when both the two signal VOP1 and VOP2 is 1, it presents the degree of the difference voltage between VREF and VOUT is large. So it need increased the width of switch in switch matrix to make the voltage transmit faster. The proposed comparator can compare 5mv voltage difference.
5.3.3 Subthreshold Voltage Reference
The traditional BVR(bandgap voltage reference) shows in Fig. 5.13 performance suffers as the supply voltage is lowered. The ability of the op amplifier to properly function as an error generator is reduced as the Input Common Mode Range (ICMR) of the op amplifier is degraded with a lower supply voltage when high loop gain is desired. This inhibits the reference's ability to match the PTAT and CTAT currents, resulting in a less accurate reference. The use of diodes to produce CTAT and PTAT
current outputs is impractical at low voltages, as the built-in voltage of a pn-junction is around 700mV and that severely limits the lower limit of the supply voltage;
especially considering that all MOSFETs in the circuit are normally designed to have enough voltage headroom to operate in their saturation region.
A low power and low voltage subthreshold voltage reference is proposed and shown in Fig. 5.13. This design makes use of the weak inversion region of MOSFET operation to allow for an extremely low supply voltage with commensurate low power expenditure. Layout size is also reduced compared to the conventional BVR. The proposed subthreshold voltage reference is comprised of a bias network, a CTAT voltage generator, and a PTAT voltage generator that combine to produce the output reference voltage. As such, the drain current of a PMOS transistor operating in weak inversion can be modeled as,
nV )
Where n is a slope factor (usually 1~2), and VT is the thermal voltage. Solving for VSG and including its temperature dependence yields,
) )
near-linear component comes from Vth. Although this component isn't exactly linear, it can be approximated with a linear function in the temperature range we are using.generate a simple low voltage and low powered PTAT voltage, a diode connected NFET was used. Fig. 5.14 shows the simulated gate-to-source voltage of M8 and the source-to-gate voltage of M6 as the temperature is swept from -40 °C to 100 °C. As shown in Fig. 5.14, the source-to-gate voltage of M6 is CTAT and the gate-to-source voltage of M8 is PTAT. The CTAT source-to-gate voltage of M6 is applied to transconductance device M7 and the resulting current through M7 is CTAT. By scaling the sizes of M7 and M8 appropriately, when the CTAT current of M7 is passed through M8, the resulting gate-to-source voltage on M8 is (ideally) independent of temperature. The matching of the CTAT to PTAT characteristics is improved through the feedback mechanism present in M1-M5.
As shown in Fig. 5.15, the proposed subthreshold voltage reference shows a reference voltage of 319 mV with a 500 mV supply. The maximum variation in the output voltage is 711.78 μV or 2.2ppm/°C, over a -50°C to 100°C range. A variation of 121 μV, or 0.38ppm/°C, was demonstrated in the -50°C to 100°C range.
VREF VDD
VSS
Figure 5.13. Proposed Bandgap Voltage Reference (BVR).
40 90 140 190 240
-50 0 50 100 150
V SG (m v)
Temperature(℃)
CTAT VSG
300 350 400 450
-50 0 50 100 150
V G S( m v)
Temperature(℃)
PTAT VGS
Figure 5.14. Simulated temperature dependence of an NFET and PFET.
0.3186 0.3187 0.3188 0.3189 0.319 0.3191 0.3192 0.3193 0.3194
-50 0 50 100 150
V R EF (V )
Temperature(℃)
Figure 5.15. Simulated VREF versus temperature.
5.3.4 Variable Voltage Reference Generation by DAC
In section 5.3.3, the subthreshold voltage reference can only output a fixed voltage 319 mV with a 500 mV supply. So this section proposed a variable voltage reference
voltage reference generation with temperature variation.
Figure 5.16 Resistor-string DAC for variable voltage reference generation.
Variable Voltage Reference
0 0.2 0.4 0.6 0.8 1 1.2
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Temperature (°C)
Output Voltage (V)
0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1V
Figure 5.17 Variable voltage reference generation with temperature variation.
Table 5.1 Temperature variation
Temperature -40°C 30°C 140°C Variation
1V 1.02 1.0 1.04 0.04V
0.9V 0.92 0.9 0.94 0.04V
0.8V 0.82 0.8 0.83 0.03V
0.7V 0.71 0.7 0.73 0.03V
0.6V 0.61 0.6 0.62 0.02V
0.5V 0.51 0.5 0.52 0.02V
0.4V 0.41 0.4 0.42 0.02V
0.3V 0.31 0.3 0.31 0.01V
5.4 Post-Layout Simulation Results
5.4.1 Layout
Layout view of the MTCMOS SC DC-DC converter with MOS capacitors in UMC 65nm standard CMOS technology is shown in Fig. 5.18(a). The area of MOS capacitors is smaller but has serious current leakage than other capacitors, so it has low power efficiency in very light load condition.
Layout view of the MTCMOS SC DC-DC converter with MOM capacitors in TSMC 65nm standard CMOS technology is shown in Fig. 5.18(b). The current leakage of MOM capacitors is small, so it has high power efficiency in light or heavy load condition.
(a)
156um
127um
MOM Cap.
DC-DC control
Pre-amp
TSMC 65nm
156um
127um
MOM Cap.
DC-DC control
Pre-amp
TSMC 65nm
(b)
Figure 5.18 Layout view of the SC DC-DC converter. (a) with MOS capacitor in UMC 65nm CMOS tech. (b) with MOM capacitor in TSMC 65nm CMOS tech.
5.4.2 The Layout of the power MOS
From layout view of SC DC-DC converter, we knows that the size of power MOS may be one thousand (1000um) in the maximum current loading. The huge size causes different layout for some purpose.
In Fig. 5.19, the poly-silicon is drawn as a beehive in order to get better electro-Static Discharge (ESD) protection. In this kind of layout, the drain and source
body model, machine model, charged device model and field induced model.
The human model and machine model are caused by the external static electricity.
Therefore, we usually make some protection between the core and the pad. In the output ping, we usually use an output stage with large size to push the external load.
The large size output stage which can endure large current is also a good discharge path of the static electricity. Therefore, we draw the layout as Fig. 5.19(a) to make the power MOS as an output stage with better ESD protection.
However, the layout as Fig. 5.19(b) will save more area. Fig. 5.20 shows the equivalent MOS of Fig. 5.19(a) and (b) in the same area. The layout as Fig. 5.19(a) will produce 30 equivalent MOS and the layout as Fig. 5.19(b) will produce 49 equivalent MOS.
(a)
(b)
Figure 5.19 The layout of the Power MOS (a) with better ESD protection (b) with better efficiency of area.
(a) (b)
Figure 5.20 The equivalent MOS of layout in Fig. 5.18(a) and(b).
5.4.3 Post-Simulation Results
The transient response of SC DC-DC converter is shown in Fig.5.21. The converter was able to achieve >60% over a load current range from 10μA to 100μA. The converter has small voltage variation, because the proposed delay-line based comparator can detect 5mv voltage variation. The comparison of switched capacitor DC-DC converter is shown in Table 5.2.
Figure 5.21 The transient response of SC DC-DC converter.
Table 5.2 Comparison of [5.2], [5.5] and proposed switched DC-DC conberter.
Ref.[5.2] Ref.[5.5] This work (MOS Cap.) This work (MOM Cap.)
Technology 0.18μm 65nm UMC 65nm TSMC 65nm
Input Voltage 1.2V 0.5V 0.5V 0.5V
Output Voltage 0.3~1.1V 0.3V 0.2~0.4V 0.2~0.4V
Variation
ΔVOUT 8% 10% 4% 4%
MAX Load
Current 400uA 400uA 70uA 80uA
Power Efficiency
75%@(1.2V to
0.5V) 75% 70%@(0.5V to 0.4V)
60%@(0.5V to 0.2V)
78%@(0.5V to 0.4V) 64%@(0.5V to 0.2V)
Switch Cap. 0.6nF 600pF 30pF(MOS Cap.) 30pF(MIM. Cap.)
Response time 540ps 288ps 500ns(0.5V to 0.4V) 450ns(0.5V to 0.4V)
Area(μm2) 750000 120000 7200 21280
5.5 Temp. Compensation for Low-voltage Digital Assisted PLL
A conventional phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input "reference" signal. A phase-locked loop circuit compares the phase of the input signal with a phase signal derived from its output oscillator signal and adjusts the frequency of its oscillator to keep the phases matched.
The architecture of PLL is shown in Fig. 5.22. A phase detector (PFD) compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the VCO frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.
PFD CP
Divider UP
DN Ref
200MHz
VCO
10MHz
VDD
N
Figure 5.22 Architecture of phase lock loop (PLL).
When we reduce the supply voltage to near/ sub-threshold region (VDD≦0.5V), the VCO output frequency range does not cover desired frequency in FF, 0.55V, 100℃ and SS, 0.45V, 0℃. The VCO output frequency shows the simulation result as below Fig. 5.23.
100℃
0℃
SS, 0.45V TT, 0.5V
FF, 0.55V
SS, 0.45V TT, 0.5V
FF, 0.55V
Desired frequency
0.1 0.2 0.3 0.4
Frequency (Hz)
Voltage (V)
Figure 5.23 Simulation results of VCO output frequency in different environment condition.
Because of above problem, we use temperature sensors to compensate the VCO output frequency. The architecture of proposed temperature compensation for low-voltage digital assisted PLL is shown in Fig. 5.24. The VCO output frequency with temperature compensation shows the simulation result as below Fig. 5.25. From the above simulation results, the VCO output frequency can cover desired frequency range after temperature compensation.
PFD CP
Divider
UP
DN Ref
0.5V
200MHz
VCO
TS
10MHz
3
N
Figure 5.24 Architecture of proposed temp. compensation for low-voltage digital assisted PLL.
100℃
0℃
SS, 0.5V TT, 0.5V FF, 0.55V
SS, 0.5V TT, 0.5V
FF, 0.55V
Desired frequency
range
0.1 0.2 0.3 0.4
Voltage (V) Frequency (Hz)
Figure 5.25 Simulation results of VCO output frequency in different environment condition with temperature compensation.
5.6 Summary
This chapter presents circuits that enable dynamic voltage and frequency scaling (DVFS) for micro-watt system to reduce both dynamic and leakage power dissipation.
The system consists of the MTCMOS SC DC-DC converter, and temperature compensation technique for low-voltage digital assist PLL. The SC DC-DC converter uses PVT sensors to adjust output supply voltage in different environmental variation.
Low-voltage PLL uses temperature sensor to compensate the output frequency.
For MTCMOS SC DC-DC converter, we improve the output voltage variation and power efficiency by using delay-line based comparator and multi-threshold CMOS technology. For low-voltage digital assisted PLL, we use temperature sensor to compensate VCO output frequency in worse case.
Chapter 6 Conclusions and Future Work
6.1 Conclusions
In this thesis, we proposed a 1-point calibration near-/sub-threshold PVT sensor in Chapter 3. A self-calibration near-/sub-threshold digital PVT sensors and a self-calibration near-/sub-threshold digital temperature sensor with adaptive pulse width generator are proposed in Chapter 4. In Chapter 5, we proposed a multi-threshold CMOS switched capacitor (SC) DC-DC converter with 70% power efficiency and 4% voltage variation for micro-watt DVFS system design. We also proposed a temperature compensation for low-voltage digital assisted PLL; it can generate output frequency cover our desired frequency in any environment condition.
The research results of Chapter 3, Chapter 4, and Chapter5 are applied to PVT sensors for micro-watt DVFS system design.
The PVT sensors micro-watt DVFS system can provides process, voltage, and temperature value, dynamically varying clock frequency and supply voltage level.
The DVFS control can reduce total energy consumption in sleep mode.
6.2 Future Work
Wireless medical microsensors are usually with two different operating modes:
Low-Power Mode and Performance Mode because the well-known signals of the main characteristics of cardiac activity, e.g. heart rate and ECG, are at a very low rate.
More than 99% operating time of sensor nodes are operating in low-power mode to record various physiological signals throughout its life time while only less than 1%
operating time in performance mode to process and transmit real-time informative
cardiovascular parameters to a host. This low-power-mode-dominated scenario is capable of further reducing total energy consumption if dynamic voltage scaling (DVS) technique is applied. The benefit of DVS technique is attributed to the quadratic savings in active CVDD2
energy. In this work, an on-chip switched capacitor(SC) DC-DC converter which can deliver desired supply voltage for each operating mode is integrated with proposed asynchronous 8T SRAM-based FIFO.
Device in low-power mode and performance mode will perform sub-threshold operation and near-threshold operation respectively.
A robust near-/sub-threshold SRAM-based FIFO for WBAN applications is shown in Fig. 6.1(a). To achieve high reliability and extend battery working time, ULV dual-port SRAM-based FIFO is applicable. The conventional dual-port SRAM fails to perform reliable subthreshold operation because of read disturb induced read static noise margin (RSNM) degradation. Plenty of subthreshold SRAMs have been implemented to overcome the degradation. However, threshold voltage shift due to random doping fluctuations and processing variation causes SRAM reliability getting worse. In addition, the reduction of signal level directly hurts the noise margin of memory. As technology scaling, the smaller Ion-Ioff-ratio limits the sharing elements like SRAM. All of the ULV effects are considered in 2Kb proposed 8T SRAM cell, shown in Fig. 6.1(b), in this work.
Besides a near-/sub-threshold memory is required, a novel switched capacitor (SC) DC-DC converter and smart dynamic voltage scaling controller are proposed. The schematic views of them are shown in Fig. 6.2(a) and Fig. 6.2(b), respectively. The SC DC-DC converter uses a pulse frequency modulation (PFM) mode of control to regulate the output voltage. When the output voltage V is above V , the switches are
generator block prevents any overlap between the Φ1 and Φ2 ON phases. The power efficiency of DC-DC converter is no less than 70% over a load current range from 10μA to 100μA. Following a request for a voltage switch (where the signal MODE changes), correct operation of the FIFO is guaranteed by sending a stall request before the actual switching of voltage. Stalling prevents processor operation during the period when the voltage supply is not completely connected. The stored data in FIFO are preserved within the internal circuits. When stalling is finished, a confirmation signal (stall_done) is transmitted back to the supply switch circuit. Finally, the stall signal is released after the new voltage supply is fully connected.
Thermal issues are fast becoming major design constraints in subthreshold systems.
Temperature variations adversely affect system reliability and prompt worst-case design. A dynamic temperature management (DTM) techniques uses to target average-case design and tack the temperature issue at runtime. A novel digital temperature sensor and dynamic temperature management mechanism are proposed.
The schematic views of them are shown in Fig. 6.3(a) and Fig. 6.3(b), respectively.
VVDD
Figure 6.1 (a) Block diagram of Near/Sub- threshold FIFO memory. (b) Proposed 8T Near/Sub-threshold SRAM cell.
Non- Overlapping
Figure 6.3 (a) Self-calibration temperature sensor with adaptive pulse width generator.
(b) DTM algorithm.
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