Chapter 5 PVT Sensors for Micro-Watt DVFS System Design
5.2 Switched Capacitor DC-DC Converter
DVFS systems often require multiple on-chip voltage domains. A switched capacitor (SC) DC-DC converter is a good choice for such battery operated systems because it can minimize the number of off-chip components and does not require any inductors. Compared to commonly use linear regulators for on-die voltage conversion, SC converters can provide 15%–30% higher efficiencies when the output voltage delivered is less than half the input voltage.
5.2.1 Conventional SC DC-DC Converter
Fig. 5.2 shows the architecture of the SC DC-DC converter [5.2]. At the core of the system is the switch matrix which contains the charge-transfer capacitors, and the topology, charge-transfer switches. A suitable topology is chosen depending on the reference voltage Vref, which is set digitally. The digital reference is converted to an analog value using an on-chip charge redistribution digital-to-analog converter. A pulse frequency modulation (PFM) mode control is used to regulate the output voltage to the desired value. A dynamic comparator clocked by the signal clk is used for this purpose. When the output voltage VO is above Vref, the switches are all set to the Ф1 mode. When VO falls below Vref, the comparator triggers a Ф2 pulse, which charges up the output load capacitor Cload. The nonoverlapping clock generator block prevents any overlap between the Ф1 and Ф2 ON phases. Typical waveforms of these phases are shown in the inset in Fig. 5.2. Bottom-plate parasitics of the on-chip capacitors significantly affect the efficiency of the converter. A divide-by-3 switching scheme was employed to mitigate the effect due to bottom-plate parasitic and improve efficiency. The switching losses are scaled with change in load power by the help of an automatic frequency scaling block. This block changes the switching frequency as the load power delivered changes, thereby reducing the switching losses at low load.
Figure 5.2 Architecture of the switched capacitor DC-DC converter system.
5.2.2 Switch Matrix
The operation of switched capacitor matrix is able to provide five different common phases and gain phases, with the gain being the ratio of the output voltage Vout to the input voltage Vin. The equivalent circuits of these conversion phases are shown in Fig. 5.3 [5.3].
whose gains are less than 1 and one gain configuration referred as unit gain with gain equal to 1. According to the input and the output, the DC-DC converter is divided to step-down type or buck type converter (Vout<Vin).
While the converter is clocked and the gain setting is chosen, the switched capacitor matrix is switched between the common phase and the chosen gain phase to transfer charges from the input to the output to keep the chosen output voltage. The gain configuration of 1/2 is used as an example to explain the implementation of gains through the switched capacitor matrix. The equivalent circuit of gain configuration of 1/2 is shown in Fig. 5.4[5.4] below. The flying capacitor Cf is used to store and transfer energy, and capacitor Ch is the hold capacitor for the output.
Figure 5.4 Equivalent circuit of the gain configuration with gain of 1/2.
At time nT, the switched capacitor stays at the end of the gain phase, and the charges in the capacitors Ch and Cf are
(nT) V
× C
= (nT)
Q
ch h out (5.1)(nT)
charges in the capacitors Ch and Cf are2 )
According to the theory of charge conversation, we have( / 2) ( / 2) ( ) ( )
ch cf ch cf
Q nT T Q nT T Q nT Q nT
(5.5) Solving Equation (5.1)-(5.5) results in( / 2) f h f ( ) the theory of charge conservation, the total charges in the capacitors Ch and Cf are
( ) ( / 2) ( / 2)
total ch ch
Q nT T Q nT T Q nT T
(5.9) So the output voltage at time nT+T is2
According to Equation (5.10), we can have
2
According to Equation (5.11) and (5.12), we can have
2 1
Where k=0,1,2…. ,because of b<1,we can have
2 2
5.2.3 Conventional Bandgap Voltage Reference
The traditional bandgap voltage reference, as shown in Fig. 5.5, is the combination of a voltage that is proportional to absolute temperature (PTAT) and a voltage that is complementary to absolute temperature (CTAT). The CTAT is traditionally generated from a diode (or diode-connected BJT). The current through the pn-junction of a diode has a dependence on temperature which is well-characterized and predictable.
The PTAT current is generated, as seen in Fig. 5.5, by BJTs Q1 and Q2, resistor R1, the op amplifier and the current sourcing FETs M1 and M2. The op amplifier feedback loop sets the currents through M1 and M2 to the same value. As Q1 and Q2 have emitter areas that differ by a factor of n, their temperature response will differ. The BJTs will sink the same amount of current, but a PTAT current will flow through R1.
This current is added to the CTAT generator, Q3, through M3. The size of M3 and the ratio of R2 to R1 are chosen so that the PTAT current is translated into a PTAT voltage that is equal to the CTAT voltage of Q3. This produces an almost temperature independent reference voltage (neglecting 2nd-order-and-above effects). The temperature dependence of the current through the pn-junction of the diode is naturally CTAT. The PTAT characteristic used to null the CTAT behavior is created by scaling the inherent thermal voltage of a BJT (VT). The reference voltage of a traditional BVR can be described in equation (5.15).
n ln R V
V R
V
T1 2 1 BE
REF
= +
(5.15)
AMP1 +
-M1 M2
Q2 Q1
R1
M3
Q3 R2 VDD
VREF
5.1.4 Automatic Frequency Scaling
To minimize gate-switching losses, the circuit automatically adjusts the switching frequency depending on the load power demand. The automatic frequency scaling (AFS) block that performs the frequency selection is shown in Fig. 5.6 [5.2]. An additional comparator called the overload comparator is used in the AFS block. The reference voltage of the overload comparator is set to Vref-Voff, where Voff is an offset voltage (~20mV) which again is set digitally. When the DC-DC converter, operating in steady state, cannot supply the desired load power at a given switching frequency, VO begins to fall below Vref. As VO falls below Vref–Voff, the overload comparator triggers the go_up signal. This signal is used to double the switching frequency which in turn doubles the width of the charge-transfer switches. At low load powers, the switching frequency is brought down using a counter mechanism. If the number of Ф2 pulses for every 4 clk cycles is found to be less than 3, the go_down signal is triggered which halves the switching frequency and the width of the charge-transfer switches.
The signals enW2 and enW4 determine the switching frequency. When only enW2 is high, 2X the minimum clock frequency is used and when enW4 is high, 4X the minimum clock frequency is used. The signals enW2 and enW4 are fed into the switch matrix to suitably size the charge-transfer switches. While the PFM mode control effectively reduces the frequency of Ф2 pulses as load power decreases, the AFS block helps in bringing down the overall system switching frequency together with the width of the charge-transfer switches, thereby reducing the switching losses in the gate-drive and the control circuitry. The entire control circuitry is digital and consumes no static power, which is a critical feature to achieve good efficiency at ultra-low load power levels. It is extremely scalable in terms of complexity to suit the
Figure 5.6 Automatic frequency scaling circuit.
5.2.4 Efficiency Analysis
Efficiency of a power converter is a key metric for battery operated electronics and energy starved systems. The principal efficiency loss in the SC DC-DC converter is shows in Fig. 5.7 [5.6].
i) Conduction Loss in transferring charge from battery to load
This is a fundamental loss mechanism which arises from charging a capacitor through a switch. To minimize conduction loss, different topologies (Fig. 5.7) are switched in to reduce the difference between the no-load voltage (VNL) of a topology and VO. Assuming that a load voltage less than 600mV is being supplied by the T8 topology, conduction loss imposes a limit on the maximum efficiency that can be achieved to ηlim = VO/0.8. By switching to the T6 topology, this efficiency limit can be improved to ηlim = VO/0.6.
ii) Loss due to bottom-plate parasitic capacitors
occurs because of the energy stored in the parasitic capacitors being dumped to ground every cycle. This loss is more pronounced if on-chip capacitors are used.
Common capacitors in CMOS processes may have up to 20% parasitic at the bottom-plate. On top of these losses are the switching and control losses. The efficiency achievable in a switched capacitor system is in general smaller than which can be achieved in an inductor based switching regulator with off-chip passives.
Further, multiple gain settings and associated control circuitry is required in a SC DC–DC converter to maintain efficiency over a wide voltage range.
Figure 5.7 Energy loss mechanisms in a switched capacitor DC–DC converter.
iii) Gate-drive Loss
The energy expended in switching the gate capacitances of the charge-transfer switches every cycle can be approximately given by
ESW = nCoxWLVBAT2
where n is the number of switches used, Cox is the gate-oxide capacitance per unit area, W and L are the width and length of the charge-transfer switches. The width of each switch is however proportional to the charge-transfer capacitance and the
frequency of switching. This is because the resistance of the switches needs to be low enough to allow settling of the charge-transfer capacitors within the time period of switching.
To minimize the gate-switching loss, depending on the location of the charge-transfer switch and the topology in use, either only a PMOS or an NMOS switch is used instead of a transmission gate comprising both PMOS and NMOS devices.
iv) Power loss in the control circuitry
The power lost in the control circuitry is of specific concern while delivering ultralow load power levels. The control circuitry does not consume any static power (no analog bias currents) other than the subthreshold leakage currents in the digital circuitry.
The overall efficiency can be expressed in a more compact form where the pre-factor is due to the linear efficiency. The 2nd term in the denominator is due to the bottom-plate parasitic loss. The next term is due to gate-drive switching loss, and the 4th and 5th terms are due to switching and leakage loss in the control circuitry.
The efficiency of the SC converter with change in load voltage while delivering 100 μW to the load from a 1.2 V supply is shown in Fig. 5.8 The converter was able to achieve 70% efficiency over a wide range of load voltages. An increase in efficiency of close of 5% can be achieved by using divide-by-3 switching.
Figure 5.8 Efficiency plot with change in load voltage.