Chapter 5 PVT Sensors for Micro-Watt DVFS System Design
5.5 Temp. Compensation for Low-voltage Digital Assisted PLL
A conventional phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input "reference" signal. A phase-locked loop circuit compares the phase of the input signal with a phase signal derived from its output oscillator signal and adjusts the frequency of its oscillator to keep the phases matched.
The architecture of PLL is shown in Fig. 5.22. A phase detector (PFD) compares two input signals and produces an error signal which is proportional to their phase difference. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the VCO frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.
PFD CP
Divider UP
DN Ref
200MHz
VCO
10MHz
VDD
N
Figure 5.22 Architecture of phase lock loop (PLL).
When we reduce the supply voltage to near/ sub-threshold region (VDD≦0.5V), the VCO output frequency range does not cover desired frequency in FF, 0.55V, 100℃ and SS, 0.45V, 0℃. The VCO output frequency shows the simulation result as below Fig. 5.23.
100℃
0℃
SS, 0.45V TT, 0.5V
FF, 0.55V
SS, 0.45V TT, 0.5V
FF, 0.55V
Desired frequency
0.1 0.2 0.3 0.4
Frequency (Hz)
Voltage (V)
Figure 5.23 Simulation results of VCO output frequency in different environment condition.
Because of above problem, we use temperature sensors to compensate the VCO output frequency. The architecture of proposed temperature compensation for low-voltage digital assisted PLL is shown in Fig. 5.24. The VCO output frequency with temperature compensation shows the simulation result as below Fig. 5.25. From the above simulation results, the VCO output frequency can cover desired frequency range after temperature compensation.
PFD CP
Divider
UP
DN Ref
0.5V
200MHz
VCO
TS
10MHz
3
N
Figure 5.24 Architecture of proposed temp. compensation for low-voltage digital assisted PLL.
100℃
0℃
SS, 0.5V TT, 0.5V FF, 0.55V
SS, 0.5V TT, 0.5V
FF, 0.55V
Desired frequency
range
0.1 0.2 0.3 0.4
Voltage (V) Frequency (Hz)
Figure 5.25 Simulation results of VCO output frequency in different environment condition with temperature compensation.
5.6 Summary
This chapter presents circuits that enable dynamic voltage and frequency scaling (DVFS) for micro-watt system to reduce both dynamic and leakage power dissipation.
The system consists of the MTCMOS SC DC-DC converter, and temperature compensation technique for low-voltage digital assist PLL. The SC DC-DC converter uses PVT sensors to adjust output supply voltage in different environmental variation.
Low-voltage PLL uses temperature sensor to compensate the output frequency.
For MTCMOS SC DC-DC converter, we improve the output voltage variation and power efficiency by using delay-line based comparator and multi-threshold CMOS technology. For low-voltage digital assisted PLL, we use temperature sensor to compensate VCO output frequency in worse case.
Chapter 6 Conclusions and Future Work
6.1 Conclusions
In this thesis, we proposed a 1-point calibration near-/sub-threshold PVT sensor in Chapter 3. A self-calibration near-/sub-threshold digital PVT sensors and a self-calibration near-/sub-threshold digital temperature sensor with adaptive pulse width generator are proposed in Chapter 4. In Chapter 5, we proposed a multi-threshold CMOS switched capacitor (SC) DC-DC converter with 70% power efficiency and 4% voltage variation for micro-watt DVFS system design. We also proposed a temperature compensation for low-voltage digital assisted PLL; it can generate output frequency cover our desired frequency in any environment condition.
The research results of Chapter 3, Chapter 4, and Chapter5 are applied to PVT sensors for micro-watt DVFS system design.
The PVT sensors micro-watt DVFS system can provides process, voltage, and temperature value, dynamically varying clock frequency and supply voltage level.
The DVFS control can reduce total energy consumption in sleep mode.
6.2 Future Work
Wireless medical microsensors are usually with two different operating modes:
Low-Power Mode and Performance Mode because the well-known signals of the main characteristics of cardiac activity, e.g. heart rate and ECG, are at a very low rate.
More than 99% operating time of sensor nodes are operating in low-power mode to record various physiological signals throughout its life time while only less than 1%
operating time in performance mode to process and transmit real-time informative
cardiovascular parameters to a host. This low-power-mode-dominated scenario is capable of further reducing total energy consumption if dynamic voltage scaling (DVS) technique is applied. The benefit of DVS technique is attributed to the quadratic savings in active CVDD2
energy. In this work, an on-chip switched capacitor(SC) DC-DC converter which can deliver desired supply voltage for each operating mode is integrated with proposed asynchronous 8T SRAM-based FIFO.
Device in low-power mode and performance mode will perform sub-threshold operation and near-threshold operation respectively.
A robust near-/sub-threshold SRAM-based FIFO for WBAN applications is shown in Fig. 6.1(a). To achieve high reliability and extend battery working time, ULV dual-port SRAM-based FIFO is applicable. The conventional dual-port SRAM fails to perform reliable subthreshold operation because of read disturb induced read static noise margin (RSNM) degradation. Plenty of subthreshold SRAMs have been implemented to overcome the degradation. However, threshold voltage shift due to random doping fluctuations and processing variation causes SRAM reliability getting worse. In addition, the reduction of signal level directly hurts the noise margin of memory. As technology scaling, the smaller Ion-Ioff-ratio limits the sharing elements like SRAM. All of the ULV effects are considered in 2Kb proposed 8T SRAM cell, shown in Fig. 6.1(b), in this work.
Besides a near-/sub-threshold memory is required, a novel switched capacitor (SC) DC-DC converter and smart dynamic voltage scaling controller are proposed. The schematic views of them are shown in Fig. 6.2(a) and Fig. 6.2(b), respectively. The SC DC-DC converter uses a pulse frequency modulation (PFM) mode of control to regulate the output voltage. When the output voltage V is above V , the switches are
generator block prevents any overlap between the Φ1 and Φ2 ON phases. The power efficiency of DC-DC converter is no less than 70% over a load current range from 10μA to 100μA. Following a request for a voltage switch (where the signal MODE changes), correct operation of the FIFO is guaranteed by sending a stall request before the actual switching of voltage. Stalling prevents processor operation during the period when the voltage supply is not completely connected. The stored data in FIFO are preserved within the internal circuits. When stalling is finished, a confirmation signal (stall_done) is transmitted back to the supply switch circuit. Finally, the stall signal is released after the new voltage supply is fully connected.
Thermal issues are fast becoming major design constraints in subthreshold systems.
Temperature variations adversely affect system reliability and prompt worst-case design. A dynamic temperature management (DTM) techniques uses to target average-case design and tack the temperature issue at runtime. A novel digital temperature sensor and dynamic temperature management mechanism are proposed.
The schematic views of them are shown in Fig. 6.3(a) and Fig. 6.3(b), respectively.
VVDD
Figure 6.1 (a) Block diagram of Near/Sub- threshold FIFO memory. (b) Proposed 8T Near/Sub-threshold SRAM cell.
Non- Overlapping
Figure 6.3 (a) Self-calibration temperature sensor with adaptive pulse width generator.
(b) DTM algorithm.
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Vita
PERSONAL INFORMATION
Birth Date: Nov. 18, 1985
Birth Place: Kaohsiung, TAIWAN.
E-Mail Address: dodolon.ee97g@nctu.edu.tw
EDUCATION
09/2008 – 07/2010 M.S. in Electronics Engineering, National Chiao Tung University Thesis: PVT-Aware Sensors for Micro-Watt DVFS System Design 09/2004 – 06/2008 B.S. in Electronical Engineering, National Tsing Hua University.
PUBLICATIONS
Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, ―Fully On-Chip Temperature, Process, and Voltage Sensors‖ in IEEE Int’l Symp. Circuits and Systems, ISCAS, Jan. 2010. (Accepted)
PATENTS
1. Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, ―Fully On-Chip Temperature, Process, and Voltage Sensors‖ US/TW Patent Pending (pending)
2. Shi-Wen Chen, Shang-Yuan Lin Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, ―Ultra-Low Voltage All-Digital Temperature Sensor With Adaptive Pulse Width Compensation‖ US/TW Patent Pending (submitted)
3. Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, ―MTCMOS Switched Capacitor DC-DC Converter with Delay Line Comparator‖ US/TW Patent Pending (submitted)