Voltage Sensor Circuit Evolution

Advanced systems (automobiles, medical and other electronic devices) have come to use multiple sensors in recent years, and the number is expected to increase even more in the future. The basic structure of the sensors includes a sensing element and electronic circuits. User requirements for sensors have become more and more demanding, including the need for high performance and lower cost.

Therefore, there are four major problems in predicting the analog type sensors of the near future. The first issue, from an economic perspective, is the difficulty of shrinkage due to loss of accuracy. The second problem involves greater sophistication of, for example, self-correction and self-diagnostics. The third issue is environmental durability. The fourth problem relates to improving reliability.

Research on digitalization of sensor circuits has become energized as efforts are made to resolve these problems. To realize digital sensing, the weak signal from the element must be analog-to-digital (A/D) converted at an early stage within the sensor chip, so an A/D converter (ADC) is required. A successive approximation ADC is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation via a binary search through all possible quantization levels before finally converging upon a digital output for each conversion.

2.2.1 Successive Approximation Analog-to-Digital Converter

The successive-approximation (SA) ADC is one of the most popular architectures for data-acquisition applications, especially when high-resolution, low power and medium speed are required. In some applications such as wireless sensor nodes, designing low power and low energy ADC is one of the major challenges. For

switching in the DAC capacitor array. Traditional successive-approximation ADC architecture is shown in Fig2.3.

The successive approximation ADC circuit typically consists of four chief subcircuits:

1. A sample and hold circuit (S/H) to acquire the input voltage (V_in).

2. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive approximation register (SAR).

3. A successive approximation register subcircuit designed to supply an approximate digital code of Vin to the internal DAC.

4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital code output of the SAR for comparison with Vin.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC which then supplies the analog equivalent of this digital code (V_ref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and do the same test, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC).

Figure 2.3 Successive Approximation ADC Block Diagram

2.2.2 All-Digital Analog-to-Digital Converter

The general schematic of all-digital ADC is shown in Fig 2.4. The multi oscillators (f₀, 2f₀, ... 2^Nf₀) are employed to be corresponding to the quantization levels (q, 2q, 2^Nq) in the conventional ADC, Fig2.5 . According to the input voltage, one of these oscillators is selected and pass through constant time pulse (T_S=l/f₀ ) to the counter.

The switching block is a combinational logic circuit as shown in Fig 2.4, which is used to pass the equivalent frequency required. The input voltage controls the selective block.

fO

2fO

2^NfO

Selective Block Vin

Swithing Block

Ts

Counter Digital Output

Figure 2.4 The general all-digital ADC.

f(Hz)

fo

2f_o 3fo

4f_o 5f_o

vo vo+q vo+2q vo+3q vo+4q vo+5q

V_in

Figure 2.5 Quantization levels of ADC.

In the last approach, the number of gates will be dramatically high. Therefore, to minimize the hardware complexity, a new circuit was presented [2.3] as shown in Fig2.6. In the circuit, the input voltage is converted to frequency (voltage controlled oscillator) using only one oscillator. This clock signal is passing through constant

the output frequency of the VCO will be less or equal f_O. (fo=l/Ts, where T, is time of conversion). Therefore, the counter will count 0's, (no positive/negative edge will be counted). At the second quantization level (2q), the frequency output must be 2fo.

Only two pulses will be memorized in the counter during the Ts pulse. The relation between the input voltage and its equivalent frequency is shown in Fig 2.5.

V

Delay Unit

Ts

Counter Digital Output

Figure 2.6 All-digital voltage to frequency converter ADC.

The digital voltage-to-time conversion technique, can be employed as controlled circuit. The basic block and timing diagram of this controlled circuit are shown in Fig2.7. The inverter steps within the gate delay pulse group are P1, P2, P3,..., which are steady states (1,0,1,...). Measurement process starts with the rise of pulse PA, then the P1, P2, P3, ... are going to invert. Due to the propagation delay time, there is an overlap between two 1's or 0's as shown in Fig 2.8. When pulse PB starts to rise, the number of inverters in which its outputs have changed due to PA is equal the

measurement time. Table 2.l illustrates the XOR gate outputs for 4-stage delay line, the 0's output logic means that position of the overlap between two l's logic. This 0's logic will be cached at Yl at level V1 of the input, at Y2 at level V2, and so on, where (V₁<V₂<V₃<V₄<V₅).

D Q

PA

PB

D Q D Q D Q D Q

V

Y1 Y2 Y3 Y4

Figure 2.7 Voltage to time conversion concept using digital circuit.

PA P1 P2 P3 P4

PB

TD

TS

Figure 2.8 Voltage to time conversion wave signals.

Table 2.1 The output of voltage-to-time conversion ADC (T

>T

>T

>T

>T

)

V

Delay Time

Output

Y

Y

Y

Y

V

V

V