Chapter 2 Previous of Process, Voltage, and Temperature sensors
2.3 Temperature Sensor Circuit Evolution
In recent years, numerous portable electronic products have been launched to the market with considerable market growth. With process scaling down continuously, this high level of integration also introduces the problem of self-heating, which is the result of increased power density. Low cost, low power, high-performance temperature sensors are therefore becoming increasingly important for applications from power consumption control to thermal monitoring, so as to enhance performance and reliability. The important applications of smart temperature sensors include:
1) The power consumption control in VLSI chips, such as CPU and chip sets.
2) The thermal compensation in single-chip systems and micro systems with built-in sensors.
3) The environment temperature monitors in automatic fabrication factories.
4) The temperature control of consumer electronics, such as automobiles and home electronics. Kim et al. [2.4] use temperature Sensor for Mobile DRAM Self-refresh Control.
2.3.1 Analog Temperature Sensor
Several different implementations of on-chip temperature sensors have been reported in the last ten years. With the use of bipolar transistors for temperature sensing, and advanced techniques including chopping circuit, dynamic element matching and sigma-delta ADC for noise suppression and cancellation, Pertijs et al.
[2.5] developed an on-chip temperature sensor with a 3σ inaccuracy of ±1℃at the expense of increased circuit complexity.
With the use of three CMOS transistors for temperature sensor was presented in [2.6]. The three-transistor temperature sensor shows in Fig. 2.9, which utilizes the
temperature characteristic of the threshold voltage, shows highly linear characteristics at a power supply voltage of 1.8 V. The conditions of this temperature sensor are defined as follows.
1) All transistors operate in the saturation region.
2) The output voltages of each node are equal.
3) The sinking currents at each node are equal.
The temperature is obtained by measuring VOUT, where the two currents, IOUT1 and IOUT2, have the same value. When the substrate bias effect of the transistor M2 is neglected to simplify the calculation, their IDS-VGS characteristics and the operating conditions are
After solving (2.16) - (2.18) for each transistor’s respective VGS, the results are applied to VGS2and VGS3 in (2.20). Then, IDS2 and IDS3 are also substituted for (2.13)&(2.14) using (2.19). Finally, (2.21) is solved against VGS1 and we get
V T
also become constant. Therefore, the output voltage corresponds to the temperature coefficients of the transistor threshold voltages.Fig. 2.10 shows the characteristics at 1.8V and 1V supply voltages, where the intersections of and correspond to the operating points of this sensor. This method shows highly linear characteristics at a power supply voltage of 1.8V or more, which enables us to define the operating conditions well above twice the threshold voltage.
But the linearity diminishes after scaling down the supply voltage to 1V using a 90-nm CMOS process. Because the temperature coefficient of the operating point’s current at a 1V supply voltage is steeper than the coefficient at a 1.8V supply voltage, the operating point’s current at high temperature becomes quite small and the output voltage goes into the subthreshold region or the cutoff region.
Figure 2.10 Operating-point comparison of three-transistor temperature sensor on IDS-VGS curves at 1.8- and 1.0-V supply voltage.
To improve linearity at a 1V supply voltage, an accurate four-transistor temperature sensor was designed in [2.7] shows in Fig. 2.11, and developed for thermal testing and
Of course, the bias voltage generation circuit must not possess temperature dependency, and, in some cases, this circuit becomes larger than the temperature sensor itself.
In addition, the W/L ratio of the transistors M0 and M1 should be as small as possible so that the current IOUT 1 remains small. However, the smaller W/L ratio requires a longer channel, so it occupies larger chip area. Consequently, there is a tradeoff between the current consumption and the chip area.
The IDS VGS characteristics and the operating conditions of both the proposed four-transistor sensor is the following:
T
I can be assumed as a constant value. Thus, (2.24) shows that the
output voltage is mainly proportional to the temperature characteristics of the threshold voltage (M2 and M3).
Figure 2.11 Four-transistor, voltage output, temperature sensor.
The output current of four- transistor temperature sensor is more high linearity with high temperature than conventional three-transistor circuit shows in Fig 2.12.
Figure 2.12 Operating points of four-transistor temperature sensor.
2.3.2 Time-to-Digital Based Temperature Sensors
In the late 20th century, analog-to-digital converters (ADCs) were gradually integrated into analog thermal sensors by IC designers to compose the so-called intelligent or smart temperature sensors. The typical block diagram of the conventional smart temperature sensor is depicted in Fig. 2.13 [2.8]. The sensor consumes more power, and large area, so another version of all-digital temperature sensor which is based on time-to-digital converters instead of ADCs was presented in [2.9]-[2.15].
Figure 2.13 Conventional digital output of temperature sensor.
Figure 2.14 Block diagram of the time-to-digital temperature sensor.
The temperature sensor composed of temperature-to-pulse generator and cyclic time-to-digital converter, shows in Fig 2.14. Temperature-to-pulse generator, it can generate a pulse width is linear to temperature variation. A simple circuit utilizing gate delays to generate the thermally sensitive pulse is shown in Fig. 2.15. The START signal is delayed a certain amount of time by the delay line composed of even number of inverter. The high-to-low and low-to-high propagation delay time for an inverter can be expressed as [2.16]
5 )
WherekN NCOX(W/L)N, kP PCOX(W/L)Pand CL are the transconductance parameters and effective load capacitance of the inverter. Note that we assume square-law behavior for the CMOS devices and thereby ignore the effects of velocity saturation. For an inverter with equivalent NMOS and PMOS, the propagation delay can be derived as As the temperature increases, the mobility (μ) and the threshold voltage (VT) will both decrease. In the case of VDD much larger than VT, the thermal effect of the propagation delay will be dominated by the mobility. That is, the thermal coefficient of the propagation delay will become positive. The major problem of the simple temperature-to-pulse generator is that the width of the output pulse at the lower bound of the measurement range is usually much larger than zero. This will cause a large DC offset at the smart temperature sensor output. The second delay line with thermal compensation for temperature sensitivity reduction is inserted in the lower transmission path of the START signal to reduce the width offset of the output pulse, which is shown in Fig. 2.16. The width offset of the output can be easily reduced by adjusting the number of delay cells in delay line 2.
Figure 2.15 Temperature-to-pulse generator.
Figure 2.16 Width offset reduction accomplished by delay line 2.
As shown in Fig. 2.17, a simple thermal compensation circuit is used to reduce the sensitivity of the inverter in delay line2. The diode connected transistors P1, N1, and P3 serve as the core of the thermal compensation circuit. Since P1, P3, and N1 are all diode connected, they will operate in saturation if bias current is flowing. Thus, we have
Figure 2.17 Delay cell is used in delay line 2.
By substituting (2.28) and (2.29) into (2.30), the equation becomes
( ) ( )
(1 ) observed for the difference between mask channel length and effective channel length.The thermal sensitivity of channel length modulation term (1VGSP3)will be neglected in the following deviations since it is much smaller than those of mobility and threshold voltage over the temperature range we are interested.
To get the minimum thermal sensitivity, let 3 0
T IDP
After simplification, we have
km
The sizes of transistors P1 and N1 are adjusted to make the gate-to-source voltage of P3 fit the requirement stated in (2.32) as closely as possible. The conduction current of transistor P3 can be found by substituting (2.32) back into (2.31) to yield
)
Whenkm2, the drain current will become totally thermal independent
)
Through the help of the current mirrors (P1, P2) and (N1, N2), the drain current of the inverter will be kept thermally insensitive as well, as will the propagation delay of delay line 2. This greatly reduces the design difficulty and enhances the tolerance to process variation.
Finally, the cyclic time-to-digital converter, shows in Fig 2.18, it convert the pulse width of temperature-to-pulse generator to digital output code.
2.3.3 Dual-DLL-Based All-Digital Temperature Sensors
With process scaling down continuously, PVT variation will be a big problem about Time-to-digital based temperature sensors. A new type DLL-based all-digital temperature sensor [2.17] was presented. It has two improvements. First, it removes the effect of process variation on inverter delays via calibration at one temperature point, thus, reducing high volume production cost. Second, we used two fine-precision DLLs, one to synthesize a set of temperature-independent delay references in a closed loop, the other as a TDC to compare temperature-dependent inverter delays to the references. The use of DLLs simplifies sensor operation and yields a high measurement bandwidth (5kS/s) at 7bit resolution, which could enable fast temperature tracking.
We execute calibration and delay normalization using the circuit of Fig. 2.19. It contains an open-loop delay line, and a DLL that synthesizes temperature-independent-delay references. This reference-DLL (R-DLL) is locked to a crystal oscillator x(t): each delay cell in the R-DLL has constant delay Δ0. MUX-1 taps a node in the R-DLL delay line: if the N-th cell’s output is tapped, the delay from input x(t) to output d(t) of the R-DLL is DDLL = NΔ0. This is our delay reference independent of temperature and process. N can be altered to produce different reference delays. In the open-loop line, if the M-th cell’s output is tapped by MUX-2, the delay between input x(t) and output c(t) is varies with temperature and process.
MUX-2 (M)
Figure 2.19 Basic architecture of DLL-based CMOS digital temperature sensor.
D Q y(t)
Figure 2.20 Calibration mode (top) and measurement mode (bottom).
In calibration mode at temperature TC, we set N = NC to fix the reference delay at DDLL = NCΔ0. We then increase M (MUX-2 setting) until DOL equals DDLL at M = MC. This comparison of DOL to DDLL to find their lock at M = MC is done via the bang-bang phase detector in the middle of Fig. 2.19. Then the MC value is corresponding to process corner.
Once 1-point calibration is complete, the sensor enters measurement mode.
Temperature T is unknown, thus, DOL of the hardwired open-loop line is an unknown delay, which the M-DLL measures by varying the reference delay DDLL of the R-DLL (bottom of Fig. 2.20). MUX-1 setting N is varied until DDLL equals DOL at N = Nm.
Nm is a digital output that faithfully represents T. Nm corresponds to the normalized delay seen earlier. Fig. 2.21 shows the implemented architecture.
MUX-2 (M)
D Q
MUX-1 (N)
y(t) FSM
x(t) Stable
clock
Open loop delay line
R-DLL
∆0
D Q
Q Control
voltage PD
Phase interpolator d(t)
Phase interpolator c(t)