A 2.17-dB NF 5-GHz-band monolithic CMOS LNA with 10-mW DC power consumption

A 2.17-dB NF 5-GHz-Band Monolithic CMOS

LNA With 10-mW DC Power Consumption

Hung-Wei Chiu, Shey-Shi Lu, Senior Member, IEEE, and Yo-Sheng Lin, Member, IEEE

Abstract—Design principles of CMOS low-noise amplifiers

(LNAs) for simultaneous input impedance and noise matching by tailoring device size for _opt = 50 are introduced. It is found that _opt close to 50 can be obtained by using small devices (110 m) and small currents (5 mA). Based on the proposed approach, CMOS LNAs with on-chip input and output matching networks on thin ( 20 m) and normal (750 m) substrates are implemented. It is found that the noise figure (NF) (3.0 dB) of the CMOS LNA at 5.2 GHz with 10-mW power consumption on the normal (750 m) substrate can be reduced to 2.17 dB after the substrate is thinned down to 20 m. The reduction of NF is attributed to the suppression of substrate loss of the on-chip inductors. The input return loss ( ₁₁) is smaller than 22 dB across the entire band of interest (5.15–5.35 GHz). An input 1-dB compression point ( _{1 dB}) of 8.3 dBm and an input third-order intercept point of 0.8 dBm were also obtained for the LNA on the thin substrate.

Index Terms—Low-noise amplifier (LNA), MOSFET amplifier,

noise figure (NF), thin substrate.

I. INTRODUCTION

H

IGH data-rate (up to 50 Mb/s) wireless local area net-works (LANs), which exploit the 300-MHz bandwidth in the 5-GHz frequency band (5.15–5.35/ 5.725–5.825 GHz) released by the Federal Communications Commission (FCC) for the unlicensed national information infrastructure (UNII) have become increasingly popular and important for mobile computing devices such as notebook computers. The allo-cated frequencies overlap the European standard for the high-performance radio local area network (HIPERLAN), which also operates in the 5-GHz band (5.15–5.35/5.47–5.725 GHz). Recently, many -band low-noise amplifiers (LNAs) have been implemented in various technologies for these LAN systems with excellent noise performance [1]–[14]. However, some of the LNAs with extremely low noise figures (NFs) were achieved at the expense of very high dc power consump-tion, and others suffered from high input/output return losses ( 10 dB), insufficient dynamic range ( dBm),

Manuscript received March 16, 2004; revised May 11, 2004. This work was supported under Grant NSC92-2212E002-091, Grant 91EC17A05-S10017, and Grant NSC93-2752-E002-002-PAE and by the United Microelectronics Com-pany (UMC) under the UMC University Program.

H.-W. Chiu was with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. He is now with the Mixed-Mode and RF Library Division, Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C.

S.-S. Lu is with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. (e-mail: sslu@ntu.edu.tw).

Y.-S. Lin is with the Department of Electrical Engineering, National Chi-Nan University, Puli, Taiwan, R.O.C. (e-mail: stephenlin@ncnu.edu.tw).

Digital Object Identifier 10.1109/TMTT.2004.842510

or low linearity [input third-order intercept point (input IP3)]. Ultra-low NF is generally not necessary in short-range wireless applications, while low power dissipation to extend the battery life is strongly demanded for portable wireless data applications [5]. Table I is a summary of recent reports on -band LNAs with low dc power consumption ( mW). From Table I, it is clear that CMOS integrated circuits, which are receiving much attention due to their potential for low cost and the prospect of system-level integration [15], must equal to or surpass the low power consumption ( mW) and low NF ( 3.0 dB) of the bipolar and GaAs circuits in order to compete with them. Besides, as previously mentioned, good input/output match, sufficient linearity, and high dynamic range are required as well. In commercial and consumer applications, the cost must also be kept low. One solution to this is the use of a foundry process with proven yield and reliability to fabricate the circuits with on-chip input/output matching networks.

Therefore, there is a need to implement an LNA, which can simultaneously balance all of the following constraints:

1) low NF ( 3.0 dB);

2) low dc power consumption ( 15 mW); 3) low input/output return losses ( 10 dB); 4) sufficient input ( 20 dBm); 5) high input IP3 ( 10 dBm); 6) low cost.

In this paper, we describe 5-GHz-band CMOS LNAs on both thin ( 20 m) and normal (750 m) substrates, which meet all the above requirements. The purpose of silicon substrate thin-ning of the LNA is to study the effect of silicon substrate thick-ness on the NF performance. The emphasis of this study is to reduce the power consumption of the CMOS LNA while still re-taining acceptable noise performance, good input/ output match, sufficient linearity, and a high dynamic range. A single-stage cascode amplifier topology with inductive degeneration at the source was used. In the course of developing such an LNA, a formula of the NF for a field-effect transistor (FET) with source and gate inductors was derived to facilitate circuit design. Based on the derived formula and the careful selection of the device size and bias, the gate inductor and source inductor, a CMOS on-chip matched LNA with a normal (750 m) substrate for 802.11a and HIPERLAN2 receivers exhibiting NFs of 2.7, 3.0, and 3.3 dB, input return losses of 27, 30, and 29 dB, output return losses of 15, 15, and 16 dB, of 8.36, 8.3, and 8.33 dBm, input IP3 of 0.3, 0.3, and 0.4 dBm with power consumptions of 12, 10 and 3.6 mW, respectively, were demon-strated experimentally (see Table I). In addition, it was found that the NF (2.17 dB) of the LNA with power consumption of 10 mW on a thin substrate (20 m) was better than that (3 dB)

TABLE I

SUMMARY OF THESTATE-OF-THE-ARTC-BANDLNAs

of the LNA on a normal substrate (750 m) [16]. The reduction of the NF of an LNA with a thin substrate is mainly due to re-duction of the substrate loss of the inductors in the LNA.

II. PRINCIPLES OFCIRCUITDESIGN

The schematic of the popular source–inductor–feedback am-plifier with the gate inductor for input impedance matching is shown in Fig. 1(a). Fig. 1(b) shows an equivalent circuit of Fig. 1(a) for noise calculation. The source inductor is used to achieve simultaneous input and noise matching [15]–[18] and to provide the desired input resistance (50 ) [19]. To thoroughly understand the effect of source inductance on the NF of an FET quantitatively, a formula of the NF for an FET with source and gate inductors was derived and is detailed as follows.

A. NF of an FET With Source and Gate Inductors

By extending the noise theory for an FET without a source inductor published by Pucel et al. [20] and referring to Fig. 1(b), we have derived the NF for an FET with source and gate inductors as follows:

(1) where is the signal source resistance (usually 50 ), and represent gate and source parasitic resistances of the FET,

Fig. 1. (a) Schematic of the popular source–inductor–feedback amplifier with an input matching gate inductor. (b) Equivalent circuit of Fig. 1(a) for noise calculation.

respectively, and stand for the series resistance of the inductors and , respectively,

, is the source impedance of the signal source, is the transconductance of the FET, is

the gate-to-source capacitance of the FET, is the Boltzmann constant, is absolute temperature, is frequency, is the induced gate noise current, and is the drain noise current. denotes “the real part of.”

and can be written as

(2) (3) where and are the coefficients of gate and drain noise, re-spectively, and are equal to and if the symbols in [21] and [22] are used, where is the coefficient of gate noise, is the coefficient of drain noise, and is the ratio of device transconductance to zero-bias drain conductance.

In fact, the expression for can be put in the following useful form by inserting (2) and (3) into (1):

(4) where , , and are defined as follows:

(5) (6)

(7) Comparing (5)–(7) with (35)–(37) derived in the Appendix, it can be seen that , , and are the functions of , , and

as follows:

(8)

(9)

(10)

is the correlation coefficient of and defined by

(11)

Theoretically, the value of is 0.395 for a long channel de-vice [21]. Since and are difficult to extract from the mea-sured results, we shall consider these functions as our fun-damental noise coefficients, which can be estimated from the measured noise parameters ( , , , and ), as will be described shortly. The expression of NF in (4) is usu-ally written in terms of minimum NF , and the optimal

source impedance or source admittance

as follows:

(12) (13) (14) where , , , and are given by (15)–(19), shown at the bottom of this page. Now, several observations are de-scribed in order here. For the time being, let us suppose that . From (18), we know that the introduction of , to a first-order approximation, does not affect , which is consis-tent with the experimental results [23]. According to (15) and (17), it is also interesting to note that is independent of

, while is reduced when is introduced; i.e., in the Smith chart should follow a constant resistance ( ) circle with decreasing reactance ( ) when increases, as shown in Fig. 2(a), which, to a first-order approximation, agrees

(15)

(16)

(17) (18)

Fig. 2. Loci ofZ andZ in the Smith chart with increasing L and L . (a) To a first-order approximation,Z follows a constant resistance circle with decreasing reactance (X ) whenL and L are increased and the loci of Z andZ intercept at some point. (b) The loci of Z andZ in the Smith chart withL , C , and L . (c) The loci of Z andZ in the Smith chart with L andL when R = 50 is required.

with the published experimental data [17]. On the other hand, the input impedance of the LNA is given by

(20) if gate-to-drain capacitance ( ) and output resistance ( ) of the FET are neglected (and, correspondingly, the

termina-tion conditermina-tion applied to the drain is immaterial). The locus of the complex conjugate of the input impedance with in-creasing is also shown in Fig. 2(a). The two loci intercept at some point, which stands for the simultaneous impedance and noise matching if and if a suitable source in-ductor is chosen. Note that, if , it is impossible

to achieve impedance matching and noise matching simultane-ously. Therefore, it is important for a circuit designer to check

whether the of the CMOS process that will be used is close to 1 or not before the source inductor feedback technique can be used for simultaneous input and noise matching. We will discuss the value of later. For the time being, if we assume , then a matching network consisting of and can be used to transform the signal source impedance (usually 50 ) into this intercept point, as shown in Fig. 2(b). For the ease of matching, one may even eliminate the need of if

is chosen to be . According to (15), it is doable to modify by a careful selection of transistor size ( ) and transconductance ( ) or bias. is then selected so that

( ) is also 50 and and are

coincident at a point on the constant 50- circle in the Smith chart. Nevertheless, from (17), it is, in general, not possible to reduce to zero by merely changing transistor parameters or by the use of . Hence, a gate inductor must be added to reduce to zero in order to achieve the minimum NF

con-dition ( ). The loci of and

cor-responding to this situation are shown in Fig. 2(c). Also note that when ( ) is reduced, is reduced as well ac-cording to (19). However, one must be cautious that

should not be too large or may become negative, and both the NF and will increase accordingly.

B. Design Procedure of the Source-Inductor-Feedback LNA

Suppose that an LNA in an RF receiver is preceded by a high-frequency bandpass filter whose output resistance is 50 ,

then . As previously mentioned, has to

be 50 and has to be zero in order to achieve the minimum NF if we want to avoid additional input matching compo-nents other than . According to (15), can be set to 50 by choosing suitable and if and are known. Sim-ilarly, can be reduced to zero by choosing suitable

if is given. , , and can be estimated from the mea-sured , , and of an FET without source and gate

inductors (i.e., ) based on the

following proposed steps. First of all, can be determined by (19). Second, can be determined by (6). Third, can be determined by (16). Finally, can be determined by (17). , , and were estimated from a test device before the design of the LNAs studied in this paper. It is found that , , and are weak functions of frequency [see Fig. 3(a)]. In addition, is 1 within an experimental uncertainty. Therefore, at least for the current CMOS process, impedance matching and noise matching can be achieved simultaneously. Besides, as shown in Fig. 3(b)–(d), the agreements between the predicted and experi-mental values of , , and are quite satisfactory for the design of LNAs.

As mentioned before, in an average modern CMOS process, whether is always close to 1 or not is crucial. From (9), is

Fig. 3. (a) ExtractedK , K , and K versus frequency characteristics of a MOSFET without source and gate inductors (i.e., L = L = R = R = 0). (b) Comparison between predicted and experimentalR . (c) Comparison between predicted and experimentalX . (d) Comparison between predicted and experimentalF .

a function of the ratio , and . Since in the short-channel regime is not currently known, we have assumed to be equal to its long channel value (i.e., 0.395), as was done in [22]. The values of versus based on (9) are plotted in Fig. 4. From this figure, it is clear that when is beyond 0.042, is a monotonically decreasing function of . Since the ratio

can be interpreted physically as the relative contribution of gate noise and drain noise to the total noise, we may say that deviates from 1 substantially if the gate noise plays an important role in a device. Some specific values of (

) may be given to get a feeling of the values of . For a long-channel FET, and (twice ) [21]. For a short-channel device, the assumptions made in [22] are adopted, i.e., continues to be approximately twice as large as and, hence, although and are taken as 1–2 and 2–4, respectively, the ratio is still a constant 2. Now is only a function of . If and were used for long-and short-channel devices [22], respectively, then the calculated ratio can be summarized as

(long channel) (short channel).

(21) From (21) and Fig. 4, the corresponding is 0.833 and 0.911 for long- and short-channel devices, respectively. Therefore, for an average modern CMOS process, should be close to 1. In addition, , , and are functions of and from (8)–(10). If is assumed to be equal to its long channel value

Fig. 4. Calculated K versus R=P characteristics of modern CMOS technologies.

(i.e., 0.395), then (the indication of the gate length) is the only parameter that most strongly affect the values of the three -parameters, i.e., process parameters highly related to gate length ( ) will most strongly affect the values of the three

-parameters.

The complete schematic of our LNA is shown in Fig. 5. A single-stage topology is chosen to minimize the power dissipa-tion and to improve input 1-dB compression point ( ) and input IP3 [15]. A cascode configuration is used to improve sta-bility and to reduce the Miller effect. The source inductor is used for simultaneous input and noise matching, while induc-tors and and capacitor are used for output matching. Fig. 6 presents a flowchart of the design procedures for finding the size and bias of the transistor. First, the current density [or gate overdrive voltage ( - )] and current

Fig. 5. Complete schematic of the LNA.

gain cutoff frequency of the transistor are set to the values corresponding to the minimum of the test device. As shown in Fig. 7, and corresponding to the minimum (1.0 dB) of the test device are 49 A m and 26 GHz, respectively. Second, check if meets the specification, which is set to 10 dB. If yes, go to the next step. If no, return to the first step, i.e., sacrifice in order to make meet the specification. It can be shown that of the LNA is given by

(22)

where is the resonant frequency of

the input/output matching networks and is the resistance seen at point D2 at the resonant frequency. Since is not known a priori, a conservative and worse case value of 50 is chosen for the initial estimate of . Third, for noise matching, is set to 50 and, from (16), the required can be de-cided. Fourth, the required is decided by and . Fifth, the driving current is decided by and . Finally, if the power consumption and linearity meet the specification, then the finding of the size and bias of the transistor is completed. Otherwise, go back to step 1 and use lower current density.

After deciding the size and bias of the transistor, the other components of the LNA can be determined as follows. The input resistance of the LNA is known to be [19] and, thus, is determined when is set to 50 . is calculated by setting (17), i.e., to zero. , , and capacitor are determined by the standard matching technique. The calcu-lated result shows that the best condition is m and mA for . The measured result shows that

is achieved when m and mA,

which not only agree with the calculated results, but also experi-mentally demonstrate that close to 50 can be obtained by using small device and small current and, therefore, the power constraint method [19], [22] is not always necessary.

III. CIRCUITIMPLEMENTATION ANDMEASUREMENTRESULTS

The LNA under study was fabricated with a standard 0.25- m mixed-signal/RF CMOS technology on a p-type

Fig. 6. Flowchart of the design procedures for finding optimized transistor’s size and bias.

substrate with substrate resistivity 20 cm provided by the commercial foundry United Microelectronics Corpo-ration (UMC), Hsinchu, Taiwan, R.O.C. The main features of the backend processes are as follows. There are five metal layers. Metal-4 (M4) and Metal-5 (M5) were used as the underpass metal layer and the top metal layer of the inductors, respectively. The top metal thickness and underpass metal thickness were 2 and 0.6 m, respectively. The oxide thick-ness between top metal and underpass metal, and the oxide thickness between underpass metal and silicon substrate were 1 and 6.2 m, respectively. No patterned ground shield was implemented below the inductors. Normal substrate thickness was approximately 750 m. Low- dielectric material was used

Fig. 7. F andf versus current density J of a test device with gatewidth 410m.

Fig. 8. Die photograph of the LNA.

as the inter-metal-dielectric (IMD) layers for high-performance mixed-signal/RF-CMOS applications.

Fig. 8 presents a die photograph of the LNA. This circuit, which occupies an area of 500 795 m , is operated with V. The substrate of the LNA was thinned down to approximately 20 m for the purpose of studying the effect of silicon substrate thickness on the NF performance of the LNA. Fig. 9 shows the detailed process flow to thin down the substrate of the LNA. First, stick the front side (the side with the LNA) of the chip (5 mm 5 mm) to the glass substrate with wax. Second, polish the back of the chip mechanically to the target thickness, i.e., 20 m, by holding the glass substrate facing down onto a rotating pad with a diamond sand paper. Third, apply photosen-sitive epoxy to the back of the chips and stick another glass sub-strate to it, followed by a 3-s UV exposure for epoxy curing and activation. Viscosity is enhanced as the exposure time increases. Fourth, soften the wax by heating so that the glass substrate on the front side of the chip can be removed. Finally, clean the chip by acetone. The thickness of the overall die plus photosensi-tive epoxy is approximately 40 m. Since a glass substrate has

Fig. 9. Detailed process flows of silicon substrate thinning.

been attached to the backside of the chip, it is easy to handle the chip. For the current small 5 mm 5 mm chip, it is found that the yield is 100% in the laboratory. It is not clear to us that if this process will be a low-cost and high-yield process in the industry. However, as technology advances, we believe that the yield of this process should also be high even for large diameter wafers used in the industry.

The noise and scattering parameters were measured on wafer using an automated NP5 measurement system from ATN Mi-crowave Inc., Palo Alto, CA. The measured characteristics of NFs versus frequency for the LNA on a normal substrate with different power consumptions are shown in Fig. 10(a). Min-imum NFs of 2.7, 2.9. and 3.3 dB were obtained at the frequency 5.2 GHz with power consumptions of 12, 7.6, and 3.6 mW, re-spectively. The frequency (5.2 GHz) where minimum NF hap-pens is denoted by . Fig. 10(b) compares the measured char-acteristics of NFs versus frequency for the LNA on both normal and thin substrates with power consumption of 10 mW. Min-imum NFs of 2.17 and 3.0 dB are obtained around the frequency GHz for the LNAs on the thin and normal sub-strates, respectively. Our results unequivocally demonstrate that low NFs and low power consumptions can be achieved simul-taneously with on-chip input and output matching networks in CMOS technology at 5-GHz band. In fact, the difference be-tween minimum and 50- NF is only 0.2 dB at 5.2 GHz, indi-cating an approximation to optimum noise matching due to the design of to the desired value of 50 ( ). From our

Fig. 10. (a) Measured characteristics of NFs versus frequency for the LNA on a normal substrate (750m) with different power consumptions. (b) Measured characteristics of NFs versus frequency for the LNA on both normal (750m) and thin (20m) substrates with 10-mW power consumption.

experimental data, we conclude that setting does not necessarily require large (device size) or large current, at least for the CMOS process we used.

Fig. 11(a) shows the measured and simulated quality factors versus frequency characteristics of a 5.5-turn testing inductor fabricated at the same time with the LNAs on both normal (750 m) and thin substrates (50 and 20 m). The track width and gap between tracks of this inductor were 8 and 2 m, respectively. The inner dimension inside the inner coil was 60 m 60 m. As can be seen, the measured maximum quality factors ( ) were 6.9, 8.5, and 11.3, respectively, for silicon substrate thicknesses of 750, 50, and 20 m. The measured self-resonance frequencies ( ) were 13.5, 14.7, and 16.7, respectively, for silicon substrate thicknesses of 750, 50, and 20 m, i.e., 63.8% (from 6.9 to 11.3) and 23.7% (from 13.5 to 16.7) performance improvements of and , re-spectively, are achieved if the silicon substrate is thinned down from 750 to 20 m. This means the silicon substrate thinning is effective in improving both the quality factor and resonant fre-quency of the inductors due to the reduction of silicon substrate loss. It is interesting to note that silicon substrate thinning can largely improve both the and of an inductor, while metal or polysilicon pattern-ground-shield (PGS) can only improve , but deteriorate of an inductor [26]. Taking the inductor with the best performance (i.e., with polysilicon PGS on a silicon substrate with resistivity cm) in [26], for example, the improvement in is only 33% (from

Fig. 11. (a) Measured and simulated quality factors versus frequency characteristics. (b) Measured minimum NFs and the inverse of maximum available power gains versus frequency characteristics of a 5.5-turn testing inductor fabricated at the same time with the LNAs on both normal (750m) and thin (50 and 20m) substrates.

5.08 to 6.76), but the deterioration in is up to 47.1% (from 6.8 to 3.6).

The measured of a 5.5-turn testing gate inductor was compared to the calculated obtained from the measured -parameters at various silicon substrate thicknesses (750, 50, and 20 m), as shown in Fig. 11(b). As can be seen, the measured conformed well to the calculated [24]. In addition, the measured at 5.4 GHz was 1.07, 0.83, and 0.52 dB, respectively, for silicon substrate thicknesses of 750, 50, and 20 m. This means the silicon substrate thinning is effective in improving of the inductors due to the reduction of silicon substrate loss. Besides, the measured -parameters of a testing MOSFET with gate length of 0.25 m fabricated at the same time with the LNAs on both normal (750 m) and thin substrates (50 and 20 m) are nearly the same, i.e., silicon substrate thinning shows no effects on the performance of MOSFETs. Based on the above results, the reason why silicon substrate thinning can improve the NF of an LNA can be explained as follows. Since the thickness of the thin substrate ( 20 m) is much smaller than the diameter of the inductor (on the order of 100 m) [26], [27] and much larger than the gate length of the MOSFETs (0.25 m), the reduction of the NF of an LNA with a thin substrate should be mainly due to the reduction of substrate loss of the inductors in the LNA. The measurement of the NFs on the 5.5-turn testing inductor shows a 0.55-dB reduction of NF

Fig. 12. Measured characteristics of input return loss (S ) versus frequency for the LNA on both normal (750m and thin (20 m) substrates with 10-mW power consumption.

(from 1.07 to 0.52 dB) after substrate thinning to 20 m [see Fig. 11(b)]. This result demonstrates the 0.83-dB reduction of the NF of the LNA (from 3.0 to 2.17 dB) is reasonable.

Fig. 12 shows the measured characteristics of versus frequency for the LNAs on both normal and thin substrates with power consumption of 10 mW. Minimum return losses of 45 dB at of 5.1 GHz (thin substrate) and 30 dB at of 5.3 GHz (normal substrate) were achieved as a result of the right choice of . The in-band (5.15 5.35 GHz) return losses were below 18 dB and 22 dB for normal and thin substrates, respectively, indicating a very good match even over the band. Note that is very close to . This is important for simultaneous input matching and noise matching. In fact, it can be shown from (4) that the frequency is given by

(23)

If and is not far from unity, (23) reduces to

(24)

Take, for example, the experimental values of the LNA on a normal substrate at power consumption of 10 mW, i.e.,

GHz and GHz, as shown in Figs. 10(b) and 12, respectively. A value of was determined, which is close to 1. The fact that approximates 1 explains why and are so close to each other. Thus, can be inter-preted physically as a measure of the separation between and . In other words, if a CMOS process does not result in a close to 1, it is almost hopeless for circuit designers to de-sign a circuit with simultaneous input impedance matching and noise matching over the narrow band of interest.

The measured transducer gain ( ) for the LNA on a normal substrate with different power consumptions is shown in Fig. 13(a). The bandpass nature of this amplifier is evident from the plot. Under the bias condition of 12 mW, the gain has

Fig. 13. Measured transducer gain (S ) versus frequency of the LNA: (a) on a normal substrate (750m) with different power consumptions and (b) on both normal (750m) and thin (20 m) substrates with 10-mW power consumption.

a peak value of 11.5 dB. For a direction conversion receiver, the load resistance is not necessarily 50 and a higher gain can be expected. For lower power consumptions, the characteristics are similar, but with lower gains of 10.4 dB at 7.6 mW and 8 dB at 3.6 mW. One figure-of-merit is the ratio of gain to dc power consumption [2]. The values of gain to dc power consumption attained by this CMOS LNA were 0.95, 1.4, and 2.2 dB/mW at three different power consumptions of 12, 7.6 and 3.6 mW, respectively. The measured and available gain for the LNA on both normal and thin substrates with power consumption of 10 mW are shown in Fig. 13(b). The available gain has peak values of 10.9 and 11.2 dB for normal and thin substrates, respectively. The values of gain to dc power consumption attained are 1.12 (thin substrate) and 1.09 (normal substrate) dB/mW. As can be seen clearly in Table I, the obtained ratios of gain to dc power consumption are comparable to the other state-of-the-art -band LNAs shown in Table I.

Microwave power performances were measured by a load–pull ATN system with automatic tuners. The measured and input IP3 data for the LNA on a thin (20 m) substrate under power consumption of 10 mW are shown in Fig. 14. As can be seen, an input of 8.3 dBm and an input IP3 of 0.3 dBm were obtained. Other measured and input IP3 data are summarized in Table I. A summary of the measured amplifier characteristics at different bias conditions is also included in Table I.

Fig. 14. Measured inputP and input IP3 for the LNA on a thin substrate (20m) with 10-mW power consumption.

IV. CONCLUSIONS

A method of designing to a desired value by the selec-tion of transistor device size and transconductance or bias is pro-posed. By setting , NFs of 2.17 and 3.0 dB, and input return losses of 45 and 30 dB at the 5-GHz band from a monolithic CMOS LNA with 10-mW dissipation on both thin ( 20 m) and normal (750 m) substrates are demonstrated with a standard 0.25- m CMOS process provided by a commer-cial foundry. The fact that is close to 1 in the CMOS process we used can achieve low NF and low input return loss simul-taneously in the narrow band of interest. In addition, substrate thinning is effective in reducing the NF. The result also unequiv-ocally demonstrates that low NFs and low power consumption can be achieved simultaneously with on-chip input and output matching networks in CMOS technology at the 5-GHz band. From both a performance and a cost perspective, these experi-mental results show that CMOS is very competitive with silicon bipolar and GaAs technologies.

APPENDIX

DERIVATION OF THE NF FOR AN FET WITH

GATE ANDSOURCEINDUCTORS

A noise analysis of the circuit shown in Fig. 1(b) quantifies the effects of the gate and source inductors. An equivalent circuit for noise calculation is depicted in Fig. 1(b). By definition the NF, can be expressed in the form

(25) where stands for the total noise current in the short-cir-cuited drain–source path originated from the noise current com-ponents , , , , , , and produced by the

noise generators from transistor gate resistance noise , se-ries resistance of gate inductor , induced gate noise current , transistor source resistance noise , series resistance of source inductor , drain noise current , and signal source resistance noise . The noise generators representing the ex-trinsic thermal sources are given by their mean square values

, , ,

, and . A careful analysis yields the following equations:

(26) (27) (28) (29) (30) (31) (32)

Inserting (26)–(32) into (25) yields

(33) Substituting

into (33), we get (34), shown at the bottom of this page. By

analogy with the results derived by Pucel et al., (34) can be put in the form of (4) if , , and are defined as follows:

(35)

(36)

(37)

and, thus, the NF of an FET with gate and source inductors are derived.

ACKNOWLEDGMENT

The authors gratefully acknowledge Dr. G. W. Huang, W. Wang,, Nano-Device Laboratory (NDL), Hsinchu, Taiwan, R.O.C., for high-frequency measurements and J. J. Yu, UMC, Hsinchu, Taiwan, R.O.C., forhelpful discussions.

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Hung-Wei Chiu was born in Taipei, Taiwan,

R.O.C., in 1976. He received the B.S. degree from National Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 1998, and the M.S. and Ph.D. degrees from National Taiwan University, Taipei, Taiwan, R.O.C., in 2000 and 2003, respectively, all in electrical engineering.

In 2004, he joined the Taiwan Semiconductor Manufacturing Company, Taiwan, R.O.C., as a Designer with the Mixed-Mode and RF Library Division. Since then, he has been involved in the area of automation of mixed-mode and RF circuit design.

Shey-Shi Lu (S’89–M’91–SM’99) was born in

Taipei, Taiwan, R.O.C., on October 12, 1962. He received the B.S. degree from National Taiwan University, Taipei, Taiwan, R.O.C., in 1985, the M.S. degree from Cornell University, Ithaca, NY, in 1988, and the Ph.D. degree from the University of Minnesota at Minneapolis–St. Paul, in 1991, all in electrical engineering. His M.S. thesis concerned the planar doped barrier hot electron transistor. His doctoral dissertation concerned the uniaxial stress effect on the AlGaAs/GaAs quantum well/barrier structures.

In August 1991, he joined the Department of Electrical Engineering, National Taiwan University, where he is currently a Professor. His current research inter-ests are in the areas of radio-frequency integrated circuits (RFICs)/monolithic microwave integrated circuits (MMICs), and micromachined RF components.

Yo-Sheng Lin (M’02) was born in Puli, Taiwan,

R.O.C., on October 10, 1969. He received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1997. His Ph.D. degree concerned the fabrication and study of GaInP/ InGaAs/GaAs doped-channel FETs and their applications on monolithic microwave integrated circuits (MMICs).

In 1997, he joined the Taiwan Semiconductor Manufacturing Company (TSMC), as a Principle Engineer for 0.35/0.32 dynamic random access memory (DRAM) and 0.25 embedded DRAM technology developments with the Integration Department of Fab-IV. Since 2000, he has been responsible for 0.18/0.15/0.13-m CMOS low-power device technology development with the Department of Device Technology and Modeling, Research and Development. In 2001, he became a Technical Manager. In August 2001, he joined the De-partment of Electrical Engineering, National Chi-Nan University, Puli, Taiwan, R.O.C., where he is currently an Associate Professor. His current research interests are in the areas of characterization and modeling of RF active and passive devices, and radio-frequency integrated circuits (RFICs)/monolithic microwave integrated circuits (MMICs).