Low temperature bonding technology for 3D integration

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Invited Paper

Low temperature bonding technology for 3D integration

Cheng-Ta Ko, Kuan-Neng Chen

⇑

Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history: Received 21 March 2011 Accepted 24 March 2011 Available online 16 April 2011

a b s t r a c t

3D integration provides a promising solution to achieve system level integration with high function den-sity, small form factor, enhanced transmission speed and low power consumption. Stacked bonding is the key technology to enable the communication between different strata of the 3D integration system. Low temperature bonding approaches are explored in industry to solve the performance degradation issue of the integrated devices. In this paper, various low temperature bonding technologies are reviewed and introduced, as well as the latest developments in world-wide companies and research institutes. The out-look for industrial application is also addressed in the paper.

1. Introduction

Three-dimensional integrated circuits (3D IC) is emerging as a leading approach to combine mixed technologies to achieve high density integration with small form factor, high performance, low power consumption, and being a promising solution to over-come the limitations of Moore’s law. To attain 3D integration struc-ture, several key technologies have to be perfectly mastered, such as vertical interconnection by through silicon via (TSV), wafer thin-ning and handling, and wafer/chip stacked bonding (including chip-to-chip (C2C), chip-to-wafer (C2W) and wafer-to-wafer (W2W) bonding schemes). Among them, stacked bonding enables the communication between different strata of the 3D integration system. Conventional Cu–Cu thermo-compression is a popular bonding approach because it provides intrinsic interconnect and excellent bonding strength. However, high bonding pressure and temperature up to 350–400 °C are always required to perform the bonding integrity. These tough conditions may result in the bond-alignment deviation, high thermal stress, and possible dam-ages to the bonded devices. It has been veriﬁed such high temper-ature could degrade the performance of DRAMs and other advanced devices[1].

Consequently, it is essential to explore alternative methods to alleviate bonding temperature and/or pressure to meet the requirement of low thermal budget and sensitive chips such as CIS, MEMS, LED and Bio application devices. In addition, low tem-perature bonding approaches are looked into the industry with great beneﬁts to overcome issues related to (a) cracks of thinned and fragile wafer during bonding, (b) performance degradation un-der higher bonding temperature (>260 °C), (c) serious wafer/chip warpage and bonding misalignment, and (d) compatibility with

the back-end-of-line process conditions and materials. In this pa-per, various low temperature bonding technologies, which could be performed under 250 °C, are reviewed in combination with the latest developments in corresponding companies or research institutes.Table 1summarizes various low temperature bonding approaches, including innovative direct bonding, surface activated bonding (SAB), adhesive bonding, eutectic bonding, and emerging nanometal bonding technologies. Each technique will be intro-duced in detail, including its advantages and disadvantages, in the following sections.

2. Direct bonding

Wafer direct bonding uses the spontaneous adhesion of two wafers placed in direct contact under room temperature with short bonding time. It can offer high via density, good alignment, high bonding strength with stress free, and hermetic sealed bonding structures. In conventional direct bonding processes, the initial intimate contact bonds, mostly Si-to-Si and SiO2-to-SiO2, rely on

the van der Waals attractive force between two extremely flat and clean surfaces. However, the subsequent high temperature annealing above 700–1000 °C is required to let the contact inter-face improve to strong covalent bonds (Si–O–Si) to ensure the bond strength and eliminate voids. In addition, the requirements of bonding environment and flat surface are very significant (root mean square (RMS) roughness lower than 0.5 nm) to perform the bonding integrity. These tough conditions are the drawbacks to limit its application. Therefore, surface treatments by wet chemical and/or dry plasma activation are developed to lower the annealing temperature to 200–400 °C or even unnecessary. These approaches can permit looser surface condition (RMS roughness up to 2 nm can still be bonded), and reduce the bonding environment limita-tion such as from ultrahigh vacuum to even the ambient air condition.

⇑Corresponding author.

E-mail address:[email protected](K.-N. Chen).

Contents lists available atScienceDirect

Microelectronics Reliability

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Ziptronix provides a direct oxide bonding technology, named ZiBond™[2], being completed at room temperature with no resid-ual stresses. It employs NH4OH exposure to terminate oxide

sur-face with amine groups, and followed by direct sursur-face contact to form covalent bonds spontaneously. The Ziptronix’s DBI (Direct Bonding Interconnect) technology [3–5] is an evolution of ZiBond™, which utilizes the standard chemical–mechanical polish (CMP) technique to expose metal patterns embedded in the silicon oxide surface of each chip or wafer, thus enabling silicon and other technologies to be bonded and interconnected in a 3D fashion. Fig. 1shows the process flow of DBI bonding technology[5]. Pat-terned metal contact structures are formed on target wafers. Sili-con oxide is then deposited to cover the Sili-contact structures and wafer surface. CMP is used to planarize the wafer surface and ex-pose the metal contacts. To perform ZiBond, the wafers are oxide-activated first, placed together with the metal contacts op-posed, and finally room-temperature direct oxide bonded with preserved alignment accuracy since no external heat and pressure applied. After bonding, 300–350 °C annealing is employed to im-prove the inter-wafer bond strength and the metal–metal contact quality. With the planarized surface and high bonding alignment accuracy, DBI can provide fine interconnect pitch bonding.Fig. 2 demonstrates 3

l

m-pitch bonded structures, allowing an intercon-nection density larger than 10 M/cm2_{using DBI technology}_[5]_.

LETI and STMicroelectronics developed direct hydrophilic Cu– Cu bonding at room temperature, atmospheric pressure, and ambi-ent air[6–8]. This approach requires good hydrophily, low RMS roughness (<0.5 nm) and surfaces with free particle contamination to ensure hydrophilic direct bonding. By means of CMP, the RMS roughness and hydrophily of Cu ﬁlm are improved from 15 nm to 0.4 nm and from 50° to 12°, respectively. Blanket wafers were successfully bonded at room temperature with a bonding strength

Fig. 1. DBI technology process ﬂow[5].

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of 2.8 J/m2_{. Bond strength was improved to 3.2 J/m}2_{after a}

post-bonding annealing at 100 °C for 30 min[6–8].Fig. 3demonstrates the cross section of bonding interface before and after annealing treatment. With a 30 min annealing at 400 °C, the interface turns wavy due to copper interdiffusion and grain growth. The appropri-ate surface preparation and the optimization of bonding process

also allow an efﬁcient conductivity through the bonding interface and a very low contact resistivity could be obtained. The speciﬁc contact resistance is 22.5 mX

l

m2 _{and 140 m}

X

l

m2 _{for 400 °C}

and 200 °C annealing, respectively. In addition, the thinning of the bonded pair down to 10

l

m without delamination on the top surface conﬁrms the high quality of the bonding. Although direct

Fig. 3. The cross section of direct copper bonding interface before (left) and after (right) 400 °C annealing treatment[7].

Fig. 4. The schematic ﬂow of surface activated bonding[10].

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copper bonding provides a promising solution for high density stacking with TSV process integration, a post bonding anneal is still required.

3. Surface activated bonding (SAB)

When the conventional direct bonding approach requires high temperature annealing which may result in thermal stress and generation of defects, surface activated bonding (SAB) provides strong bonding strength at room temperature without any anneal-ing steps[9,10].Fig. 4shows the schematic ﬂow of SAB technology [10]. Surface to be bonded is sputter-etched by ion or fast atom beam (e.g. Ar–FAB) to remove contaminant layers and absorbed molecules, and brought into contact at room temperature in ul-tra-high vacuum. When two wafers are mated and contacted in a small area, the contact area propagates spontaneously by surface attractive force between the wafers. Because the surface atoms have dangling bonds after etching and are in unstable state ener-getically, atoms from two surfaces can be bonded with strong chemical bonds under room temperature and pressure-free condi-tions. Tensile test results show that high bonding strength equiva-lent to bulk material is achieved at room temperature[9]. Without any heat treatment and applying pressure, SAB provides low-dam-age assembly and packaging processes suitable for delicate micro-structures.

The University of Tokyo has successfully performed Si–Si, Au– Au, and Cu–Cu wafer bonding by SAB technology at room temper-ature without annealing[9–14]. The bonding energy (>1.95 J/m2₎

and strength (>12 MPa) have been achieved.Fig. 5presents that the bumpless interconnect of 6

l

m pitch Cu electrodes is realized at room temperature with SAB method[14]. The alignment accu-racy better than ±1

l

m is obtained and the Cu surface with 2 nm roughness can be well-bonded with bond strength greater than 20 MPa. However, the whole bonding process has to be carried out under an ultrahigh vacuum condition (<10 5_{Pa) that makes}

these processes expensive for mass production. Therefore, they further developed Si–Si room temperature bonding using ﬂuo-rine-containing plasma activation[15,16], which can be performed in ambient air without any annealing and chemical cleaning treat-ment. This becomes an attractive wafer bonding option because of its low stress, damage, and process cost. Possible bonding mecha-nism, optimized bonding parameters, and bonding strength inves-tigations have been reported in these publications[9–14].

Fig. 6. The process ﬂow of WOW stacking method[21].

Fig. 7. Seven wafers stacked on a wafer with BCB bonding and TSV interconnection

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4. Adhesive bonding

Adhesive bonding is a low temperature and patternable tech-nique using an intermediate layer for bonding. In 3D integration

scheme, adhesive material can be used for wafer-to-wafer bonding followed by fabrication of TSV on proper position to form vertical interconnection between stacked wafers. The advantages include low bonding temperature (ranging from R.T. to 350 °C depends

Fig. 8. The illustration of Cu–Sn solid–liquid interdiffusion bonding[26].

Fig. 9. The integration of 2lm TSV and Cu–Sn SLID interconnection between stacked chips[26].

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group has lots of choices with different bonding temperature and characteristics[17–19]. Nowadays SU-8 and BCB (benzocyclobu-tene) are the most popular adhesives for precision 3D adhesive bonding below 250 °C with outstanding wafer bonding capability, chemical and thermal resistance, bonding strength, and wide acceptance in IC manufacturing environments.

Wafer-on-wafer (WOW) technology development has used BCB adhesive bonding followed by low temperature TSV fabrication [20–23].Fig. 6illustrates the process ﬂow of WOW stacking meth-od[21]. The secondary wafer (Si 2) with transistors and intercon-nect metallization fabricated is temporarily bonded with support glass, and thinned down to 20

l

m. This wafer is then permanently bonded to the primary wafer (Si 1) with BCB adhesive. After removing the support glass from the wafer stack, TSV and RDL are subsequently fabricated by Cu dual-damascene processes. In their scheme, 10

l

m TSV with 25

l

m depth (20

l

m Si + 5

l

m BCB) was designed to facilitate TSV fabrication, and 150 °C LT– TSV was developed to lower whole process temperature and in-duced stress. By repeating the bonding and TSV processes, a mul-ti-stacked integrated circuit can be fabricated. They have successfully demonstrated seven thinned wafers stacking with BCB bonding and Cu–TSV interconnection as the image shown in Fig. 7 [20].

5. Eutectic bonding

Metal eutectic bonding is a popular bonding technique used in advanced MEMS packaging and 3D integration technologies. By performing wafer bonding with two different metals under their eutectic points, the low temperature bonding can be achieved. Be-cause eutectic alloys at the interface are formed in a liquid phase, eutectic bonding facilitates surface planarization and provides a tolerance of surface topography and particles. In addition, there are no requirements on the ultrahigh vacuum bonding condition and post-bond annealing treatment. However, compared with the ultraﬁne pitch capacity of direct bonding technique, the intercon-nect pitch is limited by bump-to-bump fabrication. The commonly used eutectic bonding schemes (with the corresponding bond tem-perature) include Al–Si (600 °C), Au–Si (380–400 °C), Au–Sn (300 °C), Au–In (275 °C), Cu–Sn (250–270 °C), Pb–Sn (190°), In–Sn (120 °C), etc. Although Sn–Pb is a mature and low temper-ature bonding method, it is not preferred due to the lead-free ten-dency on all electronic products. Au and In are noble metal materials, and the complete consumption of In to transfer to inter-metallic compound (IMC) is required to prevent joint remelting due to its low melting point (156.6 °C). Therefore, Cu–Sn eutectic bonding has become a popular low temperature bonding approach for 3D integration.

Inﬁneon and IZM implemented face-to-face chip integration by Cu–Sn solid–liquid interdiffusion (SLID) bonding[24–26]. The SLID principle is to sandwich low-melting component (e.g. Sn) in be-tween two high-melting components (e.g. Cu), and melt the low-melting component at a constant temperature until the completely

IMEC developed high throughput die-to-wafer bonding by so-called collective transient liquid phase (TLP) bonding process as shown in Fig. 10 [27]. It adopts Cu–Sn for metallic interconnect in combination with no-flow underfill as the bonding adhesive. The TSV-dies are pick-and-placed onto a landing wafer with the tacky no-flow underfill has been previously coated, which can weakly bond the dies to prevent from moving. This operation is performed at room temperature with the pick-and-place process repeated until the full wafer is populated. The fully populated wa-fer is then moved to a wawa-fer bonder where pressure and heat are applied to all stacked dies at once. The collective TLP bonding is performed at 250 °C with underfill reflows and the metallic inter-connect forms between all stacked dies simultaneously. Fig. 11 demonstrates the optical image of a collectively bonded wafer, where 50

l

m TSV die bonded to corresponding landing wafer using Cu–Sn TLP bonding method[27].

ITRI and NCTU developed carrier-less 3D integration platform, shown in Fig. 12, by wafer-level micro-bump/adhesive hybrid bonding technology[28]. Cu–Sn micro-bump for metallic intercon-nect and BCB polymer as dielectric adhesive are adopted for hybrid bonding at 250 °C. The photo-deﬁnable BCB is spin-coated and pat-terned on both TSV-wafer with Cu–Sn bumps and base wafer with Cu pads to obtain the hybrid schemes. Two wafers are then aligned

Fig. 11. Optical image of a collectively bonded wafer, where 50lm TSV die bonded to corresponding landing wafer using Cu–Sn TLP bonding method[27].

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and bonded to form solder joint interconnect with BCB adhesive sealed bonding to increase the bond strength and joint reliability. With the adhesive serving reinforcement of the mechanical stabil-ity, the bonded TSV-wafer can endure the severe wafer thinning process to expose the TSV, and implementation of the backside RDL processes with the base wafer support. If required, a third wa-fer (or more) can be further added to achieve multi-layer 3D struc-tures[28].

6. Nanometal bonding

The general metal diffusion bonding, such as Cu–Cu and Au–Au bonding, provides intrinsic interconnect and excellent mechanical strength. However, the bonding temperature higher than 300 °C and high bonding pressure are required to perform the bonding integrity. Recently the nanometal materials are studied to lower the bonding temperature and pressure. RPI developed low temper-ature wafer bonding by Cu nanorod array[29–31]. They observed that surface melting disintegration of the nanorod arrays occurred at a temperature signiﬁcantly below the Cu bulk melting point. Base on this unique property, they performed wafer bonding using Cu nanorod arrays as a bonding intermediate layer at temperatures

ranging from 200 °C to 400 °C.Fig. 13shows the schematic illustra-tion of the Cu nanorod bonding[31]. The wafers are coated with a vast array of Cu nanorods with a diameter of 10–20 nm grown by an oblique angle deposition technique. Subsequently the two wa-fers are bonded at an external pressure of 0.32 MPa to facilitate the formation of nano-structured bonds at the interface. The FIB/ SEM results show that the Cu nanorod arrays fused together accompanying by grain growth at a bonding temperature as low as 200 °C. A dense Cu bonding layer with homogeneous structure was obtained upon 400 °C as the image shown inFig. 14 [29].

IZM developed another low temperature bonding approach by nanoporous Au bump interconnect[32]. Nanoporous gold bumps were deposited on silicon wafers by electroplating silver–gold al-loy followed by etching silver to provide a nanoporous gold layer as an open-porous sponge with 70–80% porosity. The porous inter-connects provide advantages, such as compressibility to compen-sate for any coplanarity and particle issues, and reduced stiffness results in potentially higher bond yield and extended reliability. Nanoporous gold bumps were bonded each other and investigated the microstructure revolution at different bonding temperatures. As the results shown inFig. 15, the nanoporous structure was den-siﬁed with temperature increasing from 150 °C to 400 °C, which turned the brown bump color into yellow[32].

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Fig. 13. The schematic illustration of copper nanorod bonding[31].

Fig. 14. (A) SEM image of as-deposited copper nanorod arrays and cross-sectional FIB/SEM images of copper nanorod bonding at (B) 200 °C, (C) 300 °C and (D) 400 °C respectively[29].

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7. Outlook

Various low temperature bonding technologies have been ad-dressed and compared in this paper. Considering the application for mass production, DBI and copper direct bonding with oxide hermetic sealing are good alternatives. Both methods have not only the excellent capacity for fine pitch and high density integration but also the constitutional advantage on the flow separation of short contact bonding and batch annealing treatment, which is suitable for high throughput production without bottlenecks. In addition, they provide the gate-level truly 3D integration with the significant benefits of size reduction, increased system perfor-mance, low power consumption, and reduced production costs. However, it is expected the annealing temperature could be further lowered to meet the requirements of low thermal budget and sen-sitive devices. SAB technique is another candidate if the high requirements of bonding environment could be improved. As aforementioned, room temperature bonding performed in ambient air has been successfully demonstrated using specific plasma acti-vation. It will become an attractive bonding approach with low stress, damage and production cost. Furthermore, low temperature hybrid bonding by eutectic bumps and adhesive sealing provides another potential solution for 3D integration. From the back-end process and packaging point of view, it is a simplified and low cost bonding approach with high mechanical strength and reliability, and will be also suitable for future industrial applications.

8. Conclusions

This review paper summarizes various low temperature bond-ing technologies for 3D integration, includbond-ing the research and development efforts from corresponding companies or research institutes. Direct bonding enables bonding at room temperature with very ﬁne interconnect pitches, but extremely ﬂat surface and post-bond annealing treatment are required to guarantee the bonding performance. SAB technology provides room temperature direct bonding without the requirement of post-bond annealing, but the severe bonding environment is a drawback for industrial application. Adhesive bonding has better particle contamination tolerance, but TSV formation after bonding limits via aspect ratio and density. Eutectic bonding and nanometal bonding for direct

interconnection can be performed at low temperature. However, the un-bonded air-gap area may result in reliability issues, which is recommended to be improved by hybrid bonding approach. Sev-eral potential technologies, including innovative direct bonding such as DBI and copper direct bond, SAB with speciﬁc plasma acti-vation, and low temperature hybrid bonding by eutectic bump and adhesive sealing, are good candidates with signiﬁcant advantages on low damage to device, high throughput and low production costs for mass production applications.

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