Low-frequency noise characteristics of hot carrier-stressed buried-channel pMOSFETs

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LOW-FREQUENCY NOISE CHARACTERISTICS OF HOT

CARRIER-STRESSED BURIED-CHANNEL PMOSFETs

SHENG-LYANG JANG1_{, HENG-KUEN CHEN}1 _{and KOW-MING CHANG}2 1_{Department of Electronic Engineering, National Taiwan Institute of Technology, 43 Keelung Road,}

Section 4, Taipei 106, Taiwan, R.O.C.

2_{Institute of Electronics, National Chiao Tung University, Hsin-Chu 300, Taiwan, R.O.C.}

(Received 17 June 1997; in revised form 2 August 1997; accepted 5 August 1997)

AbstractÐPrestress and poststress low-frequency noise characteristics of buried-channel LDD pMOS-FETs have been studied. The devices were stressed at low gate and high drain bias, and the poststress drain current increases due to the hot-electron induced channel shortening eect. The noise measure-ments were carried out between 10 Hz and 100 kHz, 1/f1.2_{and generation±recombination current noises}

have been found in the drain current noises. The poststress 1/f1.2_{drain current noise increases in both}

1. INTRODUCTION

MOSFETs are ®nding more and more important applications in the area of analog integrated cir-cuits. The capability of integrating low-noise analog circuits and high-speed digital circuits on the same chip is crucial to the production of a wide range of high-performance MOS integrated circuits such as A/D converters, memories and telecommunication circuits. The use of buried-channel (BC) MOSFETs results in improved performance both in digital and analog circuits. This is due to several properties such as lower excess noise in low frequencies, lower gate capacitance, and higher channel mobility com-pared to a standard MOS transistor. A BC MOSFET is usually realized by implanting the channel region of a MOS transistor, with impurities of opposite type to the substrate doping. When BC MOSFETs are operated with the conducting chan-nel away from the Si±SiO2interface, the 1/f noise is

greatly reduced. Since minority carrier transport now occurs aways from the interface, the charge ¯uctuation in interface states and consequently 1/f (or more generally 1/fr_{) noise may be reduced[1,2].}

In this mode of operation, not only a thermal noise but other low level noise sources are revealed[3]. The bulk channel MOSFET has a 1/f noise Hooge parameter a among the lowest values ever reported in the literature for silicon MOSFETs[4]. Furthermore a is two order of magnitude lower than that of a surface channel device. Experimental analyses have yielded evidence of at least an order of magnitude improvement of noise performance in the ion implanted nMOSFETs over standard sur-face channel MOSFETs of equivalent geometry.

It has been recognized that hot-carrier reliability in submicron p-MOSFETs can also impose as

severe constraints as in nMOSFETs. It was found by several authors such as Wang et al.[5] that the degradation of the linear drain current of pMOSFETs proceeds logarithmically in time. They attributed their observation to the trapping of elec-trons in gate oxide layers. It was reported by Tsudiya et al.[6] that interface states generated by the hot hole injection also contribute to the degra-dation of quarter-micrometer pMOSFETs. Woltjer et al.[7] also observed generation of the interface states during the hot carrier stress of LDD pMOSFETs by the charge pumping method. Pan[8] reported that the degradation of the LDD satur-ation drain current proceeds logarithmically in stress time while the linear current gradually satu-rates. The hot-electron-induced-punchthrough (HEIP) eect[9,10] is most signi®cant in pMOSFETs because of their buried channel nature, which makes them more vulnerable to drain induced barrier lowering (DIBL) and consequently source±drain punchthrough. Two approaches may be useful to mitigate the HEIP eect: ®rst, the eec-tive channel length may be increased by using shal-low source/drain diusion, and secondly hot electron generation may be minimized by reducing the channel electric ®eld. These two approaches are satis®ed simultaneously by employing an LDD (lightly doped drain) structure.

Up to now no hot-carrier stress eect on the low-frequency noise performance of BC LDD pMOSFETs has been reported in literature, and beacuse the BC MOSFET has the lower 1/f noise of various MOSFETs, therefore in this paper we study the hot-carrier-stressed low-frequency noise per-formance of these devices.

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2. EXPERIMENTAL DETAILS AND DISCUSSION In this section we describe the low-frequency noise performance of fresh and poststressed nor-mally-o buried-channel LDD pMOSFETs. The devices were mounted on a probe station, and were shielded in a metal box to avoid external interfer-ence. The DUTs were biased in series with a metal-®lm resistor, the noise across the devices were feed-back to a low-noise ampli®er and the spectrum ana-lyzer was used to measure the noise spectrum output from the ampli®er. The noise measurements were carried out between 10 and 100 KHz at room temperature.

Figure 1 shows the schematic of a damaged pMOSFET, the channel is divided into two regions, one is the undamaged region near the source and the rest is the damaged region. For pMOSFETs, the electron gate current at low VGS is larger than

the hole gate current at high VGS, hence the

hot-electrons can be trapped in the gate oxide, attract the holes to the semiconductor surface, and cause channel shortening, which increases the poststress drain current. Figure 2 shows the fresh and posts-tress current±voltage characteristics of a pMOSFET. The devices used in this study were buried-channel LDD pMOSFETs, the gate-oxide thickness is tox=9 nm, the gate length is

L = 0.60 mm. The transistor was stressed under maximun hot-electron injection conditions: vVDSv = 7 V, vVGSv = 1.2 V and stress

time = 23000 s.

Figure 3(a) and (b) are two typical fresh drain current noise spectral densities. Figure 4(a) and (b) are the poststress drain current noise spectral den-sities. These ®gures show that the noises consist of 1/f1.2 _{and generation±recombination (G±R) noises.}

G±R noise is easily distinguishable from the ¯icker noise component, with the G±R power spectrum having a Lorentzian shape with pleateau and steep 1/f2 _{regions. G±R noise shows up in the measured}

current noise spectrum as the trap energy level crosses the quasi-Fermi level. It results from the carrier transitions between the conduction/valence band and the trap energy levels. The transition is a thermal activated process[9]. We have found we can use Equation (1) to extract the noise components in all regions of operation

Fig. 1. Schematic diagram of a stressed LDD MOSFET.

Fig. 2. Measured fresh and poststress I±V characteristics of a p-type buried-channel LDD MOSFET with W = 10.0 mm, L = 0.60 mm and tox=9 nm.

S.-L. Jang et al. 412

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Fig. 4. Measured poststress drain current spectral densities of a p-channel LDD MOSFET. S.-L. Jang et al.

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SIDS f C1

f 1:2

g1

1 f =ft2 Cx- 1

where ft is the roll-o frequency. C1, g1and Cxare

®tting constants.

Figure 5 shows the ®tting fresh and poststress results of a device under the same bias condition. It indicates that the poststress noise current consists of a pure 1/f1.2 _{noise and a white noise, the ®tting}

parameters are C1=3.0 10ÿ18, and

C=2.2 10ÿ23, which were measured at

VGS= ÿ 2.0 V and VDS= ÿ 0.8 V. In the fresh

noise curve we found an additional G±R noise com-ponent, the ®tting parameters are C1=1.15 10ÿ18,

g1=6.0 10ÿ22, ft=1000 Hz, and C=2.2 10ÿ23.

Because the poststress 1/f1.2_{current noise increases,}

we can not see the original G±R noise of the fresh device in the poststress noise spectrum. The calcu-lated relative current noise SIDS/IDS2 also increases after stress. Similarly we can obtain the values of parameters at other bias. The bias VGSchanges the

level of the quasi-Fermi potential, hence the magni-tude of G±R noise increases with VGS, then

decreases as shown in Fig. 3(b) and Fig. 4(b). Figure 6(a) is a comparision of the fresh and poststress drain current noise spectral densities with a pronounced G±R noise spectrum with ft=500 Hz.

This indicates that this G±R center is not aected by the stressing. This can be further supported by the results shown in Fig. 6(b), the extracted fresh

and poststress ft associated with VGS= ÿ 2.5 V

have a similar VDS-dependence. The G±R center

may locate in the oxide near the interface as in the interpretation of random telegraph signals (RTSs) in small MOSFETs[11], it is a localized G±R center. A channel electron can be captured into the border trap. The G±R noise may be due to random emis-sion of electrons and holes at the defect centers in the depletion regions[12]. The information is not sucient at this stage to identify the location of this G±R center due to the lack of analytical buried-channel noise model. As the device is turned on, the semiconductor surface is in accumulation condition, the variation of VGS will change the band bending

of the oxide and the trap energy level and aect the generation±recombination rate. In our device, in above-threshold, the conduction-band edge at the interface lies near the quasi-Fermi level, the depleted bands in the bulk semiconductor are screened by the surface accumulation layer and shift by much less. The G±R noise may be due to a border trap. Figure 6(b) also shows the VDS

-depen-dence of ft for the fresh and the poststress device

biased at VGS= ÿ 1.5 V. The extracted fresh ft

remains constant as the device is operated in the saturation mode, it indicates this trap is uniformly distributed along the channel, as VDS increases the

location for the trap with trap energy crossing the quasi-Fermi level also moves toward the source. However the extracted poststress ftbecomes smaller

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Fig. 6. (a) Comparision of the fresh and poststress drain current noise spectral densities with a pro-nounced G±R noise spectrum with ft=500 Hz. (b) The VDS-dependence of ft for the fresh and the

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as the device is operated in the saturation mode and as VDS increases. This indicates the

stress-gen-erated traps are nouniformly distributed along the channel and possibly these traps are dierent in their trap energies.

Figure 7 is a comparision of the fresh and posts-tress 1/f1.2 _{current noise spectral densities. The}

stressing increases the nonuniform distribution of interface states which directly aect the bias-depen-dent 1/f1.2 _{noise, however the hot-carrier induced}

negative oxide charges increase the drain current, these two mechanisms interact to produce the results as shown in this ®gure. Generally traps are distributed over space inside the oxide as well as in energy over the bandgap. The 1/fg_-frequency

dependence instead of 1/f can be explained by a nonuniform spatial distribution of traps in the oxide[13]. For a trap distribution that increases away from the interface, there are a great number of low-frequency traps leading to g>1.

The 1/f noise in the drain current of nMOSFETs has been extensively studied for many years. Although it is generally agreed that the current ¯uc-tuations are due to trapping/detrapping of channel carriers, the exact origins and nature of the traps are still subjects of debate. In view of the fact that high-frequency RTS's have been found to arise from interface traps[14], and the 1/f noise is believed to be a superposition of numerous RTS's, it would be surprising if the 1/f noise was indeed

not aected by the density of interface states Dit.

Todsen et al.[15] presented the results of linear region 1/f noise and Dit measurements performed

on pMOS transistors subjected to high electric ®eld stressing of the gate oxide. High electric ®eld imposed across the oxide allows electrons to tunnel through the oxide via Fowler±Nordheim (FN) tun-nelling. These tunnelling electrons create additional traps in the oxide. For the pMOS transistors stu-died, the 1/f noise increases during the high ®eld stressing. By plotting the 1/f noise as a function of Dit, a direct relationship between the increase in

these two parameters is observed. It is believed that the low-gate hot-carrier stress in this work plays the role to increase the trapped oxide charges and gen-erate interface states. This results in an increase of poststress 1/f1.2_{current noise.}

3. CONCLUSION

In this paper we have carried out detailed exper-imental study on the low-frequency noises of fresh and poststress buried-channel LDD pMOSFETs. The devices were stressed at low gate bias, and the hot-electron-induced channel shortening is respon-sible for the increase of the poststress drain current. Generation±recombination and 1/f1.2 _noise

com-ponents have been found in the drain current noise for the devices operated both in the linear and sat-uration regions. From the bias-dependence of the

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roll-o frequecy of G±R noise we found G±R cen-ters are spatially uniformly distributed along the channel for the fresh device, however new genera-tion±recombination centers have been generated after the stressing, these newly-generated G±R cen-ters are possibly nonuniformly distributed in energy and space, and they aect the noise-performance of poststress MOSFETs. The increase in 1/f1.2_current

noise after stress is due to the stress-induced chan-nel shortening and interface states.

AcknowledgementsÐThis work is supported by the National Science Council, Taiwan, under Contract NSC 86-2215-E-011-004.

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