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The Impact of MOSFET Layout Dependent Stress on High Frequency Characteristics and Flicker Noise

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The Impact of MOSFET Layout Dependent Stress on High

Frequency Characteristics and Flicker Noise

Kuo-Liang Yeh, Chih-You Ku, and Jyh-Chyurn Guo

Institute of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan

Tel: +886-3-5131368, Fax: +886-3-5724361, E-mail: jcguo@mail.nctu.edu.tw

Abstract —Layout dependent stress in 90 nm MOSFET and

its impact on high frequency performance and flicker noise has been investigated. Donut MOSFETs were created to eliminate the transverse stress from shallow trench isolation (STI). Both NMOS and PMOS can benefit from the donut layout in terms of higher effective mobility Peff and cutoff frequency fT, as well as lower flicker noise. The measured flicker noise follows number fluctuation model for NMOS and mobility fluctuation model for PMOS, respectively. The reduction of flicker noise suggests the reduction of STI generated traps and the suppression of mobility fluctuation due to eliminated transverse stress using donut structure.

Index Terms — Donut, Shallow-Trench Isolation (STI),

Stress, Mobility, Flicker noise

I. INTRODUCTION

With the advancement of CMOS technology to nanoscale regime, the stress introduced from materials and process become more sensitive to the device layout and topography. The shallow trench isolation (STI) process will induce compressive stress and traps, which may have impact on flicker noise (i.e., 1/f noise) in NMOS and PMOS devices. [1] Layout-dependent stress from STI and its impact on high frequency characteristics as well as flicker noise has been investigated but limited to NMOS [2]-[3]. A minor layout modification, namely edge-extended was implemented to reduce the stress and traps introduced by STI [2]. However, the edge-extended layout cannot eliminate the gate-to-STI edge overlap region and leaves STI stress an impact factor. A ring type device was proposed, trying to solve the mentioned problem and identify the influence on flicker noise [3]. However, the study is limited to the stress along the gate width, i.e. transverse to the channel (transverse stress VЗ) and the impact on high frequency performance is unknown. Furthermore, both studies of edge-extended and ring type layouts did not cover PMOS, which is even more important than NMOS for low phase noise design.

In this paper, a new MOSFET layout, namely doughnut (donut) is proposed to create devices free from transverse STI stress, along the gate width.. Meanwhile, an extensive investigation is performed on both NMOS and PMOS devices to explore the STI stress effect on channel current, cutoff frequency (fT) and flicker noise. For each

device structure under a specified bias, the flicker noise is averaged from several different dies to represent statistics of die-to-die variation. This work is aimed to identify the impact from STI stress on high frequency characteristics as well as flicker noise and the results can guide MOSFET layout optimization for RF and analog circuit design.

II. DEVICE FABRICATION AND CHARACTERIZATION

In this work, the devices were fabricated in 90nm CMOS process, with 90nm gate length drawn on the layout Ldrawn and the total gate width Wtot fixed at 64Pm. In

order to investigate the stress and interface traps generated near STI edge, two types of MOSFET layouts, namely standard and donut are designed and implemented. Standard device means multi-finger structure with finger width WF=2Pm and finger number N=32. As shown in Fig.

1, donut MOSFETs are constructed as 4-side polygons in which the corners contribute very little to the channel current [4]. In this work, donut devices with two layout dimensions are implemented. In Fig. 1(a), D1S1 represents donut MOSFET in which the space from poly gate to STI edge follows the minimum rule, i.e. 0.3Pm, to maximize the compressive stress from STI and along the channel (i.e., longitudinal stress V//). Meanwhile, D10S10 shown in Fig.

1(b) denotes donut MOSFET with 10 times larger space between poly gate and STI edge, i.e. 3Pm, intentionally to relax V// from STI.

3um

D10S10

POLY

OD

0.3um

D1S1

(a)

(b)

Fig. 1 A brief layout of donut MOSFET (a) D1S1 and (b) D10S10, with two major layers, such as active region (OD) and poly gate (PO)

978-1-4244-6241-4/978-1-4244-6242-1/

978-1-4244-6243-8/10/$26.00 © 2010 IEEE 2010 IEEE Radio Frequency Integrated Circuits Symposium

RTUIF-21

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S-parameters were measured by Agilent E8364B network analyzer for high frequency characterization and AC parameters extraction. Open and short deembedding was performed to remove the parasitic capacitances from the pads as well as interconnection lines and the resistances from all of the metal interconnect. The power spectral density (PSD) of drain current noise, namely SID

was measured by low frequency noise (LFN) measurement system, consisting of Agilent dynamic signal analyzer (DSA 35670) and low noise amplifier (LNA SR570). The LFN measurement generally covers a wide frequency range from 4Hz to 10k Hz. The LFN was measured under various gate-over-drive (|VGT|=0.1~0.7V) and |VDS|=50mV

for both NMOS and PMOS.

III. RESULTS AND DISCUSSION

At first, STI stress introduced in MOSFETs with three different layouts as mentioned (standard, donut D1S1 and D10S10) is illustrated in Fig.2 to assist an analysis and understanding of layout effect on STI stress and then the electrical characteristics. Note that STI stress is classified as longitudinal stress, denoted as V// , which is in parallel

with the channel, and transverse stress, namely VЗ , which is transverse to the channel. We can see that standard MOSFETs (Fig.2(a)) are subject to V// along the channel

length and VЗ along the gate width. On the other, donut MOSFETs are free from VЗ. Regarding the stress favorable for mobility enhancement, it has a critical dependence on the device types and orientations, as shown in Table I [5]. For NMOS, tensile stress, either V// or VЗ can improve Peff.

As for PMOS, compressive stress in V// or tensile stress in

VЗ is the right one for Peff enhancement.

(b) Donut D1S1 (a) Standard W2N32 (c) Donut D10S10 V// V// V// V// V// V// VЗ VЗ

Fig. 2 Schematics of STI stress in MOSFETs with three

different layouts (a) standard multi-finger device W2N32 (b) donut device D1S1 (c) donut device D10S10. Longitudinal stress : V// in parallel with the channel, transverse stress : VЗ transverse to the channel.

TABLE I

Stress favorable for mobility enhancement in NMOS and PMOS along longitudinal and transverse directions [5]

Directions

NMOS PMOS

Longitudinal (V//) Tensile Compressive

Transverse () Tensile Tensile

Stress favorable for mobility enhancement

A. DC Performance of Standard and Donut NMOS Fig.3(a) presents the maximum transconductance Gm,max measured from NMOS. It is found that Gm,max of

D1S1 is degraded by around 9.7% but that of D10S10 is enhanced by 7.5% as compared with the standard device. The experimental suggests the compressive V// from STI,

which is maximized in D1S1 due to the minimum gate to STI space is the primary factor responsible for Gm,max

degradation. As for D10S10, the much lowerV// due to 10

times larger space and eliminated VЗ for donut layout contributes to Gm,max improvement. The influence on

effective mobility Peff shown in Fig. 3(b) reveals exactly

the same trend. D1S1 suffers 9.2% degradation while D10S10 gain 7.45% enhancement in Peff. The results

justify the mechanism that the layout dependence of Gm,max

is originated from the effect of STI stress V// and VЗ on electron mobility summarized in Table I.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 100 150 200 Peff ʻ cm 2/V -s ʼ NMOS, Vd=50mV Std W2N32 Donut D1S1 Donut D10s10 VGT (V) (b) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 2 4 6 8 10 Gm (mA/ V ) VGT (V) NMOS , Vd=50mV Std W2N32 Donut D1S1 Donut D10S10 (a)

Fig. 3 (a) The transconductance Gm and (b) effective mobility Peff

and extracted from linear I-V for standard and donut NMOS with different poly-gate to STI edge distances, D1S1 and D10S10 defined in Fig.1.

B. DC Performance of Standard and Donut PMOS As for PMOS, the donut devices D1S1 and D10S10 demonstrate 12.2% and 7.6% higher Gm,max than the

standard one shown in Fig.4(a). Again, the layout dependence of Peff illustrated in Fig.4(b) indicates the same

trend as that of Gm,max. The donut PMOS, D1S1 and

D10S10 present 12.5% and 6.3% Peff enhancement

compared to the standard device. According to Table I, it is believed that D1S1 with the min. gate to STI edge distance, resulting the highest compressive V// and minimized VЗ can benefit the most in hole mobility. The standard PMOS with relieved V// in multi-finger structure and largest VЗ along narrow width suffers the worst hole mobility.

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0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2.0 2.5 3.0 Gm ʻ mA /V ʼ |VGT| (V) PMOS , Vd=-50mV Std W2N32 Donut D1S1 Donut D10S10 (a) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 35 40 45 50 55 Peff ʻ cm 2/V-s ʼ |VGT| (V) PMOS, Vd= -50mV Standard W2N32 Donut W64_D1S1 Donut W64_D10s10 (b)

Fig. 4 (a) The transconductance Gm and (b) effective mobility

Peff and extracted from linear I-V for standard and donut PMOS

with different poly-gate to STI edge distances, D1S1 and D10S10 defined in Fig.1

C. High Frequency Performance of Donut and Standard MOSFETs

The impact from layout dependent STI stress on high frequency performance is of special concern for RF MOSFETs and circuits design. Fig. 5(a) and (b) illustrate the cutoff frequency fT measured from NMOS and PMOS

with donut and standard layouts. Note that fT is extracted

from the extrapolation of |H21| to unity gain. For NMOS in

Fig.5(a), D10S10 gains 5% improvement in the maximum fT compared to the standard and D1S1. The benefit from

donut layout becomes particularly larger for PMOS. As shown in Fig.5(b), D1S1 presents the best performance with the highest fT and realizes 28% increase in the

maximum fT than the standard device.

0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 20 40 60 80 100 120 NMOS, VDS=1.2V (a) Standard W2N32 Donut D1S1 Donut D10s10 fT @H 21 (G H z) VGS (V) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 10 20 30 40 50 60 PMOS, VDS=-1.2V fT @H 21 (GHz) (b) Standard W2N32 Donut D1S1 Donut D10s10 |VGS| (V)

Fig. 5 The cut-off frequency fT vs. Vgs measured for standard and

donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

The resulted improvement on fT in donut MOSFETs

can be consistently explained by the enhancement of Peff

and Gm. Referring to (1), an analytical model for

calculating fT [6], it is predicted that fT is proportional to

Gm and the enhancement of Gm can boost fT under fixed

gate capacitances (Cgg and Cgd). Fig.6(a) and (b) present

Cgg measured from NMOS and PMOS with three different

layouts. The results indicate much smaller difference in Cgg

between donut and standard layouts, as compared with Gm

(Fig.3 and Fig.4). Thus, layout dependence of fT just

follows that of Gm. 2 2 (1) 2 m T gg gd G f C C S  0.4 0.6 0.8 1.0 1.2 50 60 70 80NMOS, Vds=1.2V (a) Std W2N32 Donut D1S1 Donut D10S10 Cgg (f F) VGS (V) 0.4 0.6 0.8 1.0 1.250 60 70 80 PMOS, Vds= -1.2V Cgg (f F) (b) Std W2N32 Donut D1S1 Donut D10S10 |VGS| (V)

Fig. 6 Cgg vs. Vgs extracted from Y-parameters for standard and

donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

Regarding other RF performance parameters, such as maximum oscillation frequency, fmax and noise figure,

NFmin (not shown), the donut MOSFETs suffer significant

degradation due to inherently larger gate resistances than the standard one with multiple gate fingers. The experimental suggests an innovative donut device layout is required to cover all of the RF and analog performance. D. Low Frequency Noise of Standard and Donut

MOSFETs

Fig. 7(a) and (b) make a comparison of LFN in terms of SID/ID2 between the standard and donut devices for

NMOS and PMOS, respectively. The noise spectrum follows 1/f characteristics over a wide frequency domain from 4 to 10K Hz. It means that the measured LFN is a typical flicker noise. The standard device reveals near twice larger SID/ID2 as compared to donut devices for both

NMOS and PMOS, under a specified gate overdrive voltage, |VGT|=0.7V. In contrast, the donut device D10S10

with the most extended gate to STI-edge distance indicates the lowest SID/ID2. The results can be consistently

explained by the fact that D10S10 can keep free from VЗ as well as interface traps near STI edge, and the smallest V// due to 10 times larger space away from the STI edge

compared to D1S1. 101 102 103 10-14 10-13 10-12 10-11 10-10 10-9 D1S1 f -1 D10S10 Standard NMOS VDS=50mV, VGT=0.7V (a) SID /I 2 DS (1 /Hz) Frequency (Hz) 101 102 10310 -13 10-12 10-11 10-10 10-9 D1S1 D10S10 Standard (b) SID /I 2 DS (1 /Hz) PMOS VDS=-50mV VGT=-0.7V Frequency (Hz) f -1

Fig. 7 The low frequency noise SID/IDS2 measured for the standard

and donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

To further explore the mechanism responsible for LFN, the measured SID/IDS2 at frequency 50Hz are plotted versus

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IDS for three different devices, under various |VGT|

(0.1~0.7V) shown in Fig.8 (a) and b) for NMOS and PMOS, respectively. For nMOS devices, the measured LFN characteristic is dominated by number fluctuation model given by (2) in which SID/IDS2 is proportional to

Nt/IDS2 and that predicts the increase of LFN with

increasing the traps density Nt [7]. It is believed that the

gate to STI-edge overlap region will suffer the most severe compressive strain as well as interface traps Nt, and the

donut devices can eliminate these effects along the gate width, i.e. in the transverse direction. According to previous study, the stress generated traps may aggravate the scattering effect and increase the flicker noise [8]. The mentioned mechanism can explain why the donut devices free from gate to STI-edge overlap region can have the lowest LFN. 2 2 2 2 3 1 (2)2 : -B t ox eff DS ID DS DS t q k T N WC V S I f L I

N the density of traps at quasi Fermi level

J

O P

As for PMOS shown in Fig.8(b), the measured SID/IDS2

follows a simple power law of 1/IDS and manifests itself

governed by mobility fluctuation model, according to Hooge empirical formula expressed in (3) [9]. Note that the Hooge parameter DH is dimensionless and may vary

with biases and process technologies. The reduction of LFN measured from donut PMOS suggests the suppression of mobility fluctuation due to the eliminated compressive VЗ. 2 2 1 (3) : H eff DS ID DS DS H qV S I f L I

the Hooge parameter

D P D 10-4 10-3 10-2 10-12 10-11 10-10 (a) VDS= 50mV, VGT=0.1, 0.3, 0.5, 0.7V NMOS Standard D1S1 D10S10 SID /IDS 2 (1/Hz )

Drain Current IDS (A)

1/I2DS 10-4 10-3 10-2 10 -12 10-11 10-10 (b) VDS= -50mV, VGT= -0.1,-0.3,-0.5,-0.7V PMOS Standard D1S1 D10S10 SID /IDS 2 ( 1 /H z)

Drain Current IDS (A)

1/IDS

Fig. 8 SID/IDS2 vs. IDS under varying |VGT| (0.1~0.7V) for

standard and donut devices (a) NMOS (b) PMOS. Standard : multi-finger W2N32. Donut : D1S1 and D10S10.

IV. CONCLUSION

The proposed donut MOSFETs demonstrate the advantages over the standard MOSFETs, such as the lowest SID/IDS2 in low frequency domain (1~ 10K Hz) and

higher fT in very high frequency region (100/50 GHz for

N/P MOS). The elimination of STI stress and excess traps

along the gate width is validated as the primary mechanism responsible for the enhancement of Peff as well as fT, and

reduction of LFN. The layout dependent stress mechanism can be applied to both NMOS and PMOS, even though their LFN are governed by different models. An innovative donut device layout for solving the potential degradation of fmax and NFmin emerges as an interesting and important

topic in the future work for RF and analog applications.

ACKNOWLEDGEMENT

This work is supported by NSC98-2221-E009-166-MY3. Besides, the authors acknowledge the support from NDL RF Lab. for noise measurement and Chip Implementation Center (CiC) for device fabrication.

REFERENCES

[1] T. Ohguro, Y. Okayama, K. Matsuzawa, K. Matsunaga, N. Aoki, K. Kojima, H. S. Momose, and K. Ishimaru, “The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11Pm CMOS”, in Symp. on VLSI

Tech., 2003, pp. 37–38.

[2] C.-Y. Chan, Y.-S. Lin, Y.-C. Huang, S. S. H. Hsu, and Y.-Z. Juang, “Edge-extended Design for Improved Flicker Noise Characteristics in 0.13-Pm RF NMOS”, in IEEE MTT-S Intl.

Microwave Symp. 3-8 June, 2007, pp.441-444.

[3] Y.-L. R. Lu, Y.-C. Liao, W. McMahon, Y-H. Lee, Helen Kung, R. Fastow, and S. Ma, “The Role of Shallow Trench Isolation on Channel Width Noise Scaling for Narrow Width CMOS and Flash Cells”, in Int. Symp. on VLSI TSA, 21-23 April, 2008, pp. 85–86.

[4] P. L’opez, M. Oberst, H. Neubauer, D. Cabello and J. Hauer, “Performance analysis of high-speed MOS transistors with different layout styles”, IEEE Int. Symposium on Circuits and Systems, Kobe, Japan, 23-25 May, 2005.

[5] Y. Luo and D. K. Nayak, “Enhancement of CMOS performance by process-induced stress” IEEE Trans. Semicond. Manuf., vol. 18, no. 1, pp. 63–68, Feb. 2005. [6] Tajinder Manku, “Microwave CMOS—Device Physics and

Design”, IEEE Journal of Solid-State Circuits, vol. 34, no. 1, Mar. 1999, pp. 277-285.

[7] G. Reimbold, “Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion-influence of interface states,” IEEE Trans. Electron Devices, vol. ED-31, pp. 1190-1198, 1984.

[8] S. Maeda, Y. S. Jin, J. A. Choi, S. Y. Oh, H. W. Lee, J. Y. Woo, M. C. Sun, J. H. Ku, K. Lee, S. G. Bae, S. G. kang, J. H. Yang, Y. W. Kim, K. P. Suh, “ Impact of Mechanical Stress Engineering on Flicker Noise Characteristics,” in

Symp. on VLSI Tech., June 2004, pp.102-103.

[9] F. N. Hooge, et al., “Lattice scattering causes 1/f noise,” Phys. Lett. A, vol. 66, pp. 315-316, 1978.

數據

Fig. 1 A brief layout of donut MOSFET (a) D1S1 and (b) D10S10,  with two major layers, such as active region (OD) and poly gate (PO)
Fig. 3 (a) The transconductance G m  and (b) effective mobility  P eff
Fig. 7 The low frequency noise S ID /I DS 2  measured for the standard

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