Introductory Invited Paper
Overview on ESD protection design for mixed-voltage I/O interfaces
with high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology
q
Ming-Dou Ker
*, Wei-Jen Chang
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC
Received 2 March 2006; received in revised form 15 March 2006 Available online 9 June 2006
Abstract
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-system-on-a-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.
2006 Elsevier Ltd. All rights reserved.
1. Introduction
With the scaled-down device dimension in advanced CMOS technology, the power supply voltage is also scaled down to reduce the power consumption and to meet the gate-oxide reliability. However, most microelectronic sys-tems nowadays consist of mixed semiconductor chips fabri-cated in different CMOS technologies, where the interfaces between semiconductor chips or sub-systems have different internal power supply voltages. For example, a 3.3 V I/O interface is generally required by the ICs realized in CMOS processes with the internal power-supply voltage of 2.5 V or 1.8 V. The traditional CMOS I/O buffer with VDDof 2.5 V
is shown in Fig. 1(a) with both output and input stages. When an external 3.3 V signal is applied to the I/O pad, the channel of the output PMOS (Mp_out) and the parasitic
drain-to-well junction diode in the Mp_outcause the leakage
current paths from the I/O pad to VDD, as the dashed lines
shown inFig. 1(a). Moreover, the gate oxides of the output NMOS (Mn_out), the gate-grounded NMOS (Mn1) for input
electrostatic discharge (ESD) protection, and the input inverter stage are over stressed by the 3.3 V input signal to suffer the gate-oxide reliability issue[1].
To avoid the leakage current paths from I/O pad to VDD, the gate tracking circuit and the n-well self-biased
cir-cuit are designed to ensure that the pull-up PMOS (Mp_mix)
will not conduct the leakage current. To solve the gate-oxide reliability issue without using the additional thick gate-oxide process, the stacked-MOS configuration has been widely used in the mixed-voltage I/O circuits [2–4]. The typical 2.5 V/3.3 V tolerant mixed-voltage I/O circuit is shown inFig. 1(b)[2]. With a high-voltage input signal at the pad (e.g. 3.3 V in a 2.5 V/3.3 V mixed-voltage I/O interface), the common node between the Mn_top and
Mn_botin the stacked-NMOS structure has approximately
a voltage level of VDD Vth (1.9 V), where Vth
(0.6 V) is the threshold voltage of NMOS device. There-fore, the independent control on the top and bottom gates 0026-2714/$ - see front matter 2006 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2006.03.012 q
An earlier version of this paper was published in the Proceedings of the 2005 International Conference on Electron Devices and Solid-State Circuits (EDSSC 2005), Hong Kong, 19–21 December 2005, pp. 493–498.
*
Corresponding author. Tel.: +886 3 5131573; fax: +886 3 5715412. E-mail address:mdker@ieee.org(M.-D. Ker).
of the stacked-NMOS allows the devices to be operated within the safe range for both dielectric and hot-carrier reli-ability limitations during normal circuit operation. In such mixed-voltage I/O circuits, the on-chip ESD protection cir-cuits will meet more design constraints and difficulty.
In this paper, an overview on ESD protection designs for mixed-voltage I/O interface circuits without using the additional thick gate-oxide process is presented. The con-tent covers the ESD design constraints in mixed-voltage I/O circuits, the classification, and analysis of the ESD pro-tection designs for mixed-voltage I/O circuits. Especially, the ESD protection designs for mixed-voltage I/O inter-faces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.
2. ESD design constraints in mixed-voltage I/O circuits ESD stresses on an I/O pad have four pin-combination modes: positive-to-VSS (PS-mode), negative-to-VSS
(NS-mode), positive-to-VDD (PD-mode), and negative-to-VDD
(ND-mode) stresses. The ESD protection design of I/O pad cooperating with power-rail ESD clamp circuit is shown inFig. 2(a), where a PS-mode ESD pulse is applied to the I/O pad. ESD current at the I/O pad under the PS-mode ESD stress can be discharged through the parasitic diode of PMOS from I/O pad to VDD, and then through
the VDD-to-VSS ESD clamp circuit to ground. The
tradi-tional I/O circuits cooperating with the VDD-to-VSS ESD
clamp circuit can achieve a much higher ESD level [5]. But, due to the leakage current issue in the mixed-voltage I/O circuits, there is no diode connected from the I/O pad to VDDpower line. The ESD current at mixed-voltage
I/O pad under PS-mode ESD stress cannot be discharged from the I/O pad to VDD power line, and cannot be
dis-charged through the additional VDD-to-VSS ESD clamp
circuit. Therefore, the power-rail ESD clamp circuit did not help to pull up ESD level of the mixed-voltage I/O pad under the PS-mode ESD stress. Such ESD current at the mixed-voltage I/O pad is mainly discharged through the stacked-NMOS by snapback breakdown, as illustrated inFig. 2(b). However, the NMOS in stacked configuration has a higher trigger voltage and a higher snapback holding voltage, but a lower secondary breakdown current (It2), as
compared to that of the single NMOS [6,7]. Therefore, such mixed-voltage I/O circuits with stacked-NMOS often have a lower ESD level under PS-mode ESD stress, as com-pared to the traditional I/O circuits with a single NMOS [6]. In addition, without the diode connected from the I/ O pad to VDD, the mixed-voltage I/O circuit also has
I/O Pad VGp= 2.5V VGn= 0V To internal circuits 0V 3.3V 2.5V Gate-oxide Reliability Gate-oxide Reliability Mp_out Mn_out Mn1 (a) I/O Pad VDD (2.5V) VDD (2.5V) VDD (2.5V) VSS (0V) VSS (0V) Pre-Dr iver Pre-Dr iver VGp VGn To internal circuits VDD (2.5V) VSS (0V) VSS (0V) 0V 3.3V 2.5V R Vin_high = ~ (VDD-Vtn) VDD VDD N-well Self-Biased Circuit Stacked NMOS Vin_high = (VDD-Vtn) Gate Tracking Circuit Mp_mix Mn_top Mn_bot (b)
Fig. 1. Typical circuit diagrams for (a) the traditional CMOS I/O buffer, and (b) the mixed-voltage I/O circuits with the stacked-NMOS and the n-well self-biased PMOS.
I/O Pad VDD VSS Pre-Driver Po w e r-Ra il ES D Clam p Ci rc u it VESD GND IESD IESD (a) I/O Pad VDD VSS P re -D ri ver VDD N-well Self-Biased Circuit Gate Tracking Circuit Stacked NMOS Pow e r-Ra il ESD Cl amp Circ uit GND VESD IESD (b)
Fig. 2. The ESD current paths of (a) the traditional I/O pad with power-rail ESD clamp circuit, and (b) the mixed-voltage I/O pad with power-power-rail ESD clamp circuit, under the PS-mode ESD stress.
a lower ESD level for I/O pad under PD-mode ESD stress.
Although the ESD robustness of stacked-NMOS device can be somewhat improved by layout optimization, the stacked-NMOS device by snapback breakdown still cannot provide efficient ESD protection in the mixed-voltage I/O circuits. By using extra process modification such as ESD implantation [8], the ESD robustness of stacked-NMOS device can be further improved [9], but the process com-plexity and fabrication cost are increased. Therefore, effec-tive ESD protection design without increasing process complexity is strongly requested by the mixed-voltage I/O circuits in the scaled-down CMOS processes.
3. ESD protection designs for mixed-voltage I/O circuits 3.1. Substrate-triggered stacked-NMOS device
The snapback operation of the parasitic n–p–n BJT in the stacked-NMOS structure can be controlled by its sub-strate potential. The subsub-strate-triggered technique [10] can be used to generate the substrate current (Isub) in
ESD protection circuits. With the substrate-triggered cur-rent (Itrig), the trigger voltage of the stacked-NMOS device
in mixed-voltage I/O circuits can be reduced for more effec-tive ESD protection.
The finger-type layout pattern and the corresponding cross-sectional view of the substrate-triggered stacked-NMOS device are shown inFig. 3(a) and (b), respectively. As shown in the layout top view, an additional p+ diffusion is inserted into the center drain region of stacked-NMOS device as the substrate-triggered node. The trigger current is provided by the substrate-triggered circuit. An n-well structure is further diffused under the source region, which is also surrounding the whole device, to form a higher equivalent substrate resistance (Rsub) for improving
turn-on efficiency of the parasitic lateral BJT in the stacked-NMOS device. The substrate-triggered circuit should be designed to avoid electrical overstress on the gate oxide and to prevent the undesired leakage current paths during normal circuit operating condition. During ESD stress con-dition, the substrate-triggered circuit should generate large enough trigger current to effectively improve the turn-on efficiency of parasitic n–p–n BJT in stacked-NMOS device. The substrate-triggered circuit I for stacked-NMOS device in the mixed-voltage I/O circuits is shown in Fig. 4 [11]. The substrate-triggered circuit I is composed of the diode string, a PMOS Mp1, and an NMOS Mn1, to
provide the substrate current for triggering on the parasitic n–p–n BJT in the stacked-NMOS device during ESD stress. Under normal circuit operating condition, the turn-on voltage of the substrate-triggered circuit roughly equals to Vpad=Vstring(I) +jVtpj + VDD, where Vstring(I)
is the total voltage drop across the diodes and Vtp is the
threshold voltage of the PMOS. To satisfy the requirement in the 2.5 V/3.3 V mixed-voltage application, the number of the diodes in the diode string should be adjusted to make
the turn-on voltage greater than 3.3 V. When a 3.3 V input voltage is applied at I/O pad, Mp1is kept off, and the local
substrate of the stacked NMOS is biased at VSS by the
turned-on Mn1. With the diode string to block the 3.3 V
input voltage at the I/O pad, the Mp1with thin gate oxide
Fig. 3. (a) Finger-type layout pattern, and (b) the corresponding cross-sectional view, of the substrate-triggered stacked-NMOS device for mixed-voltage I/O circuits.
Substrate-Triggered Circuit I Internal Circuit s Internal Circuits Stacked-NMOS Pull-up PMOS Gate Tracking Circuit N-Well Self-Biased Circuit VSS VDD Pad I/O VDD Rsub Lateral n-p-n BJT c VDD D1 D2 Dm Mp1 Mn1 Diode String
Fig. 4. Schematic circuit diagram of the substrate-triggered stacked-NMOS device with substrate-triggered circuit I for the mixed-voltage I/O circuits.
has no gate-oxide reliability issue under normal circuit operating condition. The Mp1 in conjunction with the
diode string is used to reduce the leakage current through the substrate-triggered circuit in normal operating condi-tion. If a lower input leakage is desired, the numbers of the diodes in the diode string should be increased. Under PS-mode ESD stress condition, the gate of the Mp1 has
an initial voltage level of 0 V, while the VSS pin is
grounded but the VDD pin is floating. The
substrate-trig-gered circuit will provide the trigger current flowing through the diode string and the Mp1into the p-substrate,
when Vpad=Vstring(I) +jVtpj. The trigger current provided
by the substrate-triggered circuit is determined by the diode string and the size of Mp1. Once the parasitic n–p–n BJT in
the stacked-NMOS device is triggered on, the ESD current will be discharged from the I/O pad to VSS.
Another substrate-triggered circuit II for stacked-NMOS device in the mixed-voltage I/O circuits is shown inFig. 5 [12]. The substrate-triggered circuit II is composed of the PMOS Mp1, PMOS Mp2, NMOS Mn1, and NMOS
Mn2, to provide the substrate current for triggering on the
parasitic n–p–n BJT in the stacked-NMOS device during ESD stress. In the 2.5 V/3.3 V mixed-voltage IC applica-tion, the gates of Mp1and Mp2are biased at 2.5 V VDD
sup-ply through a resistor Rd under normal circuit operating
condition. When the input voltage transfers from 0 V to 3.3 V at the I/O pad, the gate voltage of Mn1 could be
increased through the coupling capacitor C. However, the Mn2and Mp2can clamp the gate voltage of Mn1 between
VDD Vtnand VDD+jVtpj, where Vtnis the threshold
volt-age of NMOS. Once the gate voltvolt-age of Mn1 is over
VDD+jVtpj, the Mp2will turn on to discharge the
over-cou-pled voltage and to keep the gate voltage within VDD+jVtpj. Since the upper boundary on the gate voltage
of Mn1is within VDD+jVtpj, the source voltage of Mp1is
clamping below VDD, which keeps the Mp1always off under
normal circuit operation condition. The Mn2and Mp2can
further clamp the gate voltage of Mn1to avoid gate-oxide
reliability issue in the substrate-triggered circuit, even if the I/O pad has a high input voltage level. Under PS-mode ESD-stress condition, the gates of Mp1and Mp2have an
ini-tial voltage level of0 V, while the VSSpin is grounded but
the VDDpin is floating. The positive ESD transient voltage
on the I/O pad is coupled through the capacitor C to the gate of Mn1. In this situation, both of the Mn1 and Mp1
are operated in the turned-on state. Therefore, the sub-strate-triggered circuit II will conduct some ESD current flowing from I/O pad through Mn1and Mp1into the
p-sub-strate. The trigger current provided by the substrate-trig-gered circuit II is determined by the size of Mn1, Mp1, and
the capacitor C. Once the parasitic n–p–n BJT in the stacked-NMOS device is triggered on, the ESD current can be mainly discharged from the I/O pad to VSS.
Both two substrate-triggered designs can significantly reduce the trigger voltage and ensure effective ESD protec-tion for the mixed-voltage I/O circuits. By using such sub-strate-triggered designs, the gates of stacked-NMOS in the mixed-voltage I/O circuits can be fully controlled by the pre-driver of I/O circuits without conflict to the ESD pro-tection circuits. The main ESD discharge device is the par-asitic n–p–n BJT in the stacked-NMOS device. Therefore, the ESD robustness of mixed-voltage I/O circuits can be effectively improved without occupying extra silicon area to realize the additional stand-alone ESD protection device into the mixed-voltage I/O cells.
3.2. Extra ESD device between I/O pad and VSS
To improve ESD level of the mixed-voltage I/O circuits, the extra ESD device was added between I/O pad and VSS
power line. The ESD protection design, by using the addi-tional stacked-NMOS triggered silicon controlled rectifier (SNTSCR) [13], has been reported to protect the mixed-voltage I/O circuits. The ESD protection design with the additional SNTSCR device for protecting the mixed-volt-age I/O circuits is shown inFig. 6(a). The device structure of SNTSCR and the corresponding ESD detection circuit are shown inFig. 6(b). The ESD detection circuit, designed by using the gate-coupled technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate bias to trigger on the SNTSCR device under ESD stress condition. On the contrary, this ESD detection cir-cuit must keep the SNTSCR off when the IC is under nor-mal circuit operating condition. During nornor-mal circuit operating condition, the Mn3inFig. 6(b) acts as a resistor
to bias the gate voltage (Vg1) of Mn1at VDD. But, the gate
of Mn2is grounded through the resistor R2 and Mn4. So, all
the devices in the ESD protection circuit can meet the elec-trical-field constraint of gate-oxide reliability under normal circuit operating condition. Under PS-mode ESD stress condition, the Mp1is turned on but Mn3is off since the
ini-tial voltage level on the floating VDD line is 0 V. The
capacitors C1 and C2 are designed to couple ESD transient voltage from the I/O pad to the gates of Mn1 and Mn2,
Substrate-Triggered Circuit II Internal Circuit s Internal Circuits Stacked-NMOS Pull-up PMOS Gate Tracking Circuit N-Well Self-Biased Circuit VSS VDD Pad I/O VDD Rsub Lateral n-p-n BJT VDD Mp1 VDD Mn1 C Mp2 Rd Rt Mn2
Fig. 5. Schematic circuit diagram of the substrate-triggered stacked-NMOS device with substrate-triggered circuit II for the mixed-voltage I/O circuits.
respectively. The coupled voltage should be designed greater than the threshold voltage of NMOS to turn on Mn1and Mn2for triggering on the SNTSCR device, before
the devices in the mixed-voltage I/O circuit are damaged by ESD stress. With the gate-coupled circuit technique, the trigger voltage of SNTSCR can be significantly reduced, so the SNTSCR can be quickly triggered on to discharge ESD current. From the experimental results in a 0.35 lm CMOS process, the HBM ESD level of the mixed-voltage I/O circuits with this ESD protection design has been greatly improved up to 8 kV, as compared with that (2 kV) of the original mixed-voltage I/O circuits with only stacked NMOS device.
3.3. Extra ESD device between I/O pad and VDD
Because the diode in forward-biased condition can sus-tain much higher ESD current, the diode string has been
used for protecting the mixed-voltage I/O circuits [14]. The ESD protection design with the diode string connected between the I/O pad and VDD power line for the
mixed-voltage I/O circuits is shown in Fig. 7. The ESD current at the I/O pad under PS-mode ESD stress can be dis-charged through the diode string to VDD power line, and
then through the power-rail ESD clamp circuit to the grounded VSS. The ESD current at the I/O pad under the
PD-mode ESD stress can be directly discharged through the diode string to the grounded VDD.
The number of diodes in the diode string is determined by the voltage difference between the maximum input volt-age at I/O pad and the VDDsupply voltage. To reduce the
turn-on resistance from I/O pad to VDDduring ESD stress,
the area of such diodes has to be scaled up by the number of the diodes in stacked configuration. The major concern of using the diode string for ESD protection in volt-age I/O circuits is the leakvolt-age current. While the mixed-voltage I/O circuit is operating at a high-temperature envi-ronment with a high-voltage input signal, the forward-biased leakage current from the I/O pad to VDD through
the stacked diodes could trigger on the parasitic vertical p–n–p BJT devices in the diode string. The Darlington bipolar amplification of these parasitic p–n–p BJT devices in the diode string will induce a large leakage current into the substrate. InFig. 7, an additional snubber diode (SD) was used to reduce the leakage current due to the Darling-ton bipolar amplification in the diode string [14].
4. ESD protection designs with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits
The ESD protection scheme by using the additional ESD bus for the IC with power-down-mode application has been reported in [15]. Such design concept with ESD bus can be used to form the ESD protection network for the mixed-voltage I/O circuits, as shown in Fig. 8. The additional ESD bus line is realized by a wide metal line
Internal Circuit s Internal Circuits Stacked-NMOS Pull-up PMOS Gate Tracking Circuit N-Well Self-Biased Circuit VSS VDD Pad I/O VDD D1 D2 Dm Dn SD Power-R ail
ESD Clamp Circuit
Fig. 7. ESD protection design with the diode string connected between the I/O pad and VDDpower line to protect the mixed-voltage I/O circuits.
SN TS C R Internal Circuit s Internal Circuits Stacked-NMOS Pull-up PMOS Gate Tracking Circuit N-Well Self-Biased Circuit VSS VDD Pad I/O VDD Mn1 P+ N-Well P-Sub N+ Mn2 Vg1 ES D Detect io n Circuit Vg2 (a) N-Well P-Substrate Outp ut I/O Pad P+ N+ N+ N+ Field-Oxide P+ N-Well N+ Output Internal Circuits C1 VDD VDD R1 R2 Mn4 Mp1 Mn3 C2 Vg1 Vg2
ESD Detection Circuit
Mn2 Mn1
ESD Current Path
(b)
Fig. 6. (a) ESD protection circuit with the SNTSCR device to protect the mixed-voltage I/O circuits. (b) Realizations of the SNTSCR device and the ESD detection circuit with the gate-coupling technique to trigger on the SNTSCR device.
in CMOS IC[15,16]. To save layout area, the ESD bus can be realized by the different metal layer, which overlaps the VDDpower line. The ESD bus is not directly connected to
an external power pin, but initially biased to VDDthrough
the diode D1 in Fig. 8. The diode D1 connected between the VDD power line and ESD bus is also used to block
the leakage current path from the I/O pad to VDD during
normal circuit operating condition with a high-voltage input signal. The diode Dp is connected between I/O pad
and ESD bus, whereas the diode Dnis connected between
VSS power line and I/O pad. One (the first) power-rail
ESD clamp circuit is connected between VDD power line
and VSS power line. Another (the second) power-rail
ESD clamp circuit is connected between the ESD bus and VSSpower line. The second power-rail ESD clamp
cir-cuit connected between ESD bus and VSS power line
should be designed with high-voltage-tolerant constraints without suffering the gate-oxide reliability issue. The ESD current at the I/O pad under PS-mode ESD stress can be discharged through the diode Dpto the ESD bus, and then
through the second power-rail ESD clamp circuit to the grounded VSS. The ESD current at the I/O pad under the
PD-mode ESD stress can be discharged through the diode Dpto the ESD bus, the second power-rail ESD clamp
cir-cuit to VSSpower line, and then through the parasitic diode
of the first power-rail ESD clamp circuit to the grounded VDD. With the turn-on-efficient power-rail ESD clamp
cir-cuits, high ESD level for the mixed-voltage I/O circuits can be achieved by this ESD protection scheme with ESD bus. Here, the design key point is how to design such a high-voltage-tolerant power-rail ESD clamp circuit with only low-voltage thin-oxide CMOS devices.
4.1. High-voltage-tolerant power-rail ESD clamp circuit for ESD bus with 2· VDD
Fig. 9 shows the high-voltage-tolerant power-rail ESD clamp circuit realized with only 1.2 V devices for 2.5 V
mixed-voltage I/O applications [17], which contains the ESD clamp device and an ESD detection circuit. The ESD clamp device (Mn1 and Mn2) is realized by the
stacked-NMOS (STNMOS) with the substrate-triggered technique [10]. The STNMOS is kept off without gate-oxide reliability during normal operation conditions. The ESD detection circuit is kept inactive during normal oper-ation conditions, but it becomes active to provide sub-strate-triggered current to quickly trigger STNMOS on under ESD stress conditions. Here, the time constant of R2 and C (realized by Mp3) should be designed to
distin-guish the power-on transition from the ESD transition. In normal operation conditions with VDDpower supply
of 1.2 V, the ESD bus line could be charged up to maxi-mum 2.5 V by the 2.5 V input signal at I/O pad. With a maximum voltage level of 2.5 V on the ESD bus, Mp1
and Mp2 are kept off but Mn3 is turned on to bias the
substrate of STNMOS at VSS, such that STNMOS is
Internal Circuit s Internal Circuits Stacked-NMOS Pull-up PMOS Gate Tracking Circuit N-Well Self-Biased Circuit VSS VDD Pad I/O VDD S econd P ower -Rail ES D Cl a m p Circ uit (Hi gh-Voltage-Tol erant) ESD Bus D1 Dp Dn First Power-Rail ES D Cla m p C ircuit
Fig. 8. The ESD protection network with the additional ESD bus line for the mixed-voltage I/O circuits.
Fig. 9. The high-voltage-tolerant power-rail ESD clamp circuit designed with only 1.2 V devices for operating with ESD bus of 2.5 V.
guaranteed to be kept off. The voltages across the gate-drain, gate-source, and gate-bulk terminals of every device inFig. 9do not exceed the process limitation (1.32 V in a given 1.2 V CMOS process). When ESD transient voltage is conducted to ESD bus from I/O pad with VSSrelatively
grounded, but VDDfloating with an initial voltage level of
0 V, Mp1and Mp2(whose initial gate voltages are at a low
voltage level of 0 V) can be quickly turned on by ESD energy to generate the substrate-triggered current to trigger the STNMOS into its snapback region to discharge ESD current from ESD bus to VSS.
The turn-on speed of STNMOS with or without ESD detection circuit is measured and shown inFig. 10, where a 0–20 V voltage pulse with a rise time of 10 ns is applied to ESD bus with grounded VSS and floating VDD. The
overshooting peak voltage of STNMOS without ESD detection circuit is about 10 V, which could damage the gate oxide of the low-voltage devices. On the contrary, the 20 V voltage pulse can be quickly clamped by STN-MOS with ESD detection circuit to a low voltage level without suffering the high overshooting voltage. Transmis-sion line pulsing (TLP) generator[18]is used to verify the secondary breakdown current (It2) of STNMOS with or
without ESD detection circuit. The measured TLP I–V curves of STNMOS with device dimension (W/L) of 240 lm/0.2 lm are shown inFig. 11. The STNMOS with ESD detection circuit can be triggered on at a lower voltage level than that without ESD detection circuit. In addition, the turn-on uniformity among the multiple fingers of STN-MOS can be improved to enhance its ESD robustness by the substrate-triggered effect[10], such that the It2of
STN-MOS with ESD detection circuit can be increased from 1.4 A to 2.4 A.
Another high-voltage-tolerant power-rail ESD clamp circuit realized with the stacked-PMOS device has been reported [19,20], as shown in Fig. 12. In this power-rail ESD clamp circuit, the stacked-PMOS device (Mp1 and
Mp2) with large device width is designed to discharge
ESD current between the ESD bus line and VSS under
ESD stress. The Mp3and Mp4are the long-channel devices
which divide the voltage of ESD bus by two for the mid-point with consideration of minimal leakage current. The gates of Mp1 and Mp2 are individually controlled by the
RC-based ESD detection circuits. During normal circuit operating condition, the gate of top PMOS Mp1is biased
at ESD bus, and the gate of bottom PMOS Mp2is biased
at half of ESD bus. Therefore, the Mp1and Mp2are kept
off without the gate-oxide reliability issue. Under ESD stress condition, both gates of Mp1 and Mp2 are initially
biased at 0 V by the ESD detection circuits, therefore the ESD current is discharged through the turned-on PMOS device. The design concept of stacked-PMOS configuration can be further applied to implement the power-rail ESD clamp circuit for ESD bus with 3· VDD [20]. The standby leakage current through the
Fig. 12. High-voltage-tolerant power-rail ESD clamp circuit realized with stacked-PMOS structure for ESD bus of twice the ordinary VDD.
Fig. 10. Measured voltage waveforms to verify the turn-on efficiency of the high-voltage-tolerant power-rail ESD clamp circuit with STNMOS.
Fig. 11. TLP-measured I–V curves of STNMOS with or without ESD detection circuit.
voltage divider in the ESD detection circuit should be fur-ther reduced for low-power applications.
4.2. High-voltage-tolerant power-rail ESD clamp circuit for ESD bus with 3· VDD
To meet the applications with 3· VDDinput signals, the
power-rail ESD clamp circuit is realized by using both 1 V and 2.5 V devices for the ESD bus of 3.3 V[21], as shown in Fig. 13. The internal power supply voltage of VDD is
only 1 V. The stacked-NMOS structure is formed by two NMOS transistors (Mn1and Mn2) with 2.5 V gate oxide.
During normal circuit operating condition, the gate of top NMOS Mn1is biased at VDD, and the gate of bottom
NMOS Mn2 is biased at VSS. Therefore, the
stacked-NMOS structure has no gate-oxide reliability problem under the bias (3.3 V) of ESD bus. The ESD detection cir-cuit is composed of the two PMOS devices (Mp1and Mp2)
with 2.5 V gate oxide, to provide the substrate current for triggering on the parasitic n–p–n BJT in the stacked NMOS structure during ESD stress. The gates of Mp1
and Mp2are individually controlled by the RC-based
detec-tion circuit. During normal circuit operating condidetec-tion, the ESD detection circuit can meet the gate-oxide reliability constraints and the local substrate of the stacked NMOS is biased at VSS by the turned-on Mn3.
Under ESD stress condition, both the gates of Mp1and
Mp2have the initial voltage level of0 V, while the VSSpin
is grounded but the VDD pin floating. The ESD detection
circuit will provide the trigger current flowing through the Mp1and Mp2 into the p-substrate. The Mn4 is added
in the ESD detection circuit to keep the Mn3off and Mp2
in a conductive state under ESD stress condition. Once the parasitic n–p–n BJT in the stacked-NMOS structure is triggered on, the ESD current is discharged from the ESD bus to the grounded VSS. By this design, the
turn-on-efficient high-voltage-tolerant power-rail ESD clamp circuit can be realized with an extremely low leakage cur-rent for the mixed-voltage I/O applications with 3· VDD
input signals. 5. Conclusion
This paper presents an overview on ESD protection designs for the mixed-voltage I/O circuits without suffering the gate-oxide reliability issue. To improve ESD level of the mixed-voltage I/O circuits, the ESD protection design without increasing the process complexity is strongly requested by the mixed-voltage I/O circuits in consumer IC products. The ESD protection scheme (circuit solution) with ESD bus and high-voltage-tolerant power-rail ESD clamp circuit is highly recommended to protect the mixed-voltage I/O interfaces. Such ESD protection design in the mixed-voltage I/O circuits still meets the gate-oxide reliability constraints, and can prevent the undesired leak-age current paths during normal circuit operating condi-tion. Under ESD stress condition, the ESD protection circuit should be quickly triggered on to discharge ESD current. The effective ESD protection solution for the mixed-voltage I/O circuits with low parasitic capacitance for high-speed I/O applications and low standby leakage current for low-power applications will continually be an important task to SOC implementation in nanoscale CMOS technology.
Acknowledgement
This work was supported by the National Science Coun-cil (NSC), Taiwan, ROC under Contract NSC 94-2215-E-009-048 and the MediaTek Fellowship, Hsinchu, Taiwan. References
[1] Kaczer B, Degraeve R, Rasras M, Mieroop KVD, Roussel PJ, Groeseneken G. Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability. IEEE Trans Electron Dev 2002;49:500–6.
[2] Pelgrom MJM, Dijkmans EC. A 3/5 V compatible I/O buffer. IEEE J Solid-State Circ 1995;30:823–5.
[3] Singh G, Salem R. High-voltage-tolerant I/O buffers with low-voltage CMOS process. IEEE J Solid-State Circ 1999;34:1512–25.
[4] Chuang C-H, Ker M-D. Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-lm CMOS technology. In: Proc IEEE int symp circuits and systems; 2004. p. 577–80. [5] Ker M-D. Whole-chip ESD protection design with efficient VDD
-to-VSS ESD clamp circuits for submicron CMOS VLSI. IEEE Trans Electron Dev 1999;46:173–83.
[6] Anderson W, Krakauer D. ESD protection for mixed-voltage I/O using nMOS transistors stacked in a cascode configuration. In: Proc EOS/ESD symp 1998. p. 54–71.
[7] Miller J, Khazhinsky M, Weldon J. Engineering the cascoded nMOS output buffer for maximum Vt1. In: Proc EOS/ESD symp 2000. p. 308–17.
[8] Ker M-D, Chuang C-H, Lo W-Y. ESD implantations for on-chip ESD protection with layout consideration in 0.18-lm salicided CMOS technology. IEEE Trans Semiconductor Manufact. 2005;18(2):328–37.
Fig. 13. High-voltage-tolerant power-rail ESD clamp circuit realized with the substrate-triggered stacked-NMOS device. The power-rail ESD clamp circuit is realized by only 1 V and 2.5 V devices for ESD bus biased at 3.3 V without suffering the gate-oxide reliability.
[9] Vashchenko VA, Concannon A, Ter-Beek M, Hopper P. Physical limitation of the cascoded snapback nMOS ESD protection capabil-ity due to the non-uniform turn-off. IEEE Trans Device Mater. Reliab. 2004;4:281–91.
[10] Ker M-D, Chen T-Y. Substrate-triggered technique for on-chip ESD protection design in a 0.18-lm salicided CMOS process. IEEE Trans Electron Dev 2003;50:1050–7.
[11] Ker M-D, Lin K-H, Chuang C-H. On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in sub-quarter-micron CMOS process. IEEE Trans Electron Dev 2004;51:1628–35.
[12] Ker M-D, Hsu H-C. ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit. IEEE Trans Circ Syst I 2005;52(1):44–53.
[13] Ker M-D, Chuang C-H. ESD protection design for mixed-voltage CMOS I/O buffers. IEEE J Solid-State Circ 2002;37:1046–55. [14] Voldman S, Gerosa G. Mixed-voltage interface ESD protection
circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies. In: Tech dig IEDM 1994. p. 277– 80.
[15] Ker M-D, Lin K-H. Design on ESD protection schemes for IC with power-down-mode operation. IEEE J Solid-State Circ 2004;39:1378–82.
[16] Worley ER, Gupta R, Jones B, Kjar R, Nguyen C, Tennyson M. Sub-micron chip ESD protection schemes which avoid avalanching junctions. In: Proc EOS/ESD symp 1995. p. 13–20.
[17] Ker M-D, Chang W-J, Wang C-T, Chen W-Y. ESD protection for mixed-voltage I/O in low-voltage thin-oxide CMOS. In: Tech dig IEEE int solid-state circuits conf 2006. p. 546–7.
[18] Ashton RA. Transmission line pulse measurements: a tool for developing ESD robust integrated circuits. In: Proc IEEE int conf on microelectronics test structures (ICMTS), 2004. p. 1–6.
[19] Maloney TJ, Kan W. Stacked pMOS clamps for high voltage power supply protection. In: Proc EOS/ESD symp 1999. p. 70–7.
[20] Poon SS, Maloney TJ. New considerations for MOSFET power clamps. In: Proc EOS/ESD symp 2002. p. 1–5.
[21] Ker M-D, Chen W-Y. Design on power-rail ESD clamp circuit for 3.3 V I/O interface by using only 1 V/2.5 V low-voltage devices in a 130-nm CMOS process. In: Proc IEEE int reliability physics symp 2005. p. 606–7.
