A low-cost CMOS dual-mode AC/DC data converter for signal
measuring technique
Cheng-Ta ChiangÆ Li-Lung Kao Æ Yu-Chung Huang
Received: 9 March 2009 / Revised: 17 August 2009 / Accepted: 27 August 2009 / Published online: 17 September 2009 Ó Springer Science+Business Media, LLC 2009
Abstract A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique is newly pro-posed. Instead of traditional full wave rectification, the realized synchronous rectification circuit is more attractive due to the easier integration and lower cost. In this paper, the design strategies of implementing the signal processing of AC and DC modes in the integrated circuit are discussed completely. Proven through SIMULINK in system level and SPICE simulations in circuit level, simulation results show that the proposed dual-mode AC/DC data converter achieves 8-bit resolution in DC mode and 7-bit resolution in AC mode. Measurement results have successfully veri-fied the correct functions and performance of the proposed data converter and confirmed it for AC/DC signal mea-suring technique. The area of this chip is 710 9 630 lm2 and the measured power consumption is 5.1 mW. The proposed dual-mode AC/DC data converter is suitable for the system of analog and mixed-signal boundary scan.
Keywords Analog to digital conversion Data converter Dual mode dual slope ADC
Synchronous rectification AC/DC signal measuring technique Analog and mixed-signal boundary scan
1 Introduction
Recently, efficient processes of the AC and DC signals have been an attractive research. Until now, some achievements [1–14] involving in measuring AC signals have been presented. [1–9] have been suitably used in wattmeter and digital multimeter, etc. [10–14] are inves-tigated on the topic of root-mean-square (RMS) converter. To perform AC signal processing, a suitable data converter is required. For example, the data converter in [14] is based on the algorithm of the delta-sigma modulator. Although the system performance of [14] is outstanding, the overall hardware cost will be higher due to the back-end digital signal processing, such as decimation filters. Without the delta-sigma modulator, a new design to process AC signals by using a dual slope analog-to-digital converter (ADC) is thus investigated in this work. Besides, a rectification cir-cuit is also an important circir-cuit. In the traditional full wave rectifier, such kinds of circuit structure need some passive components, such as diodes. Although MOS diodes in the integrated circuits can replace traditional diodes, some issues on the long time reliability should be especially considered. In order to avoid the reliability problems, a synchronous rectification circuit to sample AC signals [15] is more attractive due to the easier integration and lower cost. Based on the technique of the synchronous rectifica-tion circuit of [15], the novel design strategies are firstly and completely addressed in this work.
In this paper, a low-cost CMOS dual-mode AC/DC data converter for signal measuring technique is newly pro-posed. Based upon the device parameters of 0.25 lm 1P5M C.-T. Chiang (&)
Mixed Signal Design Technologies Division, SoC Technology Center, Industrial Technology Research Institute, Hsinchu 310, Taiwan, ROC
e-mail: [email protected]
C.-T. Chiang L.-L. Kao Y.-C. Huang
Measurement Techniques Laboratory, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Room 206, Engineering Building 4th,
1001 Ta-Hsueh Road, Hsinchu 300, Taiwan, ROC
L.-L. Kao
Realtek Semiconductor Corporation, Hsinchu 310, Taiwan, ROC DOI 10.1007/s10470-009-9387-6
CMOS technology with 3.3 V power supply, all the func-tions and performance of the proposed dual-mode AC/DC data converter are correctly tested and proven through SIMULINK in system level and SPICE simulations in circuit level [16]. Measurement results have successfully verified the correct functions and performance of the pro-posed data converter and confirmed it for AC/DC signal measuring technique. The proposed dual-mode AC/DC data converter is suitable for the system of analog and mixed-signal boundary scan.
The system level analysis and behavior model simula-tions are described in the Sect. 2. Section3 shows the circuit level implementation and simulation results. Sec-tion4 demonstrates measurement results. Finally, conclu-sions and future works are given in Sect.5.
2 System level analysis and behavior model simulations
Now, the system level analysis and behavior model of the proposed dual-mode AC/DC data converter are analyzed and simulated. The operational amplifier’s (OPAmp) slew rate, unity gain bandwidth, DC gain, and the -3 dB bandwidth and the oversampling ratio of the comparator are the critical points in this circuit. These requirements are different in DC and AC modes, and they should be ana-lyzed individually. By following the Sect.2, the configu-rations, operation principles, and circuit specifications of all the function blocks will be described completely. In the system level, all blocks are severely designed in the specification of 10-bit resolution. In the circuit level, the proposed dual-mode AC/DC data converter is requested to achieve 8-bit resolution in DC mode and 7-bit resolution in AC mode. Moreover, in AC mode, the OPAmp itself should be designed to support the 100 kHz of AC signal bandwidth. The requirements on the resolution and AC
signal bandwidth are fitted to the system of analog and mixed-signal boundary scan.
Figure1 shows the architecture of the proposed dual-mode AC/DC data converter. The proposed data converter consists of an input buffer, a polarity controller, an inte-grator, a comparator, a polarity prejudgment circuit, and the digital control circuits. The polarity prejudgment circuit and controller form the synchronous rectification circuit. The switching signals supplied to analog circuits are given by the digital control circuits. Based on the proposed architecture, the DC and AC signal measuring technique can be combined into a single chip. Thus, the hardware cost is reduced.
2.1 The requirements of the OPAmp’s slew rate in DC and AC mode
Firstly, the problem induced by the OPAmp’s finite slew rate is investigated in DC mode. The OPAmp’s finite slew rate will lead to the integration error. This error could not be canceled during the charging and discharging periods. The worst case of the integration error is given by DQERROR¼ Z i dt¼ Z V IN R dt¼ Z SR t R dt¼ SR 2 R Dt 2 k DVERROR¼ DQERROR C ¼ SR 2 R C Dt 2 k DVERRORjMAX¼ V2 FS 8 R C SR ð1Þ
To make DVERRORjMAX\
LSB 2 ; thus V2 FS 8 R C SR\ VFS 2Nþ1 ð2Þ
where DQERRORis the mis-integration charge on the
inte-grator capacitor, VFSthe full scale voltage, R the resistor used
in integrator, C the capacitor used in integrator, SR the
Fig. 1 The architecture of the proposed dual-mode AC/DC data converter
OPAmp’s slew rate, and Dtkthe delay induced by finite slew
rate. Taking Fig.2as an analysis, where N is the overall ADC resolution in bits, Dtithe time margin until signal has settled,
and TINTthe integration period, the requirements of slew rate
can be derived by Eq.2
SRINPUT BUFFER OP and POLARITY CONTROLLER OP [VFS 2 N2 R C ¼ 1:5 V 2102 50 MX 330 pF ¼ 23:2V ms ð3:1Þ and SRINTEGRATOR OP[ VFS 2 TINT ¼ 1:5 V 2 16:6 ms¼ 45 V s ð3:2Þ
Hence, slew rate of the OPAmp used in buffer and polarity controller is 23.2 V/ms and slew rate of the OPAmp used in integrator is 45 V/s. The integration error induced by slew rate is demonstrated in Table1. In AC mode, slew rate is defined as the maximum slope DVo/Dt of each OPAmp.
Thus, the requirements of slew rate can be derived as VIN¼ Vo¼ VSWING 2 sinðxtÞ SR¼dVo dt MAX¼ VSWING 2 x cosðxtÞ MAX ¼1:5 V 2 ð2p 100 kHzÞ cosðxtÞ MAX¼ 0:471 V ls ð4Þ VIN¼ VSWING 2 sinðxtÞ VO¼ 1 s R CVIN SR¼dVo dt MAX¼ 1 R C VSWING 2 sinðxtÞ MAX ¼ 1 50 MX 330 pF 1:5 2 sinðxtÞ MAX¼ 45:4Vs ð5Þ According to Eqs.4and5, slew rate of the OPAmp used in buffer and polarity controller is 0.471 V/ls, and the absolute value of slew rate of the OPAmp used in integrator is 45.4 V/s.
2.2 The requirements of the OPAmp’s unity gain bandwidth in AC and DC mode
The OPAmp’s finite unity gain bandwidth will lead to gain error, and produce additional pole in the overall transfer function. This effect is modeled as a DC gain error and a signal delay. In AC and DC modes, the output responses of non-ideal input buffer with ideal integrator, non-ideal polarity controller with ideal integrator, and non-ideal integrator, are derived as
VOUTPUTðtÞjADClarge enoughffi
1 R C xIN þ GBW RCxIN GBWþ x2IN GBW 1 R C WIN 2 4 3 5 eGBWt GBW RCxIN GBWþ x2IN GBW cosðxIN tÞ GBW RC GBW2þ x2 IN sinðxIN tÞ ð6:1Þ Fig. 2 The error induced by
slew rate under two different input signals
Table 1 The integration error induced by slew rate
Slew rate (V/ms) Integrating error (%)
0.225 5.0 (4-bit resolution)
2.250 0.5 (7-bit resolution)
VOUTPUTðtÞjADClarge enoughffi GBW GBWþ 1 RC 1 xIN 1 R C GBW GBWþ1 R x2 INþ GBW þ 1 RC 2 xIN R C " # e GBWþð RC1Þt GBW GBWþ1 R 1 R C xIN x2 INþ GBW þ 1 RC 2 1 xIN " # cosðxIN tÞ GBW RC x2 INþ GBW þ 1 RC 2 " # sinðxIN tÞ ð6:2Þ VOUTPUTðtÞjADClarge enoughffi
1 R C xIN þ GBW 2 RCxIN GBW 2 þ x2 IN GBW 2 1 R C xIN 2 4 3 5 eGBW2 t GBW 2 RCxIN GBW 2 þ x2 IN GBW 2 ð Þ cosðxIN tÞ GBW 2 RC GBW 2 2 þx2 IN sinðxIN tÞ ð6:3Þ
VOUTPUTðtÞjADClarge enoughffi
1 RC GBWþ 1 RC GBW e GBWt 1 RC t ð7:1Þ
VOUTPUTðtÞjADClarge enoughffi
1 RC GBW 2 þ 1 RC GBW 2 e GBW 2 ð Þt 1 RC t ð7:2Þ
VOUTPUTðtÞjADClarge enoughffi
1 R C 1 GBWþ 1 RC þ t þ 1 GBWþ 1 RC eGBWt ! GBW GBWþ 1 RC ð7:3Þ
where GBW is the OPAmp’s unity gain bandwidth, and xINthe frequency of input signal. Equations (6.1,6.2,6.3
is derived for AC mode and Eqs.7.1,7.2,7.3is derived for DC mode. The curves shown in Fig.3represent the output responses of each integrator under different unit gain bandwidth. The frequency range is swept from 150 kHz to 10 MHz. These results conclude that if the unit gain bandwidth is not large enough, the larger integration error will be obtained. Besides, this error will not be \1 least significant bit (LSB) of the 10-bit resolution. By the same way, the analysis in DC mode is also performed as shown in Fig.4. The requirements of the unity gain bandwidth and the integration error are calculated in Tables2and3.
2.3 The requirements of the OPAmp’s DC gain
The error induced by the OPAmp’s finite DC gain is a constant value. It could be canceled during the charging and discharging period as shown in Fig.5. The counter evaluation time tXis given by
VIN R C ADC1 ADC1þ 1 ADC2 ADC2þ 2 TINT ¼VREF R C ADC1 ADC1þ 1 ADC2 ADC2þ 2 tX ð8Þ
where VIN is the input signal, ADC1 the DC gain of the
OPAmp used in the input buffer, and ADC2the DC gain of
the OPAmp used in the polarity controller. Basically, the DC gain requested for 10-bit resolution should be larger than 60 dB. Although this value is suitably performed in
Fig. 3 In AC mode, the output response of the integrator under sweeping the unit gain bandwidth from 150 kHz to 10 MHz
the behavior model, the DC gain is slightly increased to 65 dB due to the margin of circuit design.
2.4 The requirements of the synchronous rectification circuit
Now, the requirements of the synchronous rectification cir-cuit are addressed. The clock frequency of the comparator used in the synchronous rectification circuit directly affects the overall ADC resolution. The reason is that when AC sine wave is going below the voltage VREF, the comparator used in
the polarity prejudgment circuit needs a clock cycle time to sense the voltage variation as displayed in Fig.6. Thus, the clock cycle time will directly affect the quality of rectifica-tion. The integration error is given by
VERROR¼ 2 R C Z TIN 2þTC TIN 2 VFS 2 sinðxin tÞdt 0 B B @ 1 C C A 2TINT TIN 1 ¼ VFS xin R C 2 TINT TIN 1 ð1 cosðxin TCÞÞ ffiVFS xIN T 2 C 2 R C 2 TINT TIN 1 ð9Þ The error voltage should \0.5 LSB, thus
VFS xin TC2 2 R C 2 TINT TIN 1 1 2 LSB ¼ 1 2 VFS 2N Finally, FCLK 2 N 2þ1pffiffiffip FIN ð10Þ
where TCis the clock cycle time, TINthe RC time constant,
TINT the integration time, and FIN the input frequency,
FCLK the frequency of the comparator used in the polarity
prejudgment circuit. The overall ADC resolution versus the comparator oversampling ratio is shown in Fig. 7 and Table4. In the specification of 10-bit resolution, the Fig. 4 In DC mode, the output
response of the integrator under sweeping the unit gain bandwidth from 60 Hz to 30 kHz
Table 2 The requirements for OP unity gain bandwidth and inte-gration error in AC mode
OPAmp FT(MHz) Error
Input buffer 4 5e-4
Polarity controller 8 5e-4
Integrator 25 5e-4
Table 3 The requirements for OP unity gain bandwidth and inte-gration error in DC mode
OPAmp FT(kHz) Error
Input buffer 15 5e-4
Polarity controller 30 5e-4
Integrator 15 5e-4
Fig. 5 The integrator’s output affected by the OPAmp’s finite DC gain during the charging and discharging period
oversampling ratio should be 56.7. Finally, all the circuit specifications discussed above are organized in Tables5 and6.
2.5 The whole system model
The whole system model is incorporated and performed by SIMULINK. The overall model shown in Fig.8 is built, and the four operational phases are demonstrated in Fig.9. Firstly, the simulations in DC mode are performed. The inputting DC signal is 0.375 V. All operational phases are the reset phase (0–16.6 ms), the integration phase (16.6– 33.3 ms), the negative integration phase (33.2–50 ms), and the output phase (50–66.4 ms). In Fig.10(b), the Fig. 6 Ideal rectification versus real rectification. The fine-type line is the ideal rectified sine wave and the boldface-type line is the real rectified sine wave
Fig. 7 The comparator oversampling ratio versus ADC’s resolution
Table 4 Overall ADC resolution versus the comparator oversam-pling ratio OSR Resolution = 16 (BIT) 453.6 Resolution = 15 (BIT) 320.8 Resolution = 14 (BIT) 226.8 Resolution = 13 (BIT) 160.4 Resolution = 12 (BIT) 113.4 Resolution = 11 (BIT) 80.2 Resolution = 10 (BIT) 56.7 Resolution = 9 (BIT) 40.1 Resolution = 8 (BIT) 28.4 Resolution = 7 (BIT) 20.0
Table 5 The specifications for OPAmp used in buffer, gain con-troller, and integrator
Spec for OPAmp used in buffer and gain controller
Spec for OPAmp used in integrator Input/output swing 1.5 V 1.5 V DC gain 65 dB 65 dB Slew rate (DC/AC mode) 23.2 V/ms 45 V/s 0.471 V/us 45.4 V/s
Unity gain frequency (DC/AC mode)
15/30 kHz 15 kHz
10 MHz 0.1 MHz
Phase margin [65° [65°
Target error tolerance \0.25 LSB \0.25 LSB
Table 6 The specifications for comparator used in polarity prejudg-ment circuit and behind integrator
Spec for comparator used in polarity prejudgement circuit
Spec for comparator used behind integrator Offset voltage (mV) \5 \3 Input/output swing (V) 1.5 1.5 DC gain of preamplifier 10 10 3 dB bandwidth of preamplifier (MHz) 10 0.1 Clock frequency 12 MHz 7.68 kHz
integration is performed to discharge the output of the integrator to -0.375 V. Finally, the counter will evaluate the corresponding digital number as shown in Fig.10(c). The error between the ideal and real digital number is
0.5 LSB. Thus, the requirement of 8-bit resolution in DC mode is successfully achieved.
Then, the simulations in AC mode are performed. The inputting AC signal is 1.5 Vpp. In the Fig.11(a, b), the operations of the synchronous rectification and integration are correctly shown, respectively. Finally, the digital counter will be triggered until the output voltage of the integrator exceeds the reference voltage (0 V). As shown in Fig.11(c), the error in AC mode is 0.7 LSB. Thus, the requirement of 7-bit resolution is fulfilled. The whole system model is successfully matched to the designed ADC resolutions. All the circuit descriptions and simulation results of the proposed dual-mode AC/DC data converter are addressed in the next section.
3 Circuit level implementation and simulation results
Based on the specifications discussed in Sect. 2, the OPAmps, comparators, and the digital control circuits will be designed and verified in this section.
Fig. 8 The proposed dual-mode AC/DC data converter modeled in SIMULINK
3.1 The OPAmp
Figure12 shows the circuit structure of folded-cascoded OPAmp. The pertinent design relationships are derived as
ADC¼ gm1 ROUT ð11:1Þ ROUT¼ g½ m6 ro6 rðo6jjro4Þjjgm8 ro8 ro10 ð11:2Þ xT ¼ gm1 CL ð11:3Þ xpdom¼ 1 ROUT CL ð11:4Þ xpnondom¼ gm5 CX ð11:5Þ
where gm is the transistor transconductance, ro the
tran-sistor resistance, Cxand CLthe capacitance loading, ADC
the overall gain of the OPAmp, ROUTthe output resistance
of the OPAmp, xT the unit gain frequency, xPdom the
dominant pole frequency, xPnon - dom the non-dominant
pole frequency. Based on Eqs.11.1,11.2,11.3,11.4,11.5, the SPICE simulations of the folded-cascoded OPAmp used in the input buffer, polarity controller, and integrator are shown in Figs.13 and 14, respectively. Besides, Fig. 10 In DC mode, the a input b output of the integrator, and c the output digital number of the counter
simulations in five design corners are listed in Tables7and 8. All the requirements are successfully matched.
3.2 The comparator
The comparator demonstrated in Fig.15is implemented as a preamplifier plus a latch stage. The gain of the pream-plifier is derived as
Apre amp¼
gm1
gm3
ð12Þ
where gm is the transistor transconductance. The
combi-nation of the diode-connected transistors of the gain stage and the transistors of the positive-feedback loop acts as a moderately large impedance, and gives gain from the preamplifier stage to the track-and-latch stage. The offset
simulations of the comparators used in the polarity pre-judgment circuit and behind the integrator are demon-strated in Figs. 16 and17. The offset voltages are 5 and 2.5 mV, respectively. The offset voltages are all \1 LSB, and matched to the requirement of resolution. Finally, the functions and output voltages of the comparator in the latch and pre-amplification are all correctly verified.
3.3 The digital control circuits and the whole system
The block diagram of the digital control circuits is dis-played in Fig.18. The digital control circuits consist of a Fig. 12 The circuit schematic of the folded-cascoded OPAmp
Fig. 13 The (a) gain (b) phase of the folded-cascoded OPAmp used in the input buffer and polarity controller
Fig. 14 The (a) gain (b) phase of the folded-cascoded OPAmp used in the integrator
Table 7 The SPICE simulations of the folded-cascoded OPAmp used in the input buffer and polarity controller
TT FF SS SF FS
DC gain (dB) 79.8 76.1 82.1 81.5 75.6
PM 75.5° 75.5° 75.5° 75.8° 75.1°
Ft(MHz) 23.9 22.9 24.7 23.8 24.0
Power (mW) 1.57 1.54 1.63 1.61 1.53
Table 8 The SPICE simulations of the folded-cascoded OPAmp used in the integrator
TT FF SS SF FS
DC gain (dB) 79.8 76.1 82.1 81.5 75.6
PM 89.7° 89.7° 89.7° 89.7° 89.7°
Ft(MHz) 0.382 0.366 0.394 0.380 0.384
divider, a Johnson counter, AC control logic, DC control logic, switching control logic, a 7-bit counter, and a 8-bit adder. Firstly, they generate all the switching signals to control analog circuits. When DC mode is chosen, the
proposed dual-mode AC/DC data converter is operated as a general dual slope ADC. On the contrary, if AC mode is chosen, the output of the comparator used in the polarity prejudgment circuit will send to the switching control Fig. 15 The circuit schematic
of the comparator Vo lt ag e (V) -5mV 3mV 10mV -20mV -2.5mV 50mV -90mV 187.5mV -375mV -750mV 750mV Time (us) 3.3 -3.3 0 130 260 390 520 780 910 1040 1170 0 650 2mV 1300 1430 1560 1690 -1.5mV 1mV 1820 -5mV 3mV 10mV -20mV -2.5mV 50mV -90mV 187.5mV -375mV -750mV 750mV 2mV -1.5mV 1mV
Fig. 16 The offset simulation of the comparator used in the polarity prejudgment circuit
Voltage (V) -5mV 3mV 10mV -20mV -2.5mV 50mV -90mV 187.5mV -375mV -750mV 750mV Time (us) 3.3 -3.3 0 130 260 390 520 780 910 1040 1170 0 650 2mV 1300 1430 1560 1690 -1.5mV 1mV 1820 -5mV 3mV 10mV -20mV -2.5mV 50mV -90mV 187.5mV -375mV -750mV 750mV 2mV -1.5mV 1mV
logic. The entire digital control signals are as listed in Table9. For example, the AC input is the sine wave. Once the sine wave is below the reference voltage of
comparator, the sine wave will be inverted. At the same time, the integration phase is also operated. Finally, they convert the output signals of analog circuits into digital Fig. 18 The block diagram of the digital control circuits
Table 9 The digital control signals for switches used in polarity prejudgment circuit
Control signal (DC/AC) Control signal (DC/AC) Control signal (DC/AC) Control signal (DC/AC) Switch 1 0/0 1/1 0/0 0/0 Switch 2 0/0 0/0 1/1 1/1 Switch 3 1/1 0/0 0/0 0//0 Switch 4 0/0 1/1 1/1 1/1 Switch 5 1/1 1/0 0(Vin\ Vcm) or 1(Vin\ Vcm)/0 0(Vin\ Vcm) or 1(Vin\ Vcm)/0 Switch 6 1/1 0/0 0/0 0/0
Fig. 19 The SPICE simulations of the digital control circuits
codes. The SPICE simulations of the digital control cir-cuits are demonstrated in Fig.19. The integrator’s output shows the four operational phases successfully, and the digital codes are correctly generated. Finally, the whole system is built and simulated in SPICE. Figure20shows the input and output of the integrator under the DC input voltage of -VFS/4. Besides, the AC input amplitude is
VFS/2, and the input and output of the integrator are shown
in Fig.21. The circuit operations and the SPICE results are correctly matched to the system level analysis and behavior model simulations as described in Sect. 2. All the functions and performance of the proposed dual-mode AC/DC data converter are successfully tested and proven through SPICE simulations.
Fig. 20 In DC mode, the input and output of the integrator under the DC input voltage of -VFS/4
Fig. 21 In AC mode, the input and output of the integrator under the AC input amplitude of VFS/2
4 Measurement results
Firstly, the circuits of the proposed dual-mode AC/DC data converter are built by discrete components to verify circuit operations. The measurement setup is shown in Fig.22. The switches, the OPAmps, a decoder, a LED display, and a dual-slope ADC, are implemented by CD4066, LF411, HD7474, LA601, and ICL7135, respectively. Figure23(a, b) show the outputs of the integrators under the DC input voltage of 1 V and the AC input amplitude of 1 V. As demonstrated, the circuit operations in DC and AC modes are all successfully performed as discussed in the Sect.2. All the measured results are plotted in Fig.24, and the accuracy is within ±1.46%. Thus, all the circuit operations of the proposed dual-mode AC/DC data converter are successfully verified.
Finally, a low-cost CMOS dual-mode AC/DC data converter for signal measuring technique has been imple-mented. Each mode can be selected by an external pin, which is labeled as DC/AC Selector. Figure25(a, b) Fig. 22 The measurement
setup of the proposed dual-mode AC/DC data converter built by the discrete components
Fig. 23 The outputs of the integrators under the (a) DC input voltage of 1 V and (b) AC input amplitude of 1 V
Fig. 24 The measured transfer curve of the proposed dual-mode AC/DC data converter built by the discrete components
demonstrate the physical layout and photograph of the proposed dual-mode AC/DC data converter, respectively. The area of this implemented chip is 710 9 630 lm2and the power consumption is 5.1 mW. The system clock fre-quency is 7.69 kHz and another clock signal for the com-parator used in the polarity prejudgment circuit is 12 MHz. Firstly, oscilloscope waveforms of the input sine wave and the output synchronous rectified signals are demonstrated in Fig.26(a–f). As shown, the correct circuit operations of the integrated synchronous rectification circuit are suc-cessfully proven. Next, a total of 32768 digital codes are collected by the logic analyzer Agilent 16702A. The dif-ferential nonlinearity error (DNL) and integral nonlinearity error (INL) are computed through the SANDWORK
soft-ware. In DC mode, the input signal is a ramp signal with frequency 0.1 Hz, and the input signal is a sine wave with frequency 8 kHz in AC mode. After the computation, the DNL and INL are all demonstrated in Figs.27and28. In these two modes, the DNL and INL are all \0.5 LSB. Thus, the whole system is correctly verified and success-fully matched to the designed ADC resolutions, which is 8-bit in DC mode and 7-bit in AC mode. Measurement results have successfully verified the correct functions and performance of the proposed data converter and confirmed it for AC/DC signal measuring technique. All the charac-teristics of the proposed data converter and comparisons with conventional methodology [14] are summarized in Table10.
Fig. 25 aThe physical layout bthe photograph of the proposed dual-mode AC/DC data converter. The area of this implemented chip is
710 9 630 lm2
Table 10 The characteristics of the proposed dual-mode AC/DC data converter and comparisons with conventional methodology [14]
This work [14]
Technology 0.25 lm 0.8 lm
Supply voltage 3.3 V ±3 V
Clock sampling methodology Oversampled Oversampled
Chip output Digital Analog
Need back-end signal processing? (decimation filters)
No Yes
Signal bandwidth 100.2 kHz 50 kHz
Signal swing 1.3–2.8 V 0.4 Vrms
Resolution DC mode: 8 bits AC mode: 7 bits DC mode: none AC mode: 14.6 bits (SNR = 88 dB)
Power consumption 5.1 mW 40 mW
Physical layout area 710 9 630 lm2 1,000 9 1,000 lm2
DNL DC mode: ?0.185 to -0.224 LSB AC mode: ?0.168 to -0.154 LSB NA INL DC mode: ?0.422 to -0.087 LSB AC mode: ?0.138 to -0.164 LSB NA
5 Conclusion
A low-cost CMOS dual-mode AC/DC data converter for signal measuring technique is newly proposed. Instead of traditional full wave rectification, the realized synchro-nous rectification circuit is more attractive due to the easier integration and lower cost. All the functions and performance of the proposed dual-mode AC/DC data converter are tested and proven through SIMULINK in system level and SPICE simulations in circuit level. Measurement results have successfully verified the correct functions and performance of the proposed data converter and confirmed it for AC/DC signal measuring technique.
By following this paper, readers can understand how to reduce hardware cost and to implement the synchronous rectification circuit in the integrated circuits. Besides, without using conventional back-end digital signal pro-cessing, another design strategy to simplify overall system complexity is demonstrated in this work. In the future research, the proposed dual-mode AC/DC data converter will be researched on analog and mixed-signal boundary scan. On the other hand, by following all the design strategies addressed above, the resolution of the proposed dual-mode AC/DC data converter can be extended. Thus it can be adaptively applied to high-resolution applications.
Fig. 26 Oscilloscope waveforms of the input sine wave and the output synchronous rectified signals under the input signal with afrequency 100 Hz and 0.75 V amplitude b frequency 100 Hz and
1.5 V amplitude c frequency 20 kHz with 0.75 V amplitude dfrequency 20 kHz with 1.5 V amplitude e frequency 100 kHz with 0.75 V amplitude f frequency 100 kHz with 1.5 V amplitude
Acknowledgments The authors acknowledge the SoC Technology Center of Industrial Technology Research Institute, Taiwan, for their support in chip fabrication. This work was supported by the National Science Council, ROC, under contracts NSC92-2218-E-009-011.
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Cheng-Ta Chiang(S’00-M’05) was born in Taiwan, ROC, in 1977. He received the B.S. degree in electronics engineer-ing from Chung Yuan Christian University, Jhongli, Taiwan, in 1999, the M.S. degree in bio-medical engineering from the National Cheng Kung Univer-sity, Tainan, Taiwan, in 2001, and the Ph.D. degree in elec-tronics engineering from the National Chiao Tung Univer-sity, Hsinchu, Taiwan, in 2006. He was a Visiting Scholar with the Department of Electrical and Computer Engineering, The Johns Hopkins University, Baltimore, MD, from October 1, 2004 until November 30, 2005. He was included in Marquis Who’s Who in Science and Engineering 2006–2007 and Marquis Who’s Who in the World 2008. He was a review committee member of the National Chip Implementation Center, Hsinchu. He is currently with Mixed Signal Design Technologies Division, SoC Technology Center, Industrial Technology Research Institute, Hsinchu. His main research interests include analog integrated circuits, biomedical electronics, image sensor circuits and systems, sensor signal conditioning and Fig. 27 The DNL and INL in DC mode. The input signal is a ramp
signal with frequency 0.1 Hz
Fig. 28 The DNL and INL in AC mode. The input signal is a sine wave with frequency 8 kHz
transducers, Nyquist A/D converters, and high-resolution delta-sigma modulator. Dr. Chiang is a journal reviewer for the IEEE Transactions on Instrumentation and Measurement, IEEE Industrial Electronics, IEEE Sensors Journal, and an editorial advisory board member for the Sensors & Transducers Journal.
Li-Lung Kaowas born in Tai-wan, Republic of China, in 1980. He received the B.S. degree in electronics engineer-ing from National Tsengineer-ing-Hua University and the M.S. degree in electronics engineering from National Chiao-Tung Univer-sity, Taiwan, ROC, in 2004 and 2007, respectively. He currently services in Realtek Semicon-ductor Corporation, Hsinchu, Taiwan, ROC. His main research interests have been in analog integrated circuits, delta-sigma A/D converter, and low-speed data converters.
Yu-Chung Huangreceived the M.S. degree in electrical engi-neering and Ph.D. degree in process engineering from the Technology University of Ber-lin, BerBer-lin, Germany, in 1982 and 1985, respectively. Since 1985, he has been a Professor in the Department of Electronics, National Chiao-Tung Univer-sity, Hsinchu, Taiwan, ROC His research interests are sensors and measuring technologies. Prof. Huang is a member of the Committee of the Chinese Metrology Society and a member of the Micromechanical Science Institute, ROC.
