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Effect of Gate Length on Device Performances of AlSb/InAs High Electron Mobility Transistors
Fabricated Using BCl3 Dry Etching
View the table of contents for this issue, or go to the journal homepage for more 2012 Jpn. J. Appl. Phys. 51 060202
(http://iopscience.iop.org/1347-4065/51/6R/060202)
Effect of Gate Length on Device Performances of AlSb/InAs High Electron Mobility
Transistors Fabricated Using BCl
3Dry Etching
Chien-I Kuo1, Heng-Tung Hsu2, Ching-Yi Hsu3, Chia-Hui Yu1, Han-Chieh Ho4, Edward Yi Chang1;3, and Jen-Inn Chyi4
1Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu, Taiwan 30010, R.O.C. 2Department of Communications Engineering, Yuan Ze University, Chungli, Taiwan 32003, R.O.C.
3Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan 30010, R.O.C. 4Department of Electrical Engineering, National Central University, Jhongli, Taiwan 32001, R.O.C.
Received March 2, 2012; accepted March 26, 2012; published online May 22, 2012
In this paper, we present the development of a mesa isolation process for AlSb/InAs high electron mobility transistors (HEMTs) using inductively coupled plasma (ICP) etching with BCl3gas. Devices with different gate lengths (Lg: 60, 100, and 200 nm) fabricated by this dry etching technique
show good DC and RF performances. With an appropriate Lg/gate-channel distance ratio, the 200-nm-gate has very high peak
transconductances of 781 mS/mm atVDS¼ 0:1 V and 2000 mS/mm at VDS¼ 0:5 V. Moreover, an extrinsic current gain cutoff frequency of
137 GHz and maximum oscillation frequency of 97 GHz were achieved at a drain bias voltageVDS¼ 0:3 V, indicating the great potential for such a
device operating at high frequency with extremely low DC power consumption. # 2012 The Japan Society of Applied Physics
E
lectronic and optical devices based on binary alloys of the 6.1 A family including InAs (6.058 A), GaSb (6.096 A), and AlSb (6.136 A) have attracted much attention recently. Antimonide-based compound semicon-ductor AlSb/InAs high electron mobility transistors (Sb HEMTs) have been demonstrated for extremely low voltage operations due to the combination of high peak electron velocity (4 107cm/s) at a low electric field and high channel conductivity with the high electron confinement barrier (1.35 eV) of the InAs/AlSb interface.1,2)In fact, these values for Sb HEMTs are nearly two times higher than those of In-rich InxGa1xAs/InP HEMTs, demonstrating their great potential for phased-array and satellite systems, which require ultralow-power consumption.3–5)The AlxGa1xSbyAs1y/InAs material system has proven to be a viable choice for advanced AlSb/InAs HEMTs with metamorphic growth on a GaAs substrate and an AlSb/ AlGaSb buffer layer can eliminate the dislocations effec-tively.6) Unfortunately, AlSb is extremely liable to be
oxidized in air. Additionally, wet etching of the AlSb and InAlAs stacked layers is hard to control to achieve the required depth and is not repeatable in mesa isolation steps. As a result, it is essential to develop a dry etching technique for a more controlled and less labor-intensive fabrication process.
Gate length scaling is a well-known technique to boost the operating frequency of devices. However, in some cases, scaling the gate length (Lg) alone may not be as effective as
expected. It is thus our motivation to investigate the effect of gate length scaling on the device performance of Sb HEMTs. In this study, we fabricate AlSb/InAs HEMTs with Lg
of 60, 100, and 200 nm using an ICP etcher with BCl3 gas. The effect of Lg on AlSb/InAs HEMTs performances has
also been investigated. The fabricated devices demonstrate excellent DC and RF performances after dry etching, indicating the successful fabrication of AlSb/InAs HEMTs using this BCl3dry etching process for mesa etching.
Figure 1 shows the epitaxial structure of the Sb HEMTs. The AlSb/InAs heterostructure was grown on a 3-in. GaAs substrate by solid-source molecular beam epitaxy (MBE). The composite AlSb/Al0:7Ga0:3Sb metamorphic buffer layer was utilized to accommodate the lattice mismatch between the GaAs substrate and device layer. Te planar doping was
employed in the AlSb barrier layer to attain high electron transfer efficiency and reduce the gate-to-channel distance.7) A 5-nm-thick In0:45Al0:55As layer was capped on the GaSb and AlSb layers to prevent air exposure and provide a chemically stable surface layer. The electron sheet carrier density and mobility at room temperature were measured to be1:7 1012cm2 and 22,400 cm2V1s1, respectively. The fabrication process started with mesa isolation through a novel inductively coupled plasma (ICP) process using BCl3 gas (ULVAC NE-950EX etcher) and the dry etching was stopped at the Al0:7Ga0:3Sb buffer layer. BCl3 gas has been found to be more effective for etching AlGaSb than Cl2-based gases.8)The critical step in guaranteeing the performance of the fabricated Sb HEMTs is mesa formation by dry etching, which must be well controlled so that it stops at the Al0:7Ga0:3Sb buffer, where 30% Ga is added to avoid the oxidation of AlSb.9)Figure 2(a) shows the etching depth as a function of etching time for the device etched with BCl3 Fig. 1. Epitaxial structure of the AlSb/InAs HEMT device. The inserted SEM image is the T-shaped gate after silicon nitride passivation. Devices with Lgbetween 60 and 200 nm were fabricated.
Japanese Journal of Applied Physics 51 (2012) 060202
060202-1 # 2012 The Japan Society of Applied Physics
RAPID COMMUNICATION DOI: 10.1143/JJAP.51.060202
gas. The etching rate is well controlled to obtain shallow mesa isolation. The measured etch depth as a function of the etching time with Cl2/Ar mixed gas is depicted in Fig. 2(b). As observed from the figure, it is hard to control the etching depth using Cl2/Ar due to the drastic increase in depth when the etching time is approximately 200 s. The depth of the device mesa was measured to be approximately 1500 A by KLA-Tencor P-10 surface profiler. Pd/Pt/Au ohmic contacts were evaporated and subsequently annealed at 300C for 30 s in N2 ambient, resulting in a low contact resistance of 0.027 mm and a sheet resistance of 157 /sq. Non-recessed Pt/Ti/Pt/Au T-shaped gates were defined on the InAs cap layer using trilayer resist and electron beam lithography. The inserted scanning electron micros-copy (SEM) image in Fig. 1 is the 60 nm T-shaped gate after silicon nitride passivation. Finally, a 100-nm-thick SiN passivation layer was deposited by low-temperature plasma-enhanced chemical vapor deposition (PECVD) to protect the devices.
Figure 3(a) shows the drain–source current (IDS) as a
function of drain–source voltage (VDS) with the gate–source
voltage (VGS) varied from 0 to0:8 V for the 200-nm-gate
and2 20-m2-width device. The device exhibits a maxi-mum drain current density of 900 mA/mm at a gate bias of 0 V and a drain bias of 500 mV. Figure 3(b) shows the DC transconductance (gm) as a function of gate voltage
at different VDSfor the same device. A maximum DC gmof
2000 mS/mm is achieved at the same bias. At room tem-perature, the measured on-resistance RON was 0.33 mm.
The IV characteristics in Fig. 3 illustrate the advantages of the Sb HEMT with low-voltage operation, low RON, and
high gm, which are necessary for ultralow-power and
high-frequency applications. Such a high current density and gm value result from the high peak electron velocity at a
low electric field and the high channel conductivity, which enable the operation of AlSb/InAs HEMTs at very low drain bias voltages. As observed from Fig. 3(b), the drastic increase in the gm peak value for VDS greater than 0.4 V is
due to the impact ionization in the channel resulting from the staggered band lineup at InAs/AlSb heterojunctions. Since the staggered band alignment at such heterojunctions does
180 160 140 120 100 80 60 1000 1500 2000 2500 3000 3500 4000
Etch depth (angstrom)
Etching time(s) Etching depth BCl3 = 15 sccm Pressure = 5 mtorr (a) 600 500 400 300 200 100 0 10000 20000 30000 40000 50000
Etching depth (angstrom)
Etching time (s) Etching depth Cl 2 = 25 sccm Ar = 5 sccm (b)
Fig. 2. (Color online) (a) Etch depth as a function of the etching time for the Sb HEMT using BCl3and (b) etch depth as a function of the etching time for the Sb HEMT using Cl2/Ar.
0.5 0.4 0.3 0.2 0.1 0.0 0 100 200 300 400 500 600 700 800 900 VGS = 0 ~ -0.8 V Lg = 200 nm LSD = 2 µm AlSb/InAs HEMTs
Drain current density (mA/mm)
Drain voltage (V) (a) 0.0 -0.2 -0.4 -0.6 -0.8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 T ransconductance (mS/mm) Gate voltage, VGS (V) Vd=0.1V Vd=0.2V Vd=0.3V Vd=0.4V Vd=0.5V AlSb/InAs HEMTs (b) 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -200 0 200 400 600 800 1000 1200 1400 1600 T ransconductance (mS/mm) Gate voltage VGS (V) 60 nm 100 nm 200 nm VDS = 0.3 V AlSb/InAs HEMTs (c)
Drain current density (mA/mm)
-0.8-0.7-0.6-0.5-0.4-0.3-0.2-0.10.0 0 100 200 300 400 500 600 700
Fig. 3. (Color online) (a) Drain and (b) transfer characteristics of the 200 nm AlSb/InAs HEMT. The gate width is20 2 m and the source– drain spacing is 2m. (c) gmversus VGSwith different gate lengths at VDS¼ 0:3 V.
C.-I Kuo et al. Jpn. J. Appl. Phys. 51 (2012) 060202
not confine holes, electron flows into the channel, increasing the channel current and gm.10)
The transconductance and drain–source current plotted as a function of gate voltage for devices with different gate lengths at VDS¼ 0:3 V is shown in Fig. 3(c). The peak
gm of the 200 nm device (1401 mS/mm) is slightly higher
than those of the 100 nm (1288 mS/mm) and 60 nm (1329 mS/mm) devices.
The S-parameter of the devices was measured from 2 to 110 GHz using an on-wafer probe system with an HP8510XF network analyzer. The extrinsic cutoff frequency ( fT) and maximum frequency of oscillation ( fmax) were
extracted from extrapolation of the measured current gain (H21) and Mason’s unilateral gain (U) using a 20 dB/ decade slope. The 200 nm device exhibited fT and fmax of
137 and 97 GHz at VDS¼ 0:3 V, respectively. These results
also demonstrate the feasibility of BCl3 dry etching for shallow mesa formation in Sb HEMTs fabrication.
fTas a function of gate voltage for different gate lengths is
shown in Fig. 4. As shown, high fTand fmaxwere achieved at
low bias levels for all devices due to the good transport properties in the InAs channel. Interestingly, it is observed that the 60 nm device does not significantly outperform the others as expected. The extracted intrinsic RF gm was
1250 mS/mm for the 60 nm device, 1175 mS/mm for the 100 nm device, and 1225 mS/mm for 200 nm device, which showed a similar trend to that depicted in Fig. 4. Apparently, merely scaling the gate length is not enough to boost the
fT if the gate-channel distance is not optimized with the
Lg aspect ratio, which agrees with the results of Guerra
et al.11) Another reason for this phenomenon is the
occurrence of the ballistic effect in the electron transport under the gate electrode for the 60 and 100 nm devices.12)
In summary, an ICP dry etching process using BCl3 gas has been developed to precisely control the etching depth for shallow mesa isolation in the fabrication of AlSb/InAs HEMTs. Effect of the gate lengths on device performances was also investigated. Good DC and RF performances, with an extrinsic fT=fmaxof 137/97 GHz, were achieved at VDS¼
0:3 V for 2 20 m HEMTs with a 200 nm gate length. These results demonstrate the potential of Sb HEMTs for low-voltage operation at high frequencies.
Acknowledgments The authors would like to acknowledge the assistance and support from the National Science Council, Taiwan, R.O.C., under contract NSC 99-2221-E-009-MY3 and ULVAC Corporation, Taiwan Branch. Part of this work was also supported by the ‘‘Nanotechnology Network Project’’ of the Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT).
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C.-I Kuo et al. Jpn. J. Appl. Phys. 51 (2012) 060202
