IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 21, NO. 7, JULY 2011 365
Rapid Thermal Treatment for Improving Thermal
Processing Stability of Ar-Implanted Surface
Passivated High-Resistivity Silicon
Chih-Yi Liu, Min-Hang Weng, and Jyun-Min Lin
Abstract—This study improved the thermal processing stability of Si-based coplanar waveguides (CPW) through Ar ion implan-tation with rapid thermal annealing (RTA). Ar ion implanimplan-tation damaged the surface layer of the high-resistivity silicon substrate, which decreased attenuation of the CPW line. However, the damaged layer recrystallized during a high temperature process, which caused thermal processing instability. A RTA process was performed to retard the epitaxial regrowth from the substrate, this improved thermal processing stability and decreased dc-voltage dependence of the attenuation of the CPW line. These improved properties were found to be due to the RTA process retaining more bulk traps within the damaged layer.
Index Terms—Coplanar waveguide (CPW), microwave loss, sur-face passivation, thermal processing stability, thermally-induced electrical instability.
I. INTRODUCTION
T
HROUGH the development of wireless communication technology, many products, such as the mobile phone and the global positioning system, have become important in daily life. Wireless communication systems require high performance, low cost, and miniaturized radio-frequency (RF) devices. The monolithic microwave integrated circuit (MMIC) has been implemented in integrated active devices using GaAs or silicon bipolar technology. Recent studies have attempted to integrate several passive devices on low-resistivity silicon (LRS) substrates. However, it is difficult to fabricate a low loss coplanar waveguide (CPW) structure on the high loss LRS substrates used in standard CMOS processes. Therefore, high-resistivity silicon (HRS) substrates are adopted for the integration of Si-based microwave devices [1]–[3]. However, the surface charge effect of the Si substrate causes a high attenuation and reduces the effective substrate resistance. Researchers have proposed several methods, such as trap-rich layer passivation [4] and silicon layer passivation [5], [6], to overcome these issues. Ar implantation has been intensively studied to damage the silicon surface and generate traps to reduce the dissipation of RF signal [3], [7]–[9]. Recently, attempts have been made to integrate ferroelectric microwaveManuscript received February 21, 2011; accepted April 13, 2011. Date of publication June 09, 2011; date of current version July 07, 2011. This work was supported by the National Science Council of Taiwan under project NSC 98-2221-E-151-058.
C.-Y. Liu and J.-M. Lin are with the Department of Electronic Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung 807, Taiwan.
M.-H. Weng is with the Metal Industries Research and Development Centre, Kaohsiung 821, Taiwan (e-mail: [email protected]).
Digital Object Identifier 10.1109/LMWC.2011.2151850
devices on a HRS substrate. However, the ferroelectric devices must be processed at high temperature [10], [11]. At these temperatures, Si grains recrystallize. This recrystallization caused thermal processing instability, which led to the ther-mally-induced electrical instability and increased attenuation of microwave devices [6]. Lederer et al. have proposed a rapid thermal annealing (RTA) process to delay the recrystallization of low-pressure chemical vapor-deposited (LPCVD) amor-phous silicon [12]. This study investigates the use of Ar ion implantation to damage the Si substrate so as to reduce the attenuation of CPW lines. After completion of Ar ion implanta-tion, a RTA process was performed to enhance grain formation and retard the epitaxial regrowth from the substrate during the subsequent thermal process [13] and improve the thermal processing stability of microwave characteristics of the CPW lines. A metal-oxide-silicon (MOS) structure was used in this work to analyze the status of traps within the Si grains.
II. EXPERIMENTALPROCEDURAL
P-type (100) 4 in HRS (5 - ) and LRS (1–10 - ) were used as CPW and MOS substrates, respectively. Table I shows a summary of the sample properties. After standard RCA cleaning, Ar ion implantation was performed with doses of 2 and 2 at 125 keV so as to damage the sil-icon substrates. The crystallinities of the surfaces of substrates were characterized by Raman spectra. After characterization, some substrates were subjected to a RTA process at 900 for 30 s. A 300 nm thick layer was deposited by plasma-en-hanced chemical vapor deposition (PECVD) at 300 on the HRS substrates. The layer insulated the CPW lines from the HRS. Next, some samples were annealed in nitrogen at atmospheric ambient and 900 for 4 h to investigate the thermal processing stability. Finally, a 1- -thick aluminum layer was deposited by a thermal evaporator and patterned by a photolithography process to fabricate the CPW lines. The di-mensions were a line length of 2000 , strip width of 60 , slot width of 40 and a ground plane width of 280 . The microwave characteristics of CPW lines were measured using a HP 8510C network analyzer. A standard thru-reflect-line (TRL) calibration was adopted as the de-embedding technique. MOS structures with a 10 nm thick layer were fabricated on the LRS substrates by the above mentioned processes. These were fabricated so as to characterize the trap status within the implanted Si layers. The top electrode area of the MOS structures was about 4.9 . Capacitance-voltage (C-V) characteristics of the MOS structures were recorded by a HP 4192A impedance analyzer at room temperature.
LIU et al.: RAPID THERMAL TREATMENT FOR IMPROVING THERMAL PROCESSING STABILITY 367
Fig. 4. Plots of attenuation versus bias voltage at 30 GHz for the CPW lines with and without post thermal treatments.
Fig. 5. Capacitance-voltage characteristics of the MOS structures with various post thermal treatments.
the interface. The traps within the implanted layer cap-tured the mobile carriers, which decreased the dissipation of the RF signal by mobile carriers. Therefore, the RTA process en-hanced grain growth and retarded the epitaxial regrowth from the substrate during the subsequent thermal process [13], which decreased value and dc-voltage dependence of the attenuation.
Fig. 5 shows the capacitance-voltage (C-V) characteristics of samples MOS-A, MOS-C, and MOS-D. The MOS structures were fabricated on LRS substrates using processes similar to that for samples A, C, and D. Parasitic effects of series resis-tance and inducresis-tance in the C-V measurements were reduced by adapting a LRS substrate and low frequency measurement, respectively [15]. Therefore, the C-V characteristics were recorded with a parallel capacitance-resistance (Cp-R) model at 1 kHz. In the inversion region, the capacitance of sample MOS-A was flat and about 20 pF, which indicates almost zero bulk traps within the Si substrate. However, the capacitance of sample MOS-C was larger than that of sample MOS-A; and the capacitance of sample MOS-D was larger than that of sample MOS-C. The Si grains of the sample MOS-C recrystallized during the high temperature process, thus reducing the amount of bulk traps within the implanted layer [16]. The larger capac-itance of sample MOS-D than MOS-C indicated that the RTA
process resulted in more traps retained within the implanted layer. Therefore, sample D had smaller dc-voltage dependence and a smaller attenuation.
IV. CONCLUSION
This study used Ar ion implantation to reduce the attenuation of a CPW line. However, the thermal processing stability of the Ar implanted sample was poor. To improve thermal processing stability, a RTA process was performed to suppress Si grain growth during high temperature annealing. This research also measured C-V characteristics of the MOS structure to investi-gate the trap status within the Si substrates. The RTA process retained more traps within the damaged Si layer, this improving the thermal processing stability and decreased dc-voltage de-pendence of the attenuation.
REFERENCES
[1] A. C. Reyes, S. M. El-Ghazaly, S. Dorn, M. Dydyk, and D. K. Schroder, “Silicon as a microwave substrate,” in IEEE MTT-S Int. Dig., May 1994, vol. 3, pp. 1759–1762.
[2] M. Fernandez-Bolanos, J. Perruisseau-Carrier, P. Dainesi, and A. M. Ionescu, “RF MEMS capacitive switch on semi-suspended CPW using low-loss high-resistivity silicon substrate,” Microelectron. Eng., vol. 85, no. 6, pp. 1039–1042, Jun. 2008.
[3] M. Spirito, F. de Paola, L. K. Nanver, E. Valletta, B. Rong, B. Rejaei, L. C. N. de Vreede, and J. N. Burghartz, “Surface-passivated high-re-sistivity silicon as a true microwave substrate,” IEEE Trans. Microw.
Theory Tech., vol. 53, no. 7, pp. 2340–2347, Jul. 2005.
[4] J. A. Reynoso-Hernández, R. Rangel-Rojo, M. Aceves, I. Zaldivar, L. E. Sánchez, and M. Herrera, “Influence of the SRO as passivation layer on the microwave attenuation losses of the CPWs fabricated on HR-Si,”
IEEE Microw. Wireless Compon. Lett., vol. 13, no. 12, pp. 508–510,
Dec. 2003.
[5] H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, “Low-loss CPW lines on surface stabilized high-resistivity silicon,” IEEE Microw. Guided Wave Lett., vol. 9, no. 10, pp. 395–397, Oct. 1999.
[6] B. Rong, J. Burghartz, L. Nanver, B. Rejaei, and M. van der Zwan, “Surface-passivated high-resistivity silicon substrates for RFICs,”
IEEE Electron Device Lett., vol. 25, no. 4, pp. 176–178, Apr. 2004.
[7] A. B. M. Jansman, J. T. M. van Beek, M. H. W. M. Van Delden, A. L. A. M. Kemmeren, A. den Dekker, and F. P. Widdershoven, “Elimination of accumulation charge effects for high-resistive silicon substrates,” in
Proc. Eur. Solid-State Device Res., 2003, pp. 3–6.
[8] G. Posada, G. Carchon, P. Soussan, G. Poesen, B. Nauwelaers, and W. De Raedt, “High-resistivity silicon surface passivation for the thinfilm MCM-D technology,” in Proc. 6th Top. Meeting Silicon Monolith.
In-tegr. Circuits RF Syst., San Diego, CA, Jan. 2006, pp. 46–49.
[9] A. G. Gullis, T. E. Seidel, and R. L. Meek, “Comparative study of an-nealed neon-, argon-, and krypton-ion implantation damage in silicon,”
J. Appl. Phys., vol. 48, no. 10, pp. 5188–5198, Oct. 1978.
[10] D. Kuylenstierna, M. Norling, A. Vorobiev, K. Reimann, D. Lederer, J. P. Raskin, and S. Gevorgian, “Performance of coplanar waveguides on surface passivated highly resistive silicon covered by ferroelectric thin film,” in IEEE MTT-S Int. Dig., 2007, pp. 2055–2058.
[11] Z. Quan, S. Xu, H. Hu, W. Liu, H. Huang, B. Sebo, G. Fang, M. Li, and X. Zhao, “Microstructure and electrical characteristics of Ba Sr TiO thin films etched in CF =Ar=O plasma,”
Mi-croelectron. Eng., vol. 85, no. 11, pp. 2269–2275, Nov. 2008.
[12] D. Lederer and J.-P. Raskin, “New substrate passivation method dedi-cated to HR SOI wafer fabrication with increased substrate resistivity,”
IEEE Electron Device Lett., vol. 26, no. 11, pp. 805–807, Nov. 2005.
[13] S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, vol. 1:
Process Technology, 2nd ed. Sunset Beach, CA: Lattice Press, 1999, pp. 393–396.
[14] S. Ashok, H. Kräutle, and H. Beneking, “Effect of argon ion implanta-tion dose on silicon Schottky barrier characteristics,” Appl. Phys. Lett., vol. 45, pp. 431–433, Aug. 1984.
[15] H. T. Lue, C. Y. Liu, and T. Y. Tseng, “An improved two-frequency method of capacitance measurement for the high-k gate dielectrics,”
IEEE Electron Device Lett., vol. 23, no. 9, pp. 553–555, Sep. 2002.
[16] C. Y. Liu and T. Y. Tseng, “Correlation between deep depletion and current-voltage saturation ofSrTiO gate dielectric capacitor,”
