Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices

Arsenic/Phosphorus LDD Optimization by

Taking Advantage of Phosphorus Transient

Enhanced Diffusion for High Voltage Input/Output

CMOS Devices

Howard Chih-Hao Wang, Chih-Chiang Wang, Carlos H. Diaz, Senior Member, IEEE, Boon-Khim Liew,

Jack Yuan-Chen Sun, Fellow, IEEE, and Tahui Wang, Senior Member, IEEE

Abstract—Optimization of a LDD doping profile to enhance

hot carrier resistance in 3.3 V input/output CMOS devices has

been performed by utilizing phosphorus transient enhanced

diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus

LDD nMOSFET’s with and without TED are characterized

comprehensively. Our result shows that the substrate current in a

nMOSFET with phosphorus TED can be substantially reduced,

as compared to the one without TED. The reason is that the TED

effect can yield a more graded n

LDD doping profile and thus a

smaller lateral electric field. Further improvement of hot carrier

reliability can be achieved by optimizing arsenic implant energy.

Secondary ion mass spectrometry analysis for TED effect and

two-dimensional (2-D) device simulation for electric field and

current flow distributions have been conducted. The phosphorus

TED effects on transistor driving current and off-state leakage

current are also investigated.

Index Terms—Hot carriers, MOS devices, transient enhanced

diffusion.

I. I

I

NPUT/OUTPUT (I/O) devices with higher operation

voltage are demanded along with high-performance and

low-voltage core devices in today’s CMOS technology. This

requirement has stimulated considerable efforts toward the

development of dual gate-oxide process, i.e., thinner gate oxide

for core devices and thicker gate oxide for I/O devices. To

minimize processing cost, I/O devices and core devices usually

share the same substrate architecture, thus eliminating the need

for extra well photo mask. Short channel effect (SCE) has been

a major limiting factor for core device design. Super-steep

Manuscript received May 17, 2001; revised August 27, 2001. H. C.-H. Wang and T. Wang were supported by the National Science Council, Taiwan, R.O.C., under Contract NSC89-2215-E009-034.

H. C.-H. Wang is with the Device Technology and Modeling Department, R&D, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. and also with the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).

C.-C. Wang, C. H. Diaz, and B.-K. Liew are with the Device Technology and Modeling Department, R&D, Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan, R.O.C. (e-mail: [email protected]).

J. Y.-C. Sun is with the Logic Technology Division, R&D, Taiwan Semicon-ductor Manufacturing Company, Hsinchu, Taiwan, R.O.C.

T. Wang is with the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, R.O.C.

Publisher Item Identifier S 0018-9383(02)00219-8.

retrograde channel, shallow source/drain junction, and pocket

implants are necessitated to achieve better control of short

channel effect [1]–[3]. These process schemes, however, are

detrimental to device hot carrier reliability [4]. In core devices,

hot carrier effects can be relieved by using reduced supply

voltage

V whereas hot carrier reliability in I/O devices

becomes a major challenge in dual gate-oxide process.

The design and the fabrication procedure of a lightly doped

drain (LDD) are important to I/O device reliability. A hybrid

arsenic/phosphorus (As/P) LDD structure is currently adopted

for high voltage I/O transistors [5]. Due to the low diffusivity,

arsenic is preferred in forming shallow junctions with a steep

doping distribution. On the other side, the abruptness of the

ar-senic junction increases the peak electric field in the channel

and deteriorates hot carrier resistance. The use of phosphorus

in LDD implant can help grading the n

LDD doping profile

and results in a smaller electric field. By modifying the

phos-phorus diffusion behavior, one can further improve device hot

carrier reliability. In this paper, it is our intention to optimize

the arsenic/phosphorus LDD doping profiles by utilizing an

en-hanced phosphorus diffusion mechanism.

It has been reported that supersaturated silicon interstitials

can be introduced during source/drain extension and pocket

im-plants, which give rise to anomalous transient enhanced

diffu-sion (TED) in the early stage of the subsequent thermal cycle

[6]. The diffusivity enhancement can be orders of magnitude

higher than the intrinsic value [7]. In order to ensure a desired

dopant profile in pocket and S/D extension regions in core

de-vices, rapid thermal anneal (RTA) prior to sidewall spacer

for-mation is necessary to suppress the TED effects [8], [9]. On the

contrary, phosphorus TED effect [10], [11] is advantageous in

certain aspects in I/O devices since it can grade the n

LDD

doping profile and improves hot carrier reliability [12]. A

com-prehensive study of the phosphorus TED effects on the n

junc-tion profile, hot carrier reliability, driving current and off-state

leakage current in I/O devices will be performed. Various As/P

LDD nMOSFET’s with and without TED are fabricated. Effects

of arsenic LDD implant energy are investigated. SIMS

anal-ysis and two-dimensional (2-D) device simulation are also

con-ducted.

II. D

F

To explore the phosphorus TED effect, two process sequences

are employed for a deep submicron dual gate-oxide CMOS

tech-nology (Table I). In process A, RTA is applied after S/D

exten-sion and pocket implants for core devices and the As/P LDD

implant for I/O devices. In process B, the sequence of the As/P

LDD implant and RTA is reversed and other steps are the same.

It should be noted that the I/O devices in process B will have

phosphorus TED during subsequent nitride spacer deposition

but core devices in process A and B have exactly the same

fab-rication procedures. The nitride spacer deposition temperature

and time are 750 C and 2 hours respectively. Four kinds of

I/O devices are fabricated with the two processes. Device A1 is

made with process A and device B1 is with process B. Device

A2 is the same as device A1 except that the phosphorus dosage

is increased by 20%. Device B2 is the same as device B1

ex-cept for arsenic implant energy being two times higher. All the

samples have a gate oxide thickness of 70

. The gate length is

from 0.26 m to 0.5 m. The supply voltage for the I/O devices

is 3.3 V.

III. R

& D

A. Effects of Phosphorus TED

The SIMS result of the phosphorus doping profiles after all

of processes in A1, A2, and B1 devices are drawn in Fig. 1. The

-axis in the figure denotes the depth in substrate. Device B1

apparently has a more graded phosphorus doping profile than

A1 and A2 due to TED. Note that adding phosphorus dose

(de-vice A2) simply increases the doping level, but does not affect

the slope of the profile. The phosphorus TED effect on substrate

current

in a 0.35 m gate-length device is shown in Fig. 2.

The measurement drain bias is 3.6 V (10% above the supply

voltage for over-stress). Devices A1 and A2 (without TED) have

nearly the same substrate current while device B1 (with TED)

has a smaller substrate current. The substrate current reduction

is nearly 30%. This remarkable reduction is in agreement with

the SIMS profile in Fig. 1. The simulation result from MEDICI

[13] in the inset of Fig. 2 also confirms a smaller lateral

elec-tric field in device B1. From the result, it can be concluded

Fig. 1. Phosphorus SIMS profiles after all of processes. Thex-axis denotes the depth in substrate.

Fig. 2. Substrate current versus gate bias in 0.35m gate length devices.

V = 3:6 V. Simulated lateral electric field at V = 3:6 V and V = 1:8 V

is shown in the inset.

Fig. 3. Maximum transconductance degradation versus stress time. The stress drain bias is 4.5 V and gate bias is 2.1 V.

that phosphorus TED can be utilized as a more effective

ap-proach to improving hot carrier resistance, as compared to other

methods such as a straight phosphorus dose change. In Fig. 3,

we present the stress-time dependence of hot carrier

transcon-ductance

degradation in the three devices. The stress is

performed in a maximum

condition, i.e.,

V and

Fig. 4. Normalized maximum substrate current(I =I ) plotted against gate length.

Fig. 5. Maximum substrate current versus drain saturation current.

V for accelerated degradation. All the devices

ex-hibit a power-law degradation rate. The power factor is about

0.4. The hot carrier lifetime, defined as 10%

degradation,

is 360 s for device A1 and 1000 s for device B1. Thus, an

im-provement of hot carrier lifetime by three times is obtained in

device B1 owing to the phosphorus TED.

The phosphorus TED effect in different gate length devices is

examined in Fig. 4.

is normalized to the source current in

the figure. Evidently, device B exhibits smaller

for gate

lengths from 0.26 m to 0.5 m. The current driving capability

of the three devices is also compared. For a 0.35 m device, the

drain saturation current

in device B1 is slightly larger

than in device A1 for two reasons; First, the effective channel

length in device B1 is shorter due to TED. The extracted

effec-tive channel length is 0.289 m and 0.267 m for device A1 and

B1 respectively. Secondly, the LDD series resistance is

domi-nated by arsenic implant condition and is therefore not affected

by the phosphorus doping profile. In Fig. 5, maximum

is

plotted against

for various gate lengths.

It should be mentioned that phosphorus TED has minimal

adverse effect on off-state drain leakage current

. For

ex-ample, the measured drain leakage current in a 0.35 m device

at

V and

V is 0.23 pA

m in device A1,

0.26 pA

m in device B1 and 0.29 pA

m in device A2.

versus

characteristics for the three devices of various gate

lengths is plotted in Fig. 6. Threshold voltage

roll-off

char-acteristics is also examined in Fig. 7. No significant difference

is observed for a gate length down to 0.3 m.

Fig. 6. I versus I characteristics for devices of various gate lengths.I is measured atV = 3:6 V and V = 0 V.

Fig. 7. Threshold voltage rolloff characteristics for the three devices.

Fig. 8. Maximum substrate current versus drain saturation current. B1 and B2 both have phosphorus TED but have different arsenic implant energy.

B. Optimization of Arsenic Implant

Based on prior work [5], increasing the arsenic dose in

hybrid LDD aggravates hot carrier reliability because of a

more abrupt junction. In this work, due to a deeper phosphorus

junction caused by phosphorus TED, we can increase arsenic

implant energy for further optimization. Device B2 is

fabri-cated with two times higher arsenic implant energy than B1.

Further reduction of

is demonstrated in Fig. 8. Fig. 9

compares the current path and the electric field contours in

B1 and B2 obtained from a 2-D simulation. The shaded area

represents an avalanche region with impact ionization rate

cm

s

. In Device B2, the high field region

moves deeper into the substrate. The current path is therefore

separated from the high field region, thus leading to a smaller

Fig. 9. Simulated lateral electric field contours and current path near the drain atV =V = 3:6 V=1:8 V for device B1 and B2. Shadowed area indicates an avalanche region with impact ionization rateR > 10 cm s .

avalanche region than in device B1. As a result, better hot

carrier reliability can be obtained by higher arsenic implant

energy. The hybrid LDD junction depth is still determined

by the phosphorus profile although arsenic implant energy is

higher. No obvious degradation of

roll-off characteristics is

found down to gate length of 0.3 m.

IV. C

We have proposed a process flow to take advantage of

phos-phorus TED to form a more graded LDD junction in I/O CMOS

devices. By using this approach, substantial improvement of

hot carrier resistance has been achieved. This process can

ef-fectively widen the performance-reliability window for I/O

de-vice design while maintaining suitability for core dede-vice

devel-opment. With phosphorus TED and thus a deeper LDD junction,

arsenic implant energy can be increased to further improve hot

carrier reliability.

A

The SIMS measurement by TSMC’s Failure Analysis

Labo-ratory is greatly acknowledged.

R

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[13] Avanti Medici 2000.2 Manual, ch. 2.

Howard Chih-Hao Wang was born in Taipei,

Taiwan, R.O.C., in 1969. He received the B.S. degree in electronic engineering from National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 1992. Since 1997, he has been pursuing the Ph.D. degree in the Department of Electronic Engineering, NCTU.

In 1995, he joined Taiwan Semiconductor Manu-facturing Company (TSMC), Hsinchu, where he was initially responsible for the process integration and yield enhancement of 0.6m and 0.5 m logic tech-nology. Since 1997, he was involved in the device design in the Device Tech-nology and Modeling Department at TSMC. He is currently working on the development of high-speed 0.1m CMOS device technology. His research in-terests involve device design and characterization for high-performance VLSI logic.

Chih-Chiang Wang received B.S. degree in physics

science from catholic Fu-Jen University, Taiwan, R.O.C., and the M.S. degree in electro-optical engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1989 and 1991, respectively. In 1991, he joined Electronics Research and Service Organization (ERSO/ITRI) and worked for DRAM device design. Since 1998, he has worked at R&D group, Taiwan Semiconductor Manufacturing Com-pany, Hsinchu. He has been engaged in process and device calibration/simulation for deep submicron technology.

Carlos H. Diaz (SM’98) received the M.S. and B.S.

degrees in electrical engineering and physics from Universidad de Los Andes, Bogota D.C., Colombia, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign.

He joined the Taiwan Semiconductor Manufac-turing Company (TSMC), Hsinchu, Taiwan, R.O.C., in 1998 as a project manager for FEOL integration in 0.18m technology. Since 1999 he has been the program manager for Advanced Device Technology and TCAD responsible for design/integration of TSMC’s logic transistor technology. Before joining TSMC, he was Member of Technical Staff, ULSI Laboratory, Hewlett-Packard Laboratories, Palo Alto, CA, working on process integration and device design since 1995. Before this, he was with Integrated Circuits Business Division at Hewlett-Packard working on physics reliability. He holds six U.S. patents, has published more than 40 papers in technical journals and international conferences, and has co-authored one book.

Dr. Diaz has been member of the Technical Program Committees for VLSI Technology Symposium, IEEE International Reliability Physics Symposium, and EOS/ESD Symposium.

Boon-Khim Liew received the B.S. degree from the

California Institute of Technology, Pasadena, in 1985 and the Ph.D. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1990.

From 1990 to 1993, he worked at Cypress Semi-conductor as a Senior Technology Engineer in device engineering, responsible for MOS transistor design, device reliability, ESD and latch-up. From 1993 to 1995, he founded BTA Technology, Inc. and served as the President and CEO. At BTA, he was respon-sible for the development, marketing of simulation and SPICE modeling soft-wares. In December, 1995, he joined Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, R.O.C., as the department manager for de-vice technology and modeling. His responsibility includes advanced transistor design, SPICE modeling and TCAD simulation.

Jack Yuan-Chen Sun (S’79–M’83–SM’91–F’00)

received the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 1983.

He is presently Senior Director of Logic Technology Division at Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan, R.O.C. In the last three years, he has led the successful expansion and acceleration of TSMC low-voltage, high-performance, and low-power logic technology roadmap, e.g. cutting edge 0.18, 0.15, 0.13, and 0.1m logic families. He has 23 years of experience in Si IC technology, including R&D, technology transfer, and product qualification. He led many successful R&D projects that set world records and/or shape industry trends in CMOS, SOI, low-power CMOS, low temperature CMOS, bipolar, and SiGe HBT. He has authored and co-authored over 200 papers and many invited papers in technical journals and conferences. He holds eight U.S. patents and four IBM invention achievement awards.

Dr. Sun is an IEEE Fellow in recognition of his significant contribution to CMOS technology. He served as mentors of several SRC projects. He was an SRC PID TAB alternate member for IBM. He was a member (1995, 1996) and the chair (1997) of the CMOS subcommittee for IEDM. He is the chair of the PIDS TWG of TSIA and the TSIA representative in the ITRS PIDS TWG. He was a lecturer for a hot carrier reliability course at UC Berkeley Extension. He has authored and co-authored over 200 papers and many invited papers in tech-nical journals and conferences. His latest invited papers are “Foundry Tech-nology for the Next Decade” at 1998 IEDM, “CMOS TechTech-nology for 1.8 V and Beyond” at the 1997 International Symposium on VLSI Technology, Systems, and Applications.

Tahui Wang (M’85–SM’94) was born in Taoyuan,

Taiwan, R.O.C., on May 3, 1958. He received the B.S.E.E. degree from National Taiwan University, Taipei, in 1980 and the Ph.D. degree in electrical engineering from the University of Illinois, Ur-bana-Champaign, in 1985.

From 1985 to 1987, he was with Hewlett-Packard Laboratories, Palo Alto, CA, where he was engaged in the development of GaAs HEMT devices and cir-cuits. Since 1987, he has been with the Department of Electronics Engineering, National Chiao-Tung Uni-versity, Hsinchu, Taiwan, where he is currently a Professor. His research inter-ests include hot carrier phenomena characterization and reliability physics in VLSI devices, RF CMOS devices and nonvolatile semiconductor devices.

Dr. Wang was granted the Best Teacher Award by the Ministry of Education, R.O.C. He has served as technical committee member of many international conferences, among them IEDM and IRPS. His name was listed in Who’s Who in the World in 2001.