Abstract—For integrated circuits (ICs) with voltage
program-ming pin (VPP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the VPP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to
VDDcannot be applied to suchVPPpin. In this work, a new ESD
protection design is proposed to improve ESD robustness ofVPP pin with the consideration of the mistriggering issue whenVPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
Index Terms—Electrostatic discharge (ESD), voltage
program-ming pin(VPP).
I. INTRODUCTION
O
NE-TIME PROGRAMMING (OTP) read-only memory (ROM) has been widely implemented in micro-con-trollers (MCUs) [1]. To successfully program the memory cells, a high voltage (HV) on the voltage programming pin ( pin) is necessary to induce channel hot electrons or to burn out the fuse [2], [3]. Because the programming voltage ( ) is higher than the normal operating voltage ( ) of internal circuits, current paths from the pin to the power supply line are not allowable. With the forbidden current path from pin to power supply line, the pin poses a stringent challenge in electrostatic discharge (ESD) protection design.ESD-induced failure has been one of the most serious re-liability issues affecting yields of IC products. As a result, on-chip ESD protection circuits have been an essential design in present-day ICs [4]. Dedicated process steps or mask layers
Manuscript received July 31, 2010; revised November 10, 2010; accepted November 15, 2010. Date of publication January 06, 2011; date of current ver-sion January 28, 2011. This paper was approved by Associate Editor Domine M. W. Leenaerts. This work was supported by ELAN Microelectronics Cor-poration, Taiwan, and supported in part by the Ministry of Economic Affairs, Taiwan, under Grant 99-EC-17-A-01-S1-104, and in part by the “Aim for the Top University Plan” of National Chiao-Tung University and Ministry of Edu-cation, Taiwan, R.O.C.
M.-D. Ker is with the Nanoelectronics and Gigascale Systems Laboratory, In-stitute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan. He is also with the Department of Electronic Engineering, I-Shou University, Kaoh-siung, Taiwan (e-mail: [email protected]).
W.-Y. Chen is with the Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
W.-T. Shieh and I-J. Wei are with ELAN Microelectronics Corporation, Hsinchu 30076, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2096114
for ESD protection such as silicide blocking (SB) are often omitted in CMOS ICs to reduce the fabrication cost [5]–[8]. Without the SB on ESD protection devices, fully-silicided ESD protection MOS field-effect transistors (MOSFETs) have been reported with poor ESD robustness [4], [8]. An efficient ESD protection design for fully-silicided ICs with the voltage programming pin is therefore a highly challenging reliability issue to IC designers [9], [10].
In this work, a new ESD protection design for fully-silicided pin is proposed, which includes a circuit design to avoid the mistriggering of the ESD protection device during the pro-gramming conditions when has a fast rise time. The pro-posed ESD protection design has been successfully verified on a commercial IC product with OTP memory cells in a 0.35 m fully-silicided CMOS process.
II. DESIGN CONSIDERATIONS OF VOLTAGE
PROGRAMMINGPINS
A. OTP Memory Cells
To electrically program the OTP memory cells, Fig. 1 depicts the required bias conditions on the memory unit (nMOS cell) which has a control gate and a floating gate. Before program-ming, there is no charge or only a few charges in the floating gate. The original threshold voltage of a non-programmed nMOS cell is defined as . is smaller than 5 V so that the nMOS cell can be turned on (channel can be induced) when the control gate is biased at 5 V [Fig. 1(a)]. To program the nMOS cell, a high gate bias of 12.5 V ( voltage) is applied on the control gate and the drain of nMOS cell is biased at of 5 V. With the high gate bias of 12.5 V on the control gate, electrons permitted from the source can pass through the insulating layer beneath the floating gate to be accumulated in the floating gate [Fig. 1(b)]. After a span of field programming time, the 12.5 V voltage is removed and the electrons that accumulated in the floating gate are trapped in the floating gate. The trapped electrons in the floating gate can substantially increase the threshold voltage of the nMOS cell from to . As long as the number of electrons trapped in the floating gate is large enough (the programming time is long enough), can be higher than 5 V. Consequently, the channel of nMOS cell can no longer be induced by 5 V gate bias, and the nMOS cell becomes an open circuit after programming, as shown in Fig. 1(c). By exploiting this principle, on-chip memory arrays can be programmed to represent different digital codes to calibrate IC products or to predefine different IC functions to broaden their application scopes [11].
Fig. 1. (a) Normal operating condition of the memory unit before programmed. Channel can be induced underV of 5 V and V of 5 V. (b) Bias conditions of the memory unit during programming. A high control gate bias of 12.5 V is used to draw channel hot electrons into the floating gate. (c) Normal operating condition of the memory unit after programmed. Channel can not be induced underV of 5 V and V of 5 V due to the trapped electrons in the floating gate.
B. Programming Waveforms
To design an ESD protection circuit for voltage programming pins, it is essential to understand the and program-ming waveforms. The typical measured and pro-gramming waveforms are shown in Fig. 2. Under the pro-gramming condition, voltage is charged up from 0 V to 5 V before the onset of voltage ramping, so that internal circuits such as control logic or address decoder can function properly. After the voltage has been charged to 5 V, the programmer pulls the voltage high from 0 V to 12.5 V, as shown in Fig. 2.
Fig. 2. Measured voltage waveforms on V and V pins during programming.
Fig. 3. Traditional whole-chip ESD protection scheme with the power-rail ESD clamp circuit. The diodeD results in an unwanted leakage current path when I/O voltage is higher than theV voltage during some special circuit operating conditions.
To comprehensively protect input/output (I/O) pins against ESD stresses, efficient current paths to discharge ESD stress energy at I/O pins are necessary. Because electrostatic charges may be either positive or negative, there are four ESD test modes at I/O pins with respect to the grounded or (GND) pins. The four ESD test modes are PS (posi-tive-to- ), PD (positive-to- ), NS (negative-to- ), and ND (negative-to- ) modes [12]. A typical rail-based ESD protection scheme is shown in Fig. 3 [13], [14], where two diodes and are used to divert ESD stress energy at the I/O pad to the or the GND power supply lines. Because the power-rail ESD clamp circuit is especially designed with a large ESD protection device , it is effective to discharge ESD energy between power supply lines [13]–[15]. Through the and diodes in cooperation with the power-rail ESD clamp circuit, the rail-based ESD protection scheme has been reported as an effective method to significantly improve ESD robustness of the I/O pin. However, since the 12.5 V voltage is higher than the 5 V voltage during program-ming, the diode that diverts the high voltage to the power supply line is prohibited. Otherwise, the memory cells cannot be successfully programmed due to insufficient voltage on the pin. Without the diode , the power-rail ESD clamp circuit cannot help discharge ESD energy at the I/O pad under PS- and PD-mode ESD tests. Accordingly, I/O pins without a forward diode from the I/O pad to the power supply line usually have a low ESD protection level, especially under PS- and PD-mode ESD tests. Mixed-voltage I/O buffers where I/O voltages would be higher than their voltages suffer the same limitation, as well [16].
onds in different programming environments [17], [18]. Because the rise time of ESD voltage has the same timescale as that of fast programming voltage (several tens of nanoseconds), some of traditional ESD protection designs could be mistriggered by their ESD trigger circuits. A primary ESD protection pMOS with an RC timer to control its gate voltage was reported to protect the programming pin [19]. The RC timer should have a time delay over several hundreds of nanoseconds, so that the gate of ESD protection pMOS can be kept low to turn on pMOS during the ESD transition. However, when the rise time of the programming voltage is also in the same scale as that of ESD transient voltage, the simple RC timer directly connected to the programming pin cannot distinguish between the normal programming event and the ESD transition event. The ESD protection pMOS in [19] would be turned on both during programming and ESD transition. The turned-on pMOS during the programming event will pull down the voltage to cause a false programming result. Additional modification should be added into the design of [19] to avoid the false programming issue when the programmer provides the programming voltage pulse with a fast rise time. To avoid the mistriggering issue and make ICs comprehensively compatible to programmers from dif-ferent manufacturers, a wide range of acceptable voltage rise times during programming is requested by customers.
C. Previous ESD Protection Design for Pin
A previous ESD protection design for the pin used in some IC products is shown in Fig. 4. Without any ESD trigger circuit in this ESD protection design, both the ESD protection devices, the field oxide device (FOD) and the diode , are in-sensitive to the rise time of programming voltage. Under ND- and NS-mode ESD tests, the power-rail ESD clamp cir-cuit and the diode provide effective ESD discharging paths. Under PS-mode ESD test, ESD voltage induces breakdown of the diode to conduct ESD current through the reverse-biased junction of . A FOD device is placed between the pin and the line, so that PD-mode ESD energy can be di-rectly discharged to the grounded line through the n-p-n bipolar junction transistor (BJT) inherent in the FOD [20]. Be-cause the diode inherent in the FOD device has a breakdown voltage higher than 12.5 V, the FOD device does not result in current path from the pin to the line during program-ming. Under PS-mode ESD test, FOD can help divert some ESD energy to the line, and it can be further discharged to the grounded GND through the power-rail ESD clamp cir-cuit. By using this previous ESD protection design, the mea-sured human-body-model (HBM) ESD protection level on the
pin is only 2 kV verified in an IC product.
Fig. 4. Previous ESD protection design forV pin. It can be safely pro-grammed with fastV voltage rise time but has a lower ESD protection level of only 2 kV in HBM.
Fig. 5. SEM image of the previous ESD protection design after 2.5 kV PS-mode ESD test. ESD failure locations were found on both the FOD device and the diodeD .
A scanning electron microscope (SEM) image of the previous ESD protection design after 2.5 kV PS-mode ESD test is shown in Fig. 5. ESD failure locations were found on both the FOD device and the diode . Failure analysis (FA) verified that the FOD device can help discharge ESD energy under PS-mode ESD test. The previous ESD protection design can provide the typical HBM ESD protection level of 2 kV to the IC product, but the specified HBM ESD protection level has recently been in-creased from 2 kV to 4 kV by customers with high reliability re-quirements. Due to the lack of an ESD trigger circuit in the pre-vious ESD protection design, further enlarging the device width of the FOD did not improve the HBM ESD protection level due to the well-known nonuniform triggering phenomenon [21]. Moreover, for cost reduction, silicide blocking (SB) was not used in such IC products. Without SB, severe current crowding phenomena and current filamentation have been reported to fur-ther deteriorate the linearity of ESD robustness to the device dimension of an ESD protection device [4]. ESD trigger tech-niques have been reported to effectively relieve the negative im-pact on ESD robustness due to silicidation [21]–[23]. Accord-ingly, with the inability to meet the new requirement of 4 kV HBM ESD protection level by the previous ESD protection de-sign, a new ESD protection design is proposed in this work. The new proposed ESD protection design can not only exploit the ESD trigger technique to achieve high ESD robustness, but also avoid the mistriggering of an ESD protection device under programming voltage with a fast rise time.
Fig. 6. The proposed ESD protection design forV programming pin.
Fig. 7. Layout top view of the proposed ESD protection design forV pin, which was realized in a 0.35m fully-silicided CMOS process.
III. NEWPROPOSEDESD PROTECTIONDESIGN FORVOLTAGE
PROGRAMMINGPINS
The new proposed ESD protection design on pin is com-posed of a snapback ESD protection device , an ESD trigger circuit ( , , , and ), an ESD bus, two diodes ( and ), and a fail-safe nMOS , as shown in Fig. 6. The ESD trigger circuit in the proposed design is con-nected to the pin through the ESD bus and the diode . The output of the ESD trigger circuit is connected to the sub-strate of to fulfill the substrate-triggered technique [21]. The floor plan of the proposed ESD protection design in an IC product realized in a 0.35 m fully-silicided CMOS process is shown in Fig. 7. Device dimensions of the proposed ESD protec-tion design and the power-rail ESD clamp circuit used in the IC product are listed in Table I. In the proposed ESD protection de-sign, , , , and are HV symmetry devices that have thick gate oxide and lightly doped n-drift (for HV nMOS) or p-drift (for HV pMOS) regions at source/drain to sustain the high programming voltage [24], [25].
During normal circuit operating conditions, the pin is biased at 5 V and the pin is either 0 V or 5 V. Through the diode, the ESD bus is charged up to a voltage level close
TABLE I
DEVICEDIMENSIONS OF THEPROPOSEDESD PROTECTIONDESIGN
USED IN THEIC PRODUCT
to of 5 V. The resistor passes the voltage on ESD bus to the node A during normal circuit operating conditions. With the same source voltage and gate voltage on , is kept off and the output current from the ESD trigger circuit to the trigger node is 0 A. With the gate of being grounded, is safely kept off during normal circuit operating condi-tions without interfering I/O signals at pin.
Under programming where the voltage has a slow voltage rise time ( in the order of microseconds), voltage on the node A can follow up the voltage transition because the time delay from and in Fig. 6 is smaller than the voltage rise time. Consequently, is safely kept off when is slow, and is off as well. The pro-posed ESD protection design therefore does not interfere with programming when is slow. However, when the programming voltage has a rise time as fast as several tens of nanoseconds, can no longer follow up the voltage tran-sition on pin. Because the ESD protection nMOS in the proposed design is with substrate-triggered design, the amount of substrate-triggered current that flows into the trigger node could turn on parasitic BJT inherent in . Accordingly, to suppress the current that may falsely flow into the substrate of
during fast voltage rising, a fail-safe nMOS was added at the output of ESD trigger circuit. The gate of is connected to through the resistor so that is kept on during programming to provide a low-impedance
Fig. 8. Measured voltage waveforms onV pin during programming with (a) slowT of 2s and (b) fast T of 25 ns.V was biased at 5 V during the tests.
current path to shunt any output current to ground. can thus stabilize ground potential of the trigger node to pre-vent from being mistriggered during programming. Because the drain of is connected to the trigger node, par-asitic and body diode of keeps the drain of at a low voltage level. Without a high voltage across , it was realized with a low-voltage device to maximize its capability of stabilizing the trigger node during programming with a fast rise time. Moreover, the initial voltage at node A is biased at through the diode and the ESD bus, which reduces the overdrive voltage to suppress the amount of mistrig-gering current that may falsely flow into the trigger node due to fast programming voltage.
To verify the ability of the proposed design against mistrig-gering during programming, 0-to-12.5 V voltage pulses with different pulse rise times were applied to the pin of the IC product realized in 0.35 m CMOS process. was biased at 5 V during the tests. Fig. 8(a) and (b) shows the measured voltage waveforms on pin with slow (2 s) and fast (25 ns) input voltage rise times, respectively. Both mea-sured voltages on the pin were successfully ramped up to 12.5 V, which has verified that the mistriggering issue of was successfully prevented in the new proposed ESD protection design.
IV. IMPLEMENTATION ANDESD TESTINGRESULTS
A. Ballast Layout to Fully-Silicided High-Voltage nMOS
In a multi-finger nMOS, different distances from the drain region of each finger to the grounded guard ring result in asym-metry of substrate resistance , which causes the central
Fig. 9. (a) Device cross-sectional view and (b) layout top view of the high-voltage ESD protection nMOS(M ) with P+ trigger node and the N-well ballast layout realized in a fully-silicided CMOS process.
fingers of nMOS to be more easily triggered on under ESD stresses [21]. After triggering of the central fingers under ESD stresses, the ESD overstress voltage is clamped down by these earlier turned-on fingers. Without sufficient ballast resistance, it is highly possible that the central fingers are burned out before the clamped voltage is large enough to trigger the remaining fingers of the nMOS [6], [8]. As a result, ESD current is concentrated in some earlier turned-on area and the rest of the area cannot be triggered on in time to discharge the ESD current. Such nonuniform turn-on behavior among the multiple fingers of nMOS limits its ESD robustness, even if the nMOS was drawn with a large device dimension. By introducing the ballast resistance to balance the turn-on resistance of the multi-finger nMOS, turn-on uniformity of the multi-finger nMOS during ESD stresses can be improved [6]. Moreover, it has been reported that by increasing the ballast resistance, the ESD current path can be spread deeper into the substrate of a large volume, which in turn improves ESD robustness as well [26]. As a result, sufficient ballast resistance can force ESD current to be conducted into the deeper substrate to have a better heat dissipation, and also increase the ESD robustness due to the improvement of turn-on uniformity among the multiple fingers of nMOS.
Since SB is not used in this work for cost reduction, the N-well ballast layout was applied to adequately increase ballast
Fig. 10. ESD current discharging path under (a) NS-, (b) ND-, (c) PS-, and (d) PD- mode, ESD test atV pin with the new proposed ESD protection design. The dashed lines denote the substrate-triggered current to trigger on the ESD protection deviceM . The solid lines show the primary ESD current flow.
circuit (Trigger Node in Fig. 6), so the is implemented with substrate-triggered design to further improve its ESD pro-tection level. A layout top view of is shown in Fig. 9(b). No additional mask layers or process steps are required to implement this ESD device in a fully-silicided CMOS process.
B. ESD Discharging Paths
Current discharging paths of the proposed ESD protection design to protect the pin against the four I/O ESD test modes are illustrated in Fig. 10(a)–(d). Under NS-mode ESD test, the ESD current is discharged through the P-substrate/N+ diode inherent in [Fig. 10(a)]. Under ND-mode ESD test, the ESD current is discharged through the power-rail ESD clamp circuit, the GND line, and the [Fig. 10(b)]. Because the is efficient in discharging ESD energy under forward conduction conditions and the gate-driven in the power-rail ESD clamp circuit has a large device dimension of m m, the pin can have high ESD robustness under the NS- and ND-mode ESD tests.
Under PS-mode ESD test, initial ESD energy is diverted to the ESD bus through the diode to elevate the voltage level on the ESD bus. The time delay from and keeps the node A at a low voltage level relative to that of the ESD bus. Con-sequently, is turned on to provide substrate-triggered cur-rent into P+ trigger nodes of , as the dashed line
shown in Fig. 10(c). The substrate-triggered current can effi-ciently trigger on the parasitic n-p-n BJT inherent in , and the PS-mode ESD current is primarily discharged to the grounded GND line through the parasitic BJT. Under PD-mode ESD test, the ESD trigger circuit can provide substrate-triggered current to turn on as well. The PD-mode ESD current is therefore discharged to the grounded line through the substrate-triggered , the floating GND line, and the parasitic diode inherent in [Fig. 10(d)].
C. ESD Measurement Results
Among the ESD current discharging paths, it is known that PS- and PD-mode ESD tests are critical to pin ESD pro-tection because the ESD current is primarily discharged through the parasitic BJT inherent in the fully-silicided . The pro-posed ESD protection design under PS-mode ESD stresses was evaluated by using 100 ns transmission-line-pulse (TLP) system [28]. Failure criterion during TLP test was defined with 1 A leakage current under 5 V bias on pin. With the substrate-triggered technique, the parasitic BJT inherent in was trig-gered on at 10 V, and the measured secondary breakdown cur-rent was 3.8 A, as shown in Fig. 11. Measured HBM ESD pro-tection levels of the IC product equipped with previous ESD
Fig. 11. TLP-measured I–V characteristics of the proposed ESD protection de-sign under PS-mode ESD stress.
TABLE II
MEASUREDHBM ESD ROBUSTNESS OF THEIC PRODUCTWITHPREVIOUS
ESD PROTECTIONDESIGN OR THEPROPOSEDESD PROTECTIONDESIGN ATV PIN
protection design (Fig. 4) or the new proposed ESD protection design (Fig. 6) at pin are summarized in Table II. In the HBM ESD tests, the starting test voltage was 0.5 kV, and the step voltage was 0.5 kV. The pin was stressed three times at each HBM ESD level. The shift of I–V curve is the typical failure criterion used in the HBM ESD tests. Before ESD stress, a 25 V voltage sweep with limited current supply was applied on pin to acquire a fresh I–V curve as the reference. An-other post-stress I–V curve was measured and compared to this fresh I–V curve after the pin had been stressed three times at each selected ESD test level. It was judged as failure when the post-stress I–V curve deviated more than 20% from its fresh
I–V curve.
With the PS- and PD-mode test results on the pin listed in Table II, the substrate-triggered technique in collaboration with the N-well ballast layout can successfully enhance the turn-on speed and turn-on uniformity of . Therefore, HBM ESD protection levels can be significantly increased up to 5 kV. For NS- and ND-mode ESD tests, because the device dimen-sion of the parasitic diode is larger than that of the diode in the previous ESD protection design, the proposed ESD protection design showed a higher HBM ESD protection level of over 8 kV. From the measurement results shown in Table II, the custom-specified 4 kV HBM ESD protection level has been successfully achieved by the proposed ESD protection design. A die photograph of the IC with the proposed ESD protection design is shown in Fig. 12, with a die size of 3.72 mm . The layout area of the proposed ESD protection circuit for the pin is 24,186 m , where occupies a silicon area of 15,900 m .
Fig. 12. Die photograph of the IC with proposed ESD protection design atV pin. Technology node used in this work is a 0.35m fully-silicided CMOS process with OTP memory cells.
Fig. 13. (a) OBIRCH and (b) SEM images of theV pin with the proposed ESD protection design after 5.5 kV PD-mode HBM ESD stress.
The pin with the proposed ESD protection design after 5.5 kV PD-mode HBM ESD test was analyzed by optical beam induced resistance change (OBIRCH) and SEM, as shown in Fig. 13(a) and (b), respectively. OBIRCH analysis revealed the location of ESD damage on the ESD protection nMOS . No light spots (no ESD damage) were found on internal circuits or the ESD trigger circuit. SEM analysis further confirmed that ESD failure spots were located on . These failure analyses have verified that the proposed ESD protection design at pin is effective to protect internal circuits from being damaged by ESD stresses.
V. CONCLUSION
Due to the high programming voltage on pin, the place-ment of ESD diode from I/O pad to is prohibited, which results in a stringent ESD design challenge for pin. More-over, the rise time of programming voltage could be as fast as several tens of nanoseconds to cause mistriggering issue in some traditional ESD protection designs. In this work, a new ESD protection design has been proposed to overcome the mis-triggering issue due to fast programming voltage. A low-voltage nMOS was added at the output of ESD trigger circuit to overcome the mistriggering issue on the ESD protection de-vice during programming. Moreover, ESD bus in the pro-posed design can help prevent the mistriggering issue as well by reducing the overdrive current from ESD trigger circuit. The proposed ESD protection design has been successfully imple-mented on a commercial IC product fabricated in a 0.35 m fully-silicided CMOS process with OTP memory cells. Exper-imental results showed that the new design can successfully avoid the mistriggering issue on ESD protection device when voltage had a rise time as fast as 25 ns. Under ESD stress conditions, ESD protection device can be efficiently triggered on by substrate-triggered current to achieve a high HBM ESD protection level of 5 kV. Accordingly, with a high immunity against mistriggering and a good ESD robustness, the new pro-posed design is a competent ESD protection solution to the CMOS IC products with high-voltage programming pin.
ACKNOWLEDGMENT
The authors would like to express their thanks for the TLP equipment from Hanwa Electronic Ind. Co., Ltd., Japan. Es-pecially, thanks to Mr. Takumi Hasebe, Mr. Keiichi Hasegawa, and Mr. Masanori Sawada for setting up the TLP measurement system at National Chiao-Tung University, Taiwan.
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[27] G. Notermans, “On the use of N-well resistors for uniform triggering of ESD protection elements,” in Proc. EOS/ESD Symp., 1997, pp. 221–229.
[28] T. Maloney and N. Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in Proc. EOS/ESD Symp., 1985, pp. 49–54.
Ming-Dou Ker (S’92–M’94–SM’97–F’08) received
the Ph.D. degree from National Chiao-Tung Univer-sity, Hsinchu, Taiwan, in 1993.
He was the Department Manager with the VLSI Design Division, Computer and Communication Research Laboratories, Industrial Technology Re-search Institute (ITRI), Hsinchu, Taiwan. Since 2004, he has been a Full Professor with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan. From 2008, he was rotated to be Chair Professor and Vice President of
applications, and biomimetic circuits and systems for intelligent prosthesis. Prof. Ker has served as a member of the Technical Program Committee and the Session Chair of numerous international conferences for many years. He served as an Associate Editor for the IEEE TRANSACTIONS ONVLSI SYSTEMS
during 2006–2007. He was selected as a Distinguished Lecturer in the IEEE Circuits and Systems Society (2006–2007) and in the IEEE Electron Devices Society (2008–2010). He was the President of Foundation in Taiwan ESD As-sociation. In 2009, he was awarded as one of the top ten Distinguished Inventors in Taiwan.
Wen-Yi Chen (S’03) received the B.S. degree from
the Department of Electronics Engineering and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 2003 and 2005, respectively. After military service, he joined the Circuit Design Department, SoC Technology Center, Industrial Technology Research Institute (ITRI), Hsinchu, as a circuit design engineer. In 2006, he joined the Amazing Microelectronic Corporation and worked with system-level ESD protection design. He is currently pursuing the Ph.D. degree in the Institute of Electronics, National Chiao-Tung University. His current research interests include reliability of high voltage CMOS devices and ESD protection design in mixed-voltage I/O circuits.
Wuu-Trong Shieh received the B.S. degree from the
Department of Electronics Engineering and the M.S. degree from the Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan, in 1986 and 1988, respectively.
From 1990 to 1994, he was a Circuit Design En-gineer in Product Development Division of Hualon Microelectronics Corporation (HMC), Hsinchu. In 1995, he joined ELAN Microelectronic Corporation, an IC design house focusing on R&D and marketing of consumer ASIC and MCU. Currently, he is the Director of the ELAN Product Development Division in charge of supervising the development of IC products. His technical area of expertise is in design of digital integrated circuits and on-chip ESD protection for consumer ICs.
I-Ju Wei received the B.S. degree from the
De-partment of Electronics Engineering, Minghsin University of Science and Technology, Hsinchu, Taiwan, in 1989. She worked as an Engineer in the Electronics and Optoelectronics Research Laborato-ries (EOL), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. Currently, she is working in the ELAN Microelectronic Corporation, Hsinchu, Taiwan, as Department Manager of the Layout Division for product development. Her technical expertise is in chip layout for consumer IC products, including area-efficient I/O cell layout with high ESD robustness.
