An Embedded Methodology for FPGAs’ Digital Distance Relay Design and Analysis

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An Embedded Methodology for FPGAs’ Digital Distance Relay

Design and Analysis

Tsair-Fwu Lee, Ming-Yuan Cho

*

, Ying-Chang Hsiao, and Hong-Jen Lee

National Kaohsiung University of Applied Science, Kaohsiung, Taiwan 807, ROC

*Corresponding to MY Cho; email: mycho@mail.ee.kuas.edu.tw

Abstract

This paper proposes a methodology for distance relay design to detect the fault location and mark out the protective region. We followed the intellectual property (IP) cores concept in system on chip to accomplish the development of an intelligent digital distance relay. Therefore, the field programmable gate arrays (FPGAs) technique was applied to design and implement the digital distance relay associated with the proposed method. In additional to verify the validation of the digital distance relay, we compare the result with Matlab simulation check. Then we concluded the performance of the designed distance relay is indeed superior in speed and accuracy with flexibility.

1. Introduction

As early as the beginning of the 1970’s, it was taken the microprocessor for applying to the protective relay in electric power system. With the development of microelectronics, the function of digital protective relay has been greatly changed, from simple electro-mechanical relays to the intelligent phase with a dedicated algorithm. And people pay more attention on system on chip (SOC) in recent years. It provides many benefits: reduced cost and reduced complexity, improved reliability and increased system availability, increased data processing speed [1]. And field programmable gate arrays (FPGAs) have grown to become multi-million-gate devices with system level features that can implement the entire system on one chip. And the concept of intellectual property (IP) cores reuse can be make SOC design to build a required system in a short time.

Distance relay is the most widely used in transmission network protection due to its applicable not only main protection but also for backup protection

by setting protective region properly [2]-[4]. The operation principle of distance relay is based on measurement of the voltage and current ratio at the point of relay installation to determine whether a fault occurs. But the conventional type of distance relay can neither estimate the fault location nor analyze the operation sensitivity. They do not take into account the error correction mechanisms which may derive error operations to cause malfunctions in the corresponding network [5]-[7]. So people pay more and more attention on digital protective relay based on system on chip in recent years.

FPGAs are generic devices which contain a vast number of basic digital components. Using higher level software the interconnections between these components can be defined by users [6].

In this paper we aim to improve the processing speed and increase the accuracy of fault detection as well as the fault location estimation. By using the IP cores concept in the FPGAs chip design, we accomplished a modern digital distance relay associated with high speed and flexibility. Theoretical background of the model

2. Theoretical Background of the Model

Distance relay can be called an impedance relay or a ratio relay generally. Where a fault occurs it will induce some variations in current and voltage consequently. Such signals arise to trip the corresponding circuit breakers for protect the transmission network. It is common used in transmission network protection over 34.5kV systems [8, 9]. So the impedance calculation for fault location on high voltage transmission lines becomes very particular importance [10, 11]. And the results directly affect the fault location decision making when compared with the impedance parameters setting in the system. For the derivation of the relationship between the fault conditions and measured impedance, a

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bus power system as shown in Fig.1 is illustrated to describe the proposed method [12].

Figure. 1. Single-line diagram of a transmission power system

Where;

Em = generator located at bus M.

En = generator located at bus N.

M,N = bus.

Zsm = the total impedance from Em to bus M.

Zsn = the total impedance from En to bus N.

Zlm = the impedance between bus M and fault point.

Zln = the impedance between bus N and fault point.

Rf = fault resistance.

F = fault point.

If = fault current flowing from fault to ground.

Zm = the impedance measured from relay.

ILD = pre-fault current.

Im = total current of bus M.

In = total current of bus N.

Imf = total current variation between bus M and

fault point.

Inf = total current variation between bus N and

fault point.

In this episode, we assume the digital distance relay is installed at bus M. The impedance Zm measured by digital distance relay at bus M may be written as

= m m m V Z I (1)

Where, Vm is the voltage measured by digital distance relay at bus M. As a fault occurs, bus voltage Vm during the fault at bus M could be expressed as:

( )

= × + + ×

m m m m n f

V I Z I I R (2)

Then; taking (2) into (1), then we obtained:

( ) = + f m n I I I _, ₌ ₊ m+ n_× m lm f m I I Z Z R I (3)

Thus, the impedance Zm seen from the distance relay can be obtained by using (3) during faults. Then we define:

2= sn+ ln

Z Z Z _,Z₁=Zsm+Zlm, Em= ×k En (4)

Where; k is the proportional constant between generators’ voltage Em and En. Since the typical

voltage of generator is between 18 to 22 kV, constant k could not be set too large. And the pre-fault current ILD is as following; 1 2 1 2 (1 ) − − = = + + m n m LD E E k E I Z Z Z Z (5)

The pre-fault voltage Vf at point F is

1

( )

= − ×

f m LD

V E I Z ₍₆₎

If a symmetrical fault occurs then the fault current If at point F will be [7]: 1 2 3 3 1 2 , × = = + + f f f V Z Z I where Z Z R Z Z (7) 2 1 1 2 = + Z and W Z Z , 1 2 1 2 . = + Z W Z Z (8)

So when the fault occurs, the current derivation could be written as

1

= ×

mf f

I W I _,Inf =W₂×If (9)

When a fault occurs, Im、In will be become

= +

m LD mf

I I I _,I_n ₌I_nf ₋I_LD₍₁₀₎

Therefore equation (1) can be rearranged in the form:

× + × = = + m lm f f m m m LD nf I Z I R V Z I I I (11) ( ) ₌ + ₊ × + + LD mf lm f f LD mf LD mf I I Z I R I I I I (12) 3 1 1 2 3 (1 ) × + = + − × _{+ ×} + + f f f lm f m f V R Z R Z V k E W Z Z Z R (13)

Taking (5), (6) into (13) then rearrange the form of Zm

3 1 1 2 , or (1 ) ( ) = + _{− ×} ₊ + × + f m lm f R Z Z k Z R W k Z Z = + ∆ m lm m Z Z Z (14)

Where, △Zm represents the impedance variation of distance relay under an abnormal situation. It will strongly affect the measurement of sensitivity and error rate. Therefore the parameters in the term of ΔZm will be considered as important variables during fault analysis. Hence we should use (14) to explore several important factors of digital distance relay, including, the ideal fault protective region, sensitivity analysis, fault location estimation, and impedance relationship.

There are no fault location estimation and possible fault segment length detection functions in conventional distance relay. It only judge whether a fault has occurred inside the protective regions but it is difficult to achieve satisfying results in the system

Em _Z_sm Bus M Zlm Distance Relay Im Zln Rf If In Bus N Zsn En ILD F

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protection. If we can pre-obtain the impedance of relay and the impedance between relay and fault point, then we can further calculate the distance factors between the relay and fault location [13]-[15].

Start

Verilog system Design (V.)

Logic circuit design By Plot method Circuit Synthesis Simulation circiut Programming (.tf) Circuit Simulation Pins assignment

Validation for Generate Programming & implement design Testing End Model selection 1.verilog 2.Plot

Then, by using the obtained data to train the distance relaying and setup the system parameters for protective region [11, 12], a higher accuracy can be achieved for the fault location estimation. In additional, in this paper, we use the piecewise linear interpolation algorithm in the predefining process to increase the precision of fault location estimation and simplify the system design. Therefore, we adapt the proposed method to FPGAs for training the parameters setting

inside. Using modern design software, circuits can be designed and implemented very rapidly, therefore making relay tripping in time and detecting and estimating the correct fault location. The fault location calculation algorithm can be shortly expressed as following;

1) When a fault occurs, the impedance Zmx seen from the relaying end can be obtained by FPGA first. 2) Check the well-trained lookup table to determine

the values of Zm .

3) Using the proposed algorithm to calculate the corresponded distance of Zmx .

We use Fig. 1 as an example to describe the calculation steps of the fault location estimation by using piecewise linear interpolation algorithm. Assume that the distance relay is installed at bus M, and the distance between bus M and bus N is D kilometers. The maximum protection reach is 80% which represents the protection distance is 0.8D kilometers. Then we use the a priori knowledge of fault distance (0% 、 5% 、 10% 、 15% … 80%) and resistances to calculate the fault impedance seen from the relaying end by using (14). Therefore when a fault occurs, we can estimate accuracy fault locations by (15) which have already been trained and embedded into FPGA previously. 2 1 1 1 2 1 ( − )( − ) = + − mx m x m m D D Z Z D D Z Z (15)

Where; Zm1、Zm2 are the well known fault impedance

during training process, and D1 、 D2 are the

corresponding distance respectively. Dx is the exact

fault location [16]-[18].

3. System Programming Alignment

This paper reports on the implementation of an FPGA chip, Xilinx’s partanII XC2S200. And Zeppe’s XC2S200 digital integrated development system was used for the functions development of the distance relay. Xilinx’s ISE WebPack 5.1i development system was applied for the software and hardware development of the FPGA chip, including the Verilog working platform, debugging, circuit synthesis, validation, and circuit wiring. The system simulation was running with Quick Logic’s SpDE9.5. Finally, downloading the system coding embedded into an FPGA chip by using Zeppe’s Integrated Development System (IDS) to finish the job. The flowchart of the system programming alignment is outlined below in Fig.2.

In this study, we selected two cases of transmission line system to test the validation of our method. Running the simulations with Matlab software, we Figure. 2. The design procedure flowchart by used

the ISE and SpDE software for distance relay.

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8. References

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