Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology

I

MPACT OF

G

ATE

T

UNNELING

L

EAKAGE ON

P

ERFORMANCES OF

P

HASE

L

OCKED

L

OOP

C

IRCUIT IN

N

ANOSCALE

CMOS

T

ECHNOLOGY

Jung-Sheng Chen and Ming-Dou Ker Nanoelectronics & Gigascale Systems Laboratory

Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan

A

The influence of gate tunneling leakage on the circuit performances of phase locked loop (PLL) in nanoscale CMOS technology has been investigated by simulation. The basic PLL with second-order loop filter is used to simulate the impact of gate tunneling leakage on performance degradation of PLL in a standard 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL. The locked time, static phase error, and jitter of second-order PLL are degraded by the gate tunneling leakage of MOS capacitor in loop filter.

I

To reduce the power consumption in CMOS VLSI systems, the supply voltage VDD has been scaled down to 1 V, or even sub-1 V.

The gate-oxide thickness of the MOS transistor becomes thinner to reduce normal operation voltage (VDD). The thinner gate oxide

causes large gate-leakage current (tunneling current) [1], [2]. In PLL, the capacitor of loop filter needs a large capacitance to make PLL stable. The MOS capacitor with a larger capacitance per area was often used in PLL to reduce the silicon cost, but the PLL performance is degraded due to the large gate tunneling leakage. Recently, circuit design techniques to compensate the gate tunneling leakage of MOS capacitor in PLL have been reported in nanoscale CMOS processes [3]-[7]. The MOS capacitor realized with thick oxide has a less gate tunneling leakage [3]. The capacitor with multi-metal structure was used to avoid the gate tunneling leakage [4]. The thin-oxide MOS capacitor with opamp compensated technique is developed to reduce the gate leakage [5], [6]. The loop filter with gate tunneling leakage compensator was also developed [7]. However, the impact of gate tunneling leakage on PLL performance has no detailed investigation and analysis in nanoscale CMOS technology.

In this work, the influence of gate tunneling leakage on performances of the phase locked loop (PLL) is investigated and analyzed in a standard 90-nm CMOS process. The operating voltage of MOSFET device is 1 V. The gate tunneling leakage of MOS capacitance is simulated by HSPICE with BSIM4 model. The BSIM4 model has been included with the gate tunneling leakage effect [1], [2]. The MOS capacitors with different oxide thicknesses are used to investigate this impact to PLL.

P

L

L

The PLL is a necessary building block in many very large scale integrated circuits (VLSI). The demand for low-jitter PLLs has become especially strong in advanced nanoscale CMOS process. A PLL is basically an oscillator whose frequency is locked onto some frequency component of an input signal. Fig. 1 shows the basic PLL with second-order low-pass loop filter structure [8]. A PLL consists of a phase/frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), a buffer, and a frequency divider (divided by N).

In this work, the PLL with second-order low-pass loop filter is used to investigate the impact of gate tunneling leakage of MOS capacitor on PLL performances. The design parameters and simulated results of second-order PLL are shown in Table 1. The results of second-order PLL are simulated by HSPICE with a standard 90-nm CMOS HSPICE model. The loop filter (C1, C2, and

R1) in second-order PLL is developed and simulated with ideal

capacitor and resistor in Table 1. The MOS capacitor is usually used to realize the on-chip capacitor to reduce the chip area. The second-order loop filter structure can be realized with PMOS or NMOS devices, respectively.

FIGURE 1. THE BASIC PHASE LOCKED LOOP WITH SECOND-ORDER LOW -PASS LOOP FILTER STRUCTURE.

TABLE 1. THE DESIGN PARAMETERS AND SIMULATED RESULTS OF SECOND-ORDER PLL IN A STANDARD 90-nmCMOS PROCESS

E

MOS

C

W

G

T

L

P

PLL

The C1 and C2 capacitors of low-pass loop filter in PLL, as

shown in Fig. 1, are replaced by MOS capacitors with different oxide thicknesses to investigate the impact of gate tunneling leakage on PLL performances. The capacitances of MOS capacitors C1 and C2 are

85.172 pf and 8.782 pf under gate voltage of 0.492 V, respectively.Fig. 2 shows the simulated control voltage (VCTRL) transition waveform to

find the locked time for MOS capacitors with different oxide

1-4244-0919-5/07/$25.00 ©2007 IEEE IEEE 07CH37867 45th Annual International Reliability

thicknesses. The thin-oxide MOS capacitors (1-V NMOS and 1-V PMOS) have longer locked time and cause larger ripple voltage Vr

than that realized with thick-oxide MOS capacitor (1.8-V NMOS), when the phase difference between VREF and VBACK is kept constant.

The simulated static phase error (Δt) in time domain for the MOS capacitors with different oxide thicknesses is shown in Fig. 3. The thin-oxide MOS capacitors (1-V NMOS and 1-V PMOS) cause larger static phase error (Δt) than that of thick-oxide MOS capacitor (1.8-V NMOS). The simulated jitter under MOS capacitors with different oxide thicknesses in second-order PLL is shown in Fig. 4. The thin-oxide MOS capacitors (1-V NMOS and 1-V PMOS) cause larger jitter than that of thick-oxide MOS capacitor (1.8-V NMOS) in second-order PLL, due to the large ripple voltage at VCTRL node.

FIGURE 2. THE SIMULATEDCONTROLVOLTAGE WAVEFORMS TO FIND THE LOCKED TIME UNDER MOS CAPACITORS WITH DIFFERENT OXIDE

THICKNESSES IN SECOND-ORDER PLL.

FIGURE 3. THE SIMULATEDVOLTAGE WAVFORMS TO FIND THE STATIC PHASE ERROR (Δt) UNDER MOS CAPACITORS WITH DIFFERENT OXIDE

THICKNESSES IN SECOND-ORDER PLL.

FIGURE 4. THE SIMULATEDVOLTAGE WAVEFORMS TO FIND THE JITTER UNDER MOS CAPACITORS WITH DIFFERENT OXIDE THICKNESSES IN

SECOND-ORDER PLL.

The dependence of different input signal frequencies on jitter and ripple voltage under different oxide thickness in the MOS capacitor is shown in Fig. 5. The high input signal frequency of VREF

has a small jitter, and low input signal frequency has a large jitter in second-order PLL with gate tunneling leakage.

FIGURE 5. THE DEPENDENCE OF DIFFERENT INPUT SIGNAL FREQUENCIES ON JITTER AND RIPPLE VOLTAGE UNDER DIFFERENT OXIDE THICKNESS

DEVICES IN THE MOS CAPACITOR.

C

The influence of gate tunneling leakage on circuit performances of second-order PLL has been analyzed and investigated in a standard 90-nm CMOS process. The locked time, static phase error, and jitter of second-order PLL are all degraded by gate tunneling leakage of MOS capacitor in loop filter. The MOS device with high threshold voltage and thick oxide thickness can be used to realize the MOS capacitor in the loop filter for achieving low-jitter and low-cost second-order PLL. The new circuit design technique on loop filter realized with thin-oxide MOS capacitor in PLL should be further developed to compensate such gate leakage issue in nanoscale CMOS technology.

R

[1] W.-C. Lee and C. Hu, “Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling,” in Proc. IEEE Int. Symp. VLSI Tech., 2000, pp. 198-201.

[2] K. M. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source-drain partition,” in IEDM Tech. Dig., 2000, pp. 815-817.

[3] K. Minami, M. Fukaishi, M. Mizuno, H. Onishi, K. Noda, K. Imai, T. Horiuchi, H. Yamaguchi, T. Sato, K. Nakamura, and M. Yamashina, “A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO,” in Proc. IEEE

Custom Integrated Circuits Conf., 2001, pp. 213-216.

[4] R. Holzer, “A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 272-274. [5] R. Maley, “Method and apparatus for tunneling leakage

current compensation,” US Patent 6744303, Jun. 2004. [6] K. Ho, “Method and apparatus for gate current compensation,”

US Patent 6696881, Feb. 2004.

[7] Y. Frans, N. Nguyen, B. Daly, Y. Wang, D. Kim, T. Bystrom, D. Olarte, and K. Donnelly, “A 1-4 Gbps quad transceiver cell using PLL with gate current leakage compensator in 90nm CMOS,” in Proc. IEEE Int. Symp. VLSI Circuits, 2004, pp. 134-137.

[8] D. H. Wolaver, Phase-Locked Loop Circuit Design. NJ: Prentice Hall, 1991.