射頻金氧半場效電晶體於熱載子效應及氧化層崩潰時之特性化及模型化分析

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(1)國 立 交 通 大 學 電子工程學系. 電子研究所碩士班. 碩 士 論 文. 射頻金氧半場效電晶體於熱載子效應及氧化層崩潰 時之特性化及模型化分析. Characterization and Modeling of RF MOSFETs under Hot Carrier Stress and Oxide Breakdown. 研 究 生: 楊 道 諺 指導教授: 張 俊 彥 博士. 中 華 民 國 九 十 四 年 六 月.

(2) 射頻金氧半場效電晶體於熱載子效應及氧化層崩潰時之 特性化及模型化分析 Characterization and Modeling of RF MOSFETs under Hot Carrier Stress and Oxide Breakdown 研 究 生:楊 道 諺. Student:Dao-Yen Yang. 指導教授:張 俊 彥 博士. Advisor:Dr. Chun-Yen Chang. 國 立 交 通 大 學 電子工程學系 電子研究所碩士班 碩 士 論 文. A Thesis Submitted to Institute of Electronics College of Electrical Engineering and Computer Science National Chiao Tung University in partial Fulfillment of the Requirements for the Degree of Master of Science in Electronic Engineering June 2005 Hsinchu, Taiwan, Republic of China. 中 華 民 國 九 十 四 年 六 月.

(3) 射頻金氧半場效電晶體於熱載子效應及氧化層崩潰時之 特性化及模型化分析. 學生: 楊 道 諺. 指導教授: 張 俊 彥 博士. 國立交通大學 電子工程學系. 電子研究所碩士班. 摘要. 近年來隨著生活水準提升,無線通訊 ( wireless communication) 市 場快速成長,無論是學術界或是工業界皆無不極力地發展無線通訊這高科 技. o. 而微波元件則是通訊系統中最重要的骨架。又由於以矽為基底的金氧. 半場效電晶體已經成為射頻元件的主流,所以射頻金氧半場效電晶體的可 靠度分析亦變得愈益重要。 本篇論文之重點即是在研究以矽為基底的金氧半場效電晶體受到熱載 子效應以及氧化層崩潰時的特性分析,此外我們也提出受到熱載子效應及 氧化層崩潰時的金氧半場效電晶體小訊號模型並且討論個別小訊號參數的 變化情形。 首先受到熱載子效應後的金氧半場效電晶體其高頻雜訊,功率特性以及. i.

(4) 截止頻率受到很嚴重的破壞。這主要是因為金氧半場效電晶體的互導下降 之故。另外我們可以藉著固定汲極電流來減緩熱載子效應對於金氧半場效 電晶體的影響。這可以由金氧半場效電晶體在受到熱載子效應後其臨界電 壓,次臨界擺幅,電子遷移率的變化來解釋。 另一方面,由於氧化層在崩潰後會產生一個漏電路徑,所以輸入端的阻 抗以及反射係數會有很明顯的變化。值得注意的是金氧半場效電晶體在氧 化層崩潰後會在氧化層區產生額外的散粒雜訊, 因此其最小雜訊值會劇烈 地增加。 最後,透過小訊號模型的分析,我們發現金氧半場效電晶體的互導,汲 極到源極的電阻以及閘極到源極的電容受到熱載子效應以及氧化層崩潰的 影響較大。另外我們也確認了在氧化層崩潰後主要的漏電路徑是產生在閘 極與源極或通道的重疊區域。. ii.

(5) Characterization and Modeling of RF MOSFETs under Hot Carrier Stress and Oxide Breakdown. Student: Dao-Yen Yang. Advisor: Dr. Chun-Yen Chang. Institute of Electronics National Chiao Tung University. Abstract In recent years, with the improvement of living standard, the development of wireless communication has become the most important technology, not only in academic circles but also in the industries. Microwave transistors are the backbone of these modern wireless communication systems. Since the Si-based MOSFETs (metal-oxide-semiconductor field-effect transistors) have become the mainstream of RF transistors in recent years, the reliability of RF MOSFETs is more and more important. The purpose of this thesis is to investigate the characteristics of RF MOSFETs under hot carrier stress and oxide breakdown. In addition, we proposed a small-signal model individually after hot carrier (HC) stress and oxide breakdown (OBD) and discuss the variations of each small-signal parameter. Firstly, we found that the degradations of cut-off frequency, noise and power characteristics are very obvious after HC stress. It can be explained by the decrease of the transconductance. In addition, the degradation of linearity can be softened by biasing the transistor at constant drain currents. This experimental observation can be explained by the change of threshold voltage, transconductance, subthreshold swing, and mobility under HC stress. iii.

(6) Secondly, since a new leakage path is generated in the gate oxide after oxide breakdown, the input impedance and optimized input reflection coefficient suffer degradations. It is worthwhile to notice that the minimum noise figure increases dramatically after hard oxide breakdown (HBD). It can be explained by the additional shot noise source in gate oxide after HBD. Finally, from the small-signal model, the transconductance (gm0), drain-to-source resistance (Rds), and gate-to-source capacitance (Cgs) suffer more degradation after HC stress and oxide breakdown. We also confirm that the main leakage path locates at the gate and source/channel overlap region.. iv.

(7) 誌. 謝. 在兩年碩士研究生涯中,首先要感謝我的指導教授張俊彥校長,提供 我最好的研究資源並且在繁忙的校務工作之餘仍耐心地給予我們學術上的 指導和鼓勵,在實驗與論文方面最要感謝陳坤明博士以及黃聖懿學長不厭 其煩的耐心指導。也感謝聯華電子提供給我實驗所需要的元件以及國家奈 米元件實驗室黃國威博士在量測上的大力支持。 而在儀器的使用方面,感謝 NDL 高頻元件實驗室卓銘祥學長以及其他 工程師們幫助我解決實驗時的許多問題,同時感謝吳師道學長、彭辭修學 長、楊宗熺學長、吳永俊學長、陳漢譽學長和胡心卉學姊在經驗上的傳承, 亦感謝同屆同學們對我在修業期間給予的指點及扶持,還有助理小姐在行 政工作上的幫忙 最後要感謝家人多年辛苦的栽培,感謝你們長久以來對我無限的支持 和包容,提供給我自由的成長空間讓我在求學路上能走得十分順利。. v.

(8) Contents i iii v. Abstract (Chinese) Abstract (English) Acknowledgement Contents Table Captions Figure Captions. vi. viii ix. Chapter 1 Introduction 1.1 RF Transistors 1.2 Basic Concept of RF MOSFETs 1.3 RF MOSFET Reliability Issues. 1.4 Organization of the Thesis. 1 2 3 3 3 4. Table.1.1 Fig.1.1. 5 6. 1.3.1 Hot Carrier Reliability of RF MOSFETs 1.3.2 Effects of Oxide Breakdown on RF MOSFET. Chapter 2 Basic Theory and Experiments 2.1 Hot Carriers Mechanism 2.2 Oxide Breakdown Mechanism 2.3 Device under Test and Measurement Techniques 2.3.1 Device under Test 2.3.2 I-V Measurement 2.3.3 High Frequency Characteristics Measurement 2.3.4 RF Noise Measurement 2.3.5 Output Power Measurement. Fig.2.1-2.4 Chapter 3 Characteristics of RF MOSFETs under Hot Carriers Stress 3.1 HC stress Experiments 3.2 Effect of HC Stress on DC Characteristics vi. 7 9 10 10 11 11 12 14. 18 18.

(9) 3.3 HC Effects on S-parameters 3.4 Effects of HC Stress on Cut-off Frequency and Maximum Oscillation Frequency 3.5 HC Effects on Power Performance 3.6 HC Effects on Linearity 3.7 HC Effects on Noise Characteristics. 19 20 21 22 24. Fig.3.1-3.17. 26. Chapter 4 Characteristics of RF MOSFETs after Oxide Breakdown 4.1 Effects of Oxide Breakdown on DC Characteristics. 38. 4.2 Effects of Oxide Breakdown on Cut-off frequency and Maximum Oscillation Frequency 4.3 Effects of Oxide Breakdown on S-Parameters 4.4 Effects of Oxide Breakdown on Power Performance and Linearity 4.5 Effects of Oxide Breakdown on Noise Performance Table.4.1 Fig.4.1-4.15. 41 42 45 46. Chapter 5 Modeling of RF MOSFETs under HC stress and Oxide Breakdown 5.1 Extraction Method of Small-Signal Model Parameters 5.2 Modeling of RF MOSFETs under HC Stress 5.3 Modeling of RF MOSFET after Oxide Breakdown. 58 60 61. Table 5.1-5.3 Fig.5.1-5.11. 63 66. Chapter 6 Conclusion and Future Work 6.1 Conclusion 6.2 Future Work. 77 78. References. 79. Vita (Chinese) vii. 39 40.

(10) TABLE CAPTIONS CHAPTER 1 Table 1-1. Performance of CMOS technology in several generations.. CHAPTER 4 Table 4-1. The variations of DC, high-frequency, noise and power characteristics of a MOSFET after HBD and HC stress.. CHAPTER 5 Table 5-1. Extracted parameters before and after HC at (a) VG=1.2V, VD=1.2V, (b) VG=0.8V, VD=1.2V, and (c) VG=0.65V, VD=1.2V.. Table 5-2. Extracted parameters before and after HBD and SBD at (a) VG=0.8V, VD=1.2V,and (b) VG=0.65V, VD=1.2V.. Table 5-3. Extracted parameters before and after HBD and SBD at (a) VG=0.8V, VD=1.2V, and (b) VG=0.65V, VD=1.2V.. viii.

(11) FIGURE CAPTIONS CHAPTER 1 Fig.1-1. Schematic of a typical bulk MOSFET structure.. CHAPTER 2 Fig.2-1. The mechanism of (a) Channel hot electrons (b) Drain avalanche hot carriers (c) Substrate hot electrons.. Fig.2-2. (a) Schematic illustrating the trapping of tunneling electrons. (b) Schematic illustrating the generation of an electron-hole pair in the anode by a tunneling electron. (c) Schematic illustrating the trapping of holes in the oxide layer.. Fig.2-3 Fig.2-4. The schematic and block diagram of the RF noise measurement system. (a) Block diagram of the load-pull measurement system. (b) Power contours on a Smith chart.. CHPATER 3 Fig.3-1. (a) DC characteristics of a MOSFET before and after CHE stress. (b) DC characteristics of a MOSFET before and after DAHC stress.. Fig.3-2. S-parameter degradations with increasing stress time at different bias conditions. Fig.3-3. Output impedance versus stress time.. Fig.3-4. Threshold voltage versus stress time.. Fig.3-5. (a) Cut-off frequency before and after HC stress. (b) Maximum oscillation frequency before and after HC stress.. Fig.3-6 Fig.3-7. Relation between fT and fmax degradations and gm degradation. Output power and 3rd-order intermodulation (IM3) power versus input power before and after HC stress.. Fig.3-8. Power gain versus gate bias voltage for a MOSFET before and after stress measured at a fixed VDS = 1.2V.. Fig.3-9. VIP3 versus VGS –VTH for a MOSFET before and after stress. Inset is the effective channel mobility before and after stress.. ix.

(12) Fig.3-10. Measured OIP3 and IIP3 versus drain current for a MOSFET before and after HC stress.. Fig.3-11. Simulation results of VIP3 with different subthreshold swings and mobility degradation coefficients.. Fig.3-12. (a) Equivalent circuit model of a MOSFET with thermal noise sources, where SiD and Sig are drain current and induced gate noise, respectively. (b) Noise free MOSFET circuit model with input referred noise voltage and current.. Fig.3-13. Optimized input reflection coefficient (Γopt) before and after stress.. Fig.3-14 Fig.3-15 Fig.3-16. Minimum noise figure (NFmin) versus frequency before and after HC stress. Minimum Noise figure versus drain current before and after HC Stress. Noise resistance (Rn) versus frequency before and after stress at fixed bias.. Fig.3-17. Noise resistance versus gate voltage before and after stress.. CHAPTER 4 Fig.4-1. (a) Time evolution of gate current before and after soft breakdown. (b) Time evolution of gate current before and after hard breakdown.. Fig.4-2 Fig.4-3 Fig.4-4. Gate current versus gate voltage before and after oxide breakdown. DC characteristics of a MOSFET before and after oxide breakdown. (a) Cut-off frequency and (b) maximum oscillation frequency versus gate voltage before and after oxide breakdown.. Fig.4-5 Fig.4-6 Fig.4-7. S-parameters before and after oxide breakdown. Small signal model for the measurement of S-parameters. Power gain versus gate bias voltage for a MOSFET before and after oxide breakdown at a fixed VDS = 1.2V.. Fig.4-8. Output power, power gain and PAE versus input power before and after oxide breakdown and HC stress.. Fig.4-9. (a) Output power and 3rd-order intermodulation (IM3) power versus input power before and after soft breakdown. (b) Output power and 3rd-order intermodulation (IM3) power versus input power before and after hard breakdown.. Fig.4-10. Measured OIP3 and IIP3 versus drain current for a MOSFET before and after oxide breakdown. Fig.4-11. Noise resistance (Rn) versus frequency before and after oxide breakdown at a fixed gate bias. x.

(13) Fig.4-12 Fig.4-13 Fig.4-14 Fig.4-15. The variation of Rn versus different VG after HBD and SBD. Minimum noise figure (NFmin) versus frequency before and after stress. Minimum Noise figure versus drain current before and after oxide breakdown. (a) Magnitude of optimized input reflection coefficient before and after oxide breakdown. (b) Phase of optimized input reflection coefficient before and after oxide breakdown.. CHAPTER 5 Fig.5-1. (a) Conventional small-signal model of a MOSFET. (b) Equivalent circuit after de-embedding parasitic components. (c) Small-signal model for the intrinsic part of a MOSFET.. Fig.5-2 Fig.5-3 Fig.5-4. Small-signal model of the MOSFET at the zero bias condition. Extracted values of Rs, Rg and Rd versus frequency. (a) Extracted capacitance versus frequency. (b) Extracted gm0 and τ versus frequency. (c) Extracted Rds and Rbk versus frequency.. Fig.5-5. Measured and modeled S-parameters of a MOSFET before stress at VG=0.8V, VD=1.2V.. Fig.5-6. Measured and Simulated S-parameters of a MOSFET after 7000s HC stress at VG=0.8V, VD=1.2V.. Fig.5-7. (a) Extracted Cgs with increasing stress time. (b) Extracted Cgd with increasing stress time.. Fig.5-8. (a) Variations of Extracted gm0 with increasing HC stress time. (b) Extracted Rds with increasing HC stress time.. Fig.5-9 Fig.5-10 Fig.5-11. Small-signal model of a MOSFET after HBD. Measured and modeled S parameters after SBD at VG=0.8V, VD=1.2V. Measured and modeled S parameters after HBD at VG=0.8V, VD=1.2V.. xi.

(14) Chapter 1. Introduction. 1.1 RF Transistors Currently RF electronics is one of the fast growing parts of semiconductor industry. This is due to explosive growth in the wireless communication market in the past 10 years. However about twenty years ago, this situation was much different. During that time, RF electronics was somewhat mysterious and their applications had been mainly military (e.g. secure communication, electronic warfare system). In the 1990s, the situation changed dramatically. The new global political situation has led to considerable cuts in military budgets. Furthermore, a shift to consumer applications took place, and consumer applications clearly became dominated. Therefore, the design philosophy for many microwave systems changed from “performance at any price” to “sufficient performance at lowest cost”. Microwave transistors are used in a large number of different circuits such as low-noise amplifiers, power amplifiers, mixers, frequency converters and multipliers, attenuators, and phase shifters. Although the requirements on transistor performance differ from application to application, microwave transistors in principle can be distinguished into two groups as small-signal low-noise transistors and power transistors. For microwave electronics, on the other hand, a large variety of different semiconductor materials have been employed, such as Si, SiGe, GaAs, InP, further III-V compounds, and wide bandgap materials [1-3]. In the few years, the silicon-base MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) have become the mainstream of RF transistors.. 1.

(15) 1.2 Basic Concepts of RF MOSFETs In the past 20 years, the silicon base MOSFETs have widely been used in VLSI (Vary Large Scale Integration) applications. However, most RF circuits and systems have been implemented either compound semiconductor transistors. It is due to that the microwave properties of silicon base MOSFETs were inferior to other high-frequency transistors. In recent years, with the fast growth in the wireless communications market, the demand for high performance and low cost RF solutions is rising. Fortunately, the continuous down-scaling CMOS technology has resulted in a strong improvement in the RF performance of MOS device [4]. The basic structure of MOSFETs, shown in Fig. 1-1, consisting of a single gate, a semiconductor substrate and a heavily doped source and drain region, has not changed in the past twenty years. Only the dimensions and other features have been scaled down continuously to meet the demands of higher speed and increased compactness. There are several criterions to determine RF MOSFETs performance such as cut-off frequency, maximum oscillation frequency, power gain, linearity, and noise figure. Table 1-1 shows the cut-off frequency, maximum oscillation frequency and minimum noise figure versus the gate length of n-channel MOSFETs. For today 50- to 100-nm gate length the cut-off frequency can achieve almost 200GHz and maximum oscillation frequency can achieve 70 GHz. The NFmin for 70nm gate length RF MOSFET can be reduced to 0.13 dB. In addition, very high power gain (>25dB) is possible at realistic current for the most advanced technologies [5]. The VIP3 of 70nm gate length can be lower than 0.81 V [6]. Therefore RF MOSFETs have been serious alternatively to the traditional microwave transistors. Moreover, MOSFETs offer very large scale integration and high reliability. As a result, to realize systems-on-chip, the RF operation must use RF MOSFETs to conform to the integration.. 2.

(16) 1.3 RF MOSFET Reliability Issues 1.3.1 Hot Carrier Reliability of RF MOSFETs With the scaling MOS transistor technology, the hot-carrier (HC) reliability becomes a challenging concern while keeping a relatively high drain voltage for both the digital and analog applications. Hot carrier generation and their effects in the characteristics of MOSFETs have been known for a long time [7-9]. It is a result of the high electric fields present inside the MOSFET which naturally appear when high biasing voltages are applied to a short-channel device. The general damages from the hot-carriers on a MOS transistor include the shift of the threshold voltage, the drain current degradation and the decreasing transconductance. Because the RF circuits are sensitive to the parameters of their components [10], HC effects are also important in RF circuit design.. 1.3.2 Effects of Oxide Breakdown on RF MOSFETs Due to the scaling of the SiO2-based gate dielectric in MOSFET, the time to the first oxide breakdown reduces hugely. The chip reliability margin shrinks significantly. Therefore, ultra thin gate-oxide reliability is an urgent issue in deep-submicron silicon CMOS integrated circuit technology. Traditionally, the occurrence of a first gate-oxide breakdown event is considered as a failure for MOSFETs. However, when the gate-oxide is ultra thin, the first breakdown event is most likely to be a soft breakdown. As long as the inversion layer is formed in the channel, the device will still work functionally. In fact, even when hard breakdown happens, MOSFETs may not fail. However, those post-breakdown will generate many defects near oxide-semiconductor interface. Moreover, there will be a small spot of breakdown path through the gate oxide after hard breakdown. These phenomenon cause device parameters shift and change the oxide conduction.. 3.

(17) 1.4 Organization of the Thesis In Chapter 2, we will explain the physical mechanism of hot carriers and oxide breakdown. Then we will introduce different measurement methods that are use to measure s-parameters, noise characteristics and power characteristics of RF MOSFETs. In Chapter 3, we will discuss HC effects on the RF behaviors of MOS transistors. Then we will discuss the effects of oxide breakdown on FOM of RF MOSFETs in Chapter 4. In Chapter 5, we will establish the small-signal models of MOSFETs under HC stress and oxide breakdown and discuss the degradations of each model parameters. For the device model after hard breakdown, some external components will be added into the conventional model to discuss the shift of model parameters of RF MOSFETs after oxide breakdown. Finally, some conclusions will be given in Chapter 6.. 4.

(18) Year. 1995 1997 1999. 2001. 2003. 2005. 2007. 2009. L(nm). 250. 180. 140. 120. 100. 70. 50. 35. fT (GHz). 33. 49. 70. 84. 112. 145. 205. 420. fmax (GHz). 41. 47. 51. 52. 60. 62. 68. 85. NFmin (dB). 0.5. 0.35. 0.23. 0.2. 0.15. 0.13. 0.1. 0.08. Table 1-1: Performance of CMOS technology in several generations.. .. 5.

(19) Gate Source. Drain. Poly-Si Oxide. n+. n+ inversion channel p-type substrate. Fig. 1-1: Schematic of a typical bulk MOSFET structure.. 6.

(20) Chapter 2. Basic Theory and Experiments. 2.1 Hot Carriers Mechanism Hot Carriers are a result of the high electric fields inside the MOSFETs when high biasing voltages are applied to a short-channel length device. Electrons in the inversion layer can get high energies in the high electric field. It is possible that carriers with high energy (i.e. hot carriers) have sufficient energy to overcome the potential barrier between the silicon and silicon dioxide and penetrate into the gate oxide. Some of them may get stuck inside the gate oxide at the defect sites or traps, denoted by Nox. Hot carriers also can break the atomic bonds at the interface of the silicon substrate and the gate oxide and generate new traps which are called interface traps, denoted by Nit. The difference between these two types of traps is that interface traps can be in charge exchange with channel whereas the oxide traps cannot be in direct charge exchange with charges in the channel. These two types of traps will degrade the quality of gate oxide and affect the device electric parameters. As shown in Fig. 2-1(a), when the MOSFET is operated in the saturation region, the channel electrons will gain high energy on their way from source to drain and penetrate into gate oxide. The hot carriers are called channel hot electrons (CHE). The event of a carrier gaining energy and entering the gate oxide is a statistical phenomenon. The maximum numbers of hot carriers which penetrate into gate oxide occur when VG ≅ VD [11]. Another effect that can be caused by energetic carriers in the channel is that carriers on the way toward drain collide with lattice atoms and generate new electron-hole pairs. These electron-hole pairs can also gain high energy in the electric field and produce new 7.

(21) electron-hole pairs, similar to avalanche process in a reversed biased p-n junction. This process is called drain avalanche hot-carriers (DAHC), which is shown in Fig. 2-1(b). During the same process, the energetic carriers can impinge on the atomic bonds at the interface of the substrate and gate oxide or inside the oxide, and break them. Therefore new electronic states Nit are created at the interface. In an NMOSFET, the extra electrons generated in avalanche process are absorbed by drain, and the extra holes are absorbed by substrate terminal which form the substrate current component Isub. It is known that generation of electron-hole pairs in an avalanche process is proportional to both strength of electric field and the number of primary carriers initially flowing in the channel. For low values of VG above the threshold, the transistor is in deep saturation and a pinch-off region is formed near the drain which results in a strong lateral electric field in that region. Also at low values of VG the drain current is low. As VG increases, Id increases, but transistor comes out of saturation region gradually. This causes that a maximum value for Isub appears at some particular value. 1 of VG. It is reported that at VG ≅ VD the maximum Isub is generated in MOSFETs [12]. 2 The third mechanism of hot carriers is called substrate hot electrons (SHE). Unlike the cases of CHE and DAHC, which were caused by lateral electric field in the channel, SHE is caused by the vertical electric field between gate and the substrate. As shown in Fig 2-2(c), the electrons which are thermally generated in the region below the gate, drift toward the silicon-silicon dioxide interface and gain kinetic energy in the electric field below the gate. Some of these electrons penetrate into oxide and cause a uniform distribution of trapped charge in the oxide. SHE is not a major problem in short channel devices as most of the electrons are absorbed into source and drain region and a smaller fraction of them reaches the device surface, compared to the long channel devices.. 8.

(22) 2.2 Oxide Breakdown Mechanism Generally, in advanced MOS devices, there are two breakdown mechanisms observed in dielectric materials. One is called HBD (Hard-Breakdown) and has a permanently distortion in gate oxide dielectric. It results in a dramatic increase of the output currents due to the increasing gate leakage current. The other breakdown mechanism is called SBD (Soft-Breakdown), and the breakdown process shows smoothly and slightly. The physical mechanism involved in, and leading to, the dielectric breakdown process are very complex. They involve impact ionization in the oxide layer, injection of holes from the anode, creation of electron-hole pairs in the oxide, electron and hole trapping, creation of surface state at the oxide-silicon interface, and the interaction of many or all of these process. The mechanism of tunneling into an electron trap can be explained by Fig. 2-2(a). As electrons tunnel into an oxide layer, some of the electrons can get trapped. The trapped electrons modify the oxide field so that the field near the cathode is decreased, while the filed near the anode is increased. Hence the tunneling current will reach a stable value in Soft Breakdown. As electrons travels in the conduction band of an oxide layer, it gains energy from the oxide filed. If the voltage drop across the oxide layer is larger than the band-gap energy of silicon dioxide, the electron can get enough energy to cause impact ionization. As shown in Fig. 2-2(b), when a tunneling electron arrives to the anode, it could cause impact ionization in the anode near oxide-anode interface. Depending on the energy of the tunneling electron, the hole thus generated could be from deep down in the valence band, and thus could be “hot”, a hot hole in the silicon–oxide interface can have a high probability of been injected into oxide layer. On the other hand the injected hole can be trapped in the oxide layer as it travels towards the cathode. The trapped holes in the oxide layer cause an increase in the oxide field near the cathode. 9.

(23) and a decrease in the oxide field near the anode. This could be illustrated in Fig. 2-2(c). According to the F-N tunneling equations:. J FN =. q 3 EOX 2 4 2m*φOX 3/ 2 exp(− ) 16π =φOX 3=qEOX. (2-1). A small increase in the oxide field near the cathode can cause a large increase in the tunneling current. Thus, hole-trapping in the oxide near the cathode provides positive feedback leading to the electron tunneling process. Dielectric hard breakdown occurs when the positive feedback leads to a run away of the electron tunneling current at some local weak spots of the oxide [13]. It appears as a current prominence in current-versus-time plots.. 2.3 Device under Test and Measurement Techniques 2.3.1 Device under Test The MOSFETs are n type MOSFETs in P-well. Multi-finger MOS transistors used in this work were fabricated using a 0.13 µm baseline technology with channel L=0.12 µm and two different sizes of channel width W=3.6μm×22(number of fingers)×2(multiplier) and 3.6μm× 4(number of fingers)×8(multiplier) . The gate oxide thickness is 20 Å.. 2.3.2 I-V Measurement The DC characterizations and stress experiments of RF MOSFETs were performed using Agilent 4156B precision semiconductor parameter analyzer. From the ID-VG curve, we extract the threshold voltage (VTH), and transconductance (gm=dID/dVG).. 10.

(24) 2.3.3 High Frequency Characteristics Measurement For microwave devices, the high frequency characteristics are generally obtained by the measurement of the s-parameters. In this work, on-wafer s-parameters measurement was carried out from 0.1 to 50.0 GHz using microwave coplanar probes and HP 8510C Network Analyzer. On-wafer dummy structures were used to de-embed the pad parasitics. Then, the de-embedded parameters were transformed to the H, Z or Y parameters to extract the desired parameters.. 2.3.4 RF Noise Measurement The ATN NP5 system was used for high frequency noise measurement in this study. It includes the instruments of dc measurement system, small-signal s-parameter system and noise power measurement system. The schematic and block diagram is shown as Fig. 2-3. The NP5 system consists of a mainframe controller and two remote modules suitable for mounting on a wafer probe station. The port 1 (input) module, the Mismatch Noise Source (MNS), contains the solid state electronic tuner with a built-in bias tee and switching circuitry. The port 2 (output) module, the Remote Receiver Module (RRM), contains a bias tee, switching circuitry, and a low noise amplifier. Noise figure is often a simplified model of the actual noise in a system, where a single, theoretical noise element is assumed in each stage. Designing low-noise microwave circuits and systems involves trade-offs between the available gain of a stage and its corresponding noise figure. Making design decisions requires knowledge of how an active device's gain and noise figure change as a function of the source reflection coefficient. In general, noise parameters and gain are independent, requiring separate device characterization. Gain can be determined from S-parameters. A noise parameter characterization must vary the source reflection coefficient presented to the device by using a special tuner. 11.

(25) The dependence of noise factor on source impendence is shown as the following equations. 2 ⎛ Γ opt − Γ S 4 Rn ⎜ F = Fmin + Z 0 ⎜⎜ 1 + Γ 2 1 − Γ 2 opt S ⎝. (. F. ). ⎞ ⎟ ⎟⎟ ⎠. (2-2). = Noise factor of the DUT. Fmin = Minimum noise factor of the DUT that occurs at Γ opt = Γ S. Rn = Noise resistance (the sensitivity of noise figure to source admittance changes) Γ S = Source reflection coefficient that results in the noise factor F Γ opt = Optimum source reflection coefficient for minimum noise factor. The associated gain provided by a device when it is driven by a specific source impedance and can be calculated from the S-parameters of the device and the source reflection coefficient. The associated gain as a function of source impedance is:. (1 − Γ S ) S 21 2. Ga =. 2. (2-3). 2. 1 − S11Γ S (1 − S22 + 2. S21S12 Γ S ) 1 − S11Γ S. 2.3.5 Output Power Measurement We used the load-pull system (ATN LP1 measurement system) to measure and discuss power characteristics and linearity in our study. The functions of this load-pull system perform power discussions on output power, power gain, power added efficiency (PAE), and inter-modulation distortion. The configuration of a load-pull system is shown in Fig. 2-4(a).. 12.

(26) By load-pull test, the output power is measured and plotted as a function of the complex load seen by the transistor. Since a complex load requires two axes, the plot actually appears as constant power contours on a complex impedance plane, for example, a Smith chart. A variable, precisely calibrated tuner operates as a matching network, presenting various complex impedances to the transistor according to a control input. With the aid of an automated system, the real and imaginary parts of Z1 are gradually varied such that the power meter maintains a constant reading. The result is the contour corresponding to that power level shown in Fig. 2-4(b). When Z1 arise so does Zin, necessitating the use of the tuner between the signal generator and the transistor to ensure that the impedance seen by the generator remains constant. If the power delivered to the input is constant, the output power increases as Z1 approaches its optimum value, Zopt. This trend is accompanied by a narrower range for Z1, resulting in the tighter contours and eventually a single impedance value, Zopt, as the output reaches its maximum level, Pmax. In other words, the load-pull test systematically narrows downs the values of Z1 so as to obtain both the maximum output power and corresponding load impedance. The load pull system can also calculate intermodulation distortion using two-tone frequency test.. 13.

(27) VG VD G a te. Source. IG. IC H. D ra in. V S ub. (a). VG VD G a te. Sourc e. IG. IC H. D ra in. I S ub V S ub. (b). VG VD Gate. IG. Source. Drain. ISub V Sub. (c) Fig. 2-1: (a) Channel hot electrons (b) Drain avalanche hot carriers (c) Substrate hot electrons 14.

(28) Ec Ev. Cathod Ec. Ev Anode. After electron trapping Before electron trapping. (a) Ec Ev. Cathod Ec. Ev Anode. (b) After hole trapping. Ec. Before hole trapping. Ev. Cathod Ec. Ev Anode. (c) Fig. 2-2: (a) Schematic illustrating the trapping of tunneling electrons. (b) Schematic illustrating the generation of an electron-hole pair in the anode by a tunneling electron. (c) Schematic illustrating the trapping of holes in the oxide. layer. 15.

(29) (a). (b). Fig. 2-3: The schematic and block diagram of the RF noise measurement system.. 16.

(30) signal generator. input tuner. output tuner power meter. DUT Z1. Zin. controller (a). (b) Fig. 2-4: (a) Block diagram of the load-pull measurement system. (b) Power contours on a Smith chart. 17.

(31) Chapter 3. Characteristics of RF MOSFETs under Hot Carriers Stress. In this chapter, the effects of HC stress on DC characteristics of RF MOSFETs will be discussed in the beginning. In general, the degradations are quite different by using different stress method and in our experiments we found that the degradations are more serious under drain avalanche hot carrier (DAHC) stress. After then we discuss HC effects on the S-parameters, we found that the values of S22 and S21 are degraded seriously. It implies that the output impedance and voltage gain are influenced after stress. Finally, we focus on the changes of the main figures of merit (FOM) of RF MOSFETs after HC stress. It shows that the degradations of noise and power characteristics are obvious due to the HC stress effect.. 3.1 HC Stress Experiments In our experiments, the channel length and total width of MOSFETs are 0.12 µm and 158.4 µm, respectively. For DAHC stress, the gate and drain of the test transistors were biased at 1.2V and 2.4V, respectively. For channel hot electron (CHE) stress, the gate and drain of the test transistors were both biased at 2.4V. The DC characteristics and S-parameters were measured by every 1000 seconds during the stress process. The final stress time is terminated at 7000 second.. 3.2 Effect of HC Stress on DC Characteristics The general effects of the HC stress on the dc characteristics of a MOSFET are shown in 18.

(32) Fig. 3-1. It shows no noticeable variations for device under CHE stress as illustrated in Fig. 3-1(a). Therefore the channel hot electrons just slightly influence the DC characteristics of MOSFETs. On the contrary, it shows a large degradation for device measured after DAHC stress shown in Fig. 3-1(b). Hence the degradations caused by drain avalanche hot carriers are much larger compared to channel hot electrons. Therefore in the following discussion we will focus on the degradations of MOSFET caused by DAHC stress. After DAHC stress, the degradation of saturation drain current in our experiments is about 17%, and the threshold voltage is shifted from 0.45 V to 0.52 V. In Fig 3-1(b), the transconductance (gm) reduces significantly, and the maximum value shifts to higher gate voltages after HC stress. We also found that gm and drain current reduction is more serious in low gate bias region and this phenomenon is possibly due to the interface state generation and the oxide trap charge [14][15].. 3.3 HC Effects on S-parameters As shown in Fig. 3-2, the values of S11 and S12 are almost unchanged with increasing HC stress time. It implies that the input reflection coefficient and isolation of the RF MOSFETs are affected slightly by HC stress. On the other hand, S22 and S21 changed more obviously after HC stress. The degradations of S22 and S21 can be explained by the decrease of transconductance and the increase of the output drain conductance. It also implies that the output reflection coefficient and the voltage gain of the RF MOSFET are affected seriously after HC stress. It is worthwhile to pay attention to the degradation of S22 when biasing at lower gate voltages. With increasing stress time, the degradations of low frequency value of S22 have different trends. The low frequency value of S22 strongly depends on the output impedance. After HC stress, there are a lot of defects generated by impact ionization near the drain region and those defects provide acceptor states in NMOSFETs [16]. Therefore the 19.

(33) electric field near the drain region will increase and the drain current is more controlled by VD. Therefore the output impedance decreases while biasing at high VG shown in Fig. 3-3. However while biasing at low VG, due to the reduction of the depth of depletion region, the output impedance decrease more slightly initially. After a long period of stress time, the increase of oxide trapped charge raise the threshold voltage dramatically shown in Fig. 3-4, so the output impedance becomes to increase shown in Fig. 3-3. Therefore the degradations of low frequency value of S22 have different trends with increasing stress time at low VG bias condition.. 3.4 Effects of HC Stress on Cut-off Frequency and Maximum Oscillation Frequency The cut-off frequency is defined as the transition frequency at which the small-signal current gain of a transistor with common source configuration and short-circuit load drops to unity. As shown in Fig. 3-5(a), the cut-off frequency drops off conspicuously after HC stress. By using the small-signal equivalent-circuit model, the cut-off frequency (fT) can be approximated as:. fT ≅. gm 2π (Cgs + Cgd ). (3-1). From above equation, fT is related with gm and gate-to-source capacitance (Cgs). After HC stress, there are many interface states generated near the oxide and semiconductor interface. Therefore Cgs increased after stress. In addition, from discussions in Section 3-2, gm reduced significantly after HC stress. Due to the increase of Cgs and the decrease of gm, fT reduced dramatically after HC stress. By the observation of Fig. 3-5(a), it also suggested that. 20.

(34) the degradation of cut-off frequency is more robust to HC stress when biasing at higher gate voltages which is similar to the degradation of gm. As shown in Fig. 3-5(b), maximum oscillation frequency (fmax) also decreases after HC stress. The maximum oscillation frequency is defined as the transition frequency at which the unilateral gain of a transistor with common source configuration drops to unity. It can be approximated as:. f max ≅. fT 2 2π f t Cgd Rg + Gds Rin ). (3-2). Because the maximum oscillation frequency is approximately proportional to the cut-off frequency, the degradations are correlated to the cut-off frequency. Therefore, fmax decreased after HC stress and the degradation is more serious while biasing at low VG which is similar to the degradation of fT. From Fig. 3-5, we compared the RF performance degradation with the DC performance degradation. The degradations of fT and fmax are proportional to the gm degradation which can be explained by equation (3-1) and (3-2). Comparing the slopes of these two lines in Fig 3-6, the degradation of fT is much larger than of fmax. Since fmax is proportional to gm1/2, it is less sensitive to HC stress.. 3.5 HC Effects on Power Performance The effect of HC stress on the output power of a MOS transistor is shown in Fig 3-7. It was measured at gate voltage VGS=0.8 V and drain voltage VDS=1.2 V, where gm is the maximum value in device saturation regions, and the frequency was operated at 2.4 GHz. The source and load impedances are matched for maximum output power before stress. Because 21.

(35) the fundamental output power of a MOS transistor is basically correlated to gm/gds, the HC-induced degradation of the dc parameters will lead to a reduction of output power and gain. After HC stress the output conductance has changed, the load impedance will deviate from the maximum output power condition, making the further reduction of output power. In Fig. 3-8, it shows the power gain as a function of gate voltage biases. The power gain reduces after HC stress. However, as the gate voltage bias increases to a higher value, the power gain which was degraded by the HC effect shows a consistent value with the fresh one. As the source and load impedances are matched for maximum output power, the available output power gain can be expressed as:. Ga ,max =. fT 2 4 f 2 (2π ⋅ fT ⋅ Rg ⋅ Cgd + Gds ⋅ Rin ). (3-3). We can find the maximum available power gain is proportional to fT which is correlated to gm. Therefore after HC stress, the power performance in Fig. 3-8 shows a consistent curve with the transconductance in Fig. 3-1. It also suggested that biasing at a higher gate voltage is more robust to HC stress. However, in order to reduce static power consumption in analog/RF applications, they are going to be biased at much lower VGS than digital devices thus are more vulnerable to HC stress.. 3.6 HC Effects on Linearity To characterize the linearity, the third-order intercept point (IP3), at which the output power and third-order intermodulation (IM3) power are equal, is commonly used. For low distortion operation, the third-order intercept point should be as high as possible. As shown in Fig. 3-7, by the two tone test, the output IP3 (OIP3) reduces from 21 dBm to 19.22 dBm after HC stress, while the input referred IP3 (IIP3) reduces from -2.27 dBm to -3.55 dBm. Hence, 22.

(36) the RF linearity degrades under HC stress when the MOSFET operates at a fixed gate bias. The third-order point of gate voltage amplitude (VIP3), where the fundamental and IM3 output amplitude of drain current are equal, is a good indication of device linearity even at high frequency [17] and a large VIP3 is required for high linearity. In addition, it is easily obtained from the DC characteristics [17]. Therefore we use this parameter to explain the impact of HC stress on linearity of RF MOSFET. The definition of VIP3 can be given as:. VIP3 =. 4 gm 3g m3. (3-5). where gm3 is the third-order Taylor expansion coefficient of drain current versus gate voltage. The parameters, gm and gm3, can be directly extracted from the dc characteristics. Actually, the equation (3-5) is obtained without considering the non-linearity of output conductance. Because the amount of output conductance non-linearity is much smaller than that of transconductance when devices operate in saturation region, it can be negligible for low load impedance condition [17], [18]. Fig. 3-9 shows the VIP3 measured with VGS -VTH (VTH is the threshold voltage) of a MOSFET before and after stress. With a fixed VGS – VTH bias condition, we can ignore the shift of the threshold voltage, and observe that the VIP3 shows a slightly change after stress with a typical analog bias conditions, i.e. 0.1V< VGS – VTH < 0.6V. It indicates that the degradation of linearity after stress at a constant gate bias condition is mostly due to the shift of threshold voltage. The observation in Fig. 3-9 is interesting and indicates that although the hot carrier stress affects the transconductance and threshold voltage of the device, its effects on linearity of the transistor can be alleviated as VGS – VTH is kept at a constant. That is to say, RF linearity is less affected by HC stress if biasing the MOSFET at constant drain currents as shown in Fig 3-10. We find that OIP3 and IIP3 only show a slightly change after stress for the device measured at a fixed output drain current. It is noted that OIP3 decreases slightly on middle drain currents due to decrease of the power gain after stress. 23.

(37) From Fig 3-9, we observe the VIP3 increases after HC stress at low bias condition, which can be explained by the increase of linearity at lower drain currents. Because the HC stress will affect the threshold voltage, channel mobility, subthreshold swing, and source/drain resistance, their effects on VIP3 have to be studied. In general, the effective channel mobility in strong inversion region can be expressed as:. µeff =. µ0. (3-6). 1 + θ (VGS − VTH ). where µ0 is the low field mobility and θ is the mobility degradation coefficient due to high electric field. From the simulated results of an I-V model [19], we found that the most important parameters affecting VIP3 at fixed VGS – VTH are subthreshold swing (S.S.) and θ, as shown in Fig 3-11. With increasing S.S., VIP3 will increase in weak inversion region. With reducing θ, VIP3 will increase at 0.05 V < VGS – VTH <0.2 V, and decrease at VGS – VTH >0.2 V. It should be noted that µ0 has no effects on VIP3. This is because µ0 contributes equally to gm and gm3, so its effects are cancelled out in gm/gm3. The observation in Fig. 3-11 can also be predicted by Volterra series calculation as reported in [20]. For the transistor in our work, after HC stress, S.S. increases from 82.6 to 92.6 mV/decade, and θ decreases from 1.54 to 0.68 V-1 (see the inset of Fig. 3-9), so VIP3 increases in the low bias region, as shown in Fig. 3-9.. 3.7 HC Effects on Noise Characteristics To characterize the noise characteristics, three noise parameters have been analyzed. If the noise contribution of source resistance of the MOSFET was neglected, we can use the compact model shown in Fig. 3-12 to approximate these parameters as [21]:. 24.

(38) Rn ≈ R g +. WC OX µ eff 2 gm2. NFmin ≈ 1 + 2[(. ×. 1 LC. (3-7). f 2 WCOX µeff (Vgs − Vth ) Rg f WCOX µeff (Vgs − Vth ) Rg ) +( ) ] 2LC 2LC fT fT. Zopt ≅ Ropt + jX opt =. 35 1 × ∠57.7° 7 ωCgs. (3-8). (3-9). From above equations, the noise parameters strongly depend on the gate-to-source capacitance and transconductance. Due to the little change of input impedance (see the S11 in Fig. 3-2), the optimized input reflection coefficient almost didn’t change after HC stress, as shown in Fig. 3-13. From equation (3-9), we found that the minimum noise figure has a strong dependence on Cgs and gm. Due to the degradation of gm, minimum noise figure increases drastically after stress shown in Fig 3-14. The increase of minimum noise figure is about 88% of initial value. Therefore, HC effect is a very critical concern as designing a LNA. As shown in Fig 3-15, the locations of the valley are not the same. The degradation is also less serious in higher gate voltage region. It is possibly due to the shift of the threshold voltage and the gm degradation shown in Fig. 3-1. Fig 3-16 shows the noise resistance increases after HC stress. It can be explained by equation (3-7) and the gm degradations. According to equation (3-7), the noise resistance is independent of frequency. However, the noise resistance is indeed correlated with the frequency shown in Fig. 3-16. This relation may be contributed by the parasitic parts of RF MOSFETs. Fig. 3-17 shows the degradations of Rn versus different gate voltages. It is obvious that degradations are almost consistent when the MOSFET turns on.. 25.

(39) 0.01. VDS=0.05V. 1E-3. 0.16 0.14. 1E-4. VDS=1.2V. 1E-5. ID(A). 0.18. VDS=1.2V. Before Stress After HC Stress. 0.12 0.10. 1E-6. 0.08. 1E-7. gm(A/V). 0.1. 0.06. 1E-8. VDS=0.05V. 1E-9. 0.04 0.02. 1E-10 1E-11 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2. 0.00. VG(V). (a). 0.18 VD=1.2V Before Stress After HC Stress. 0.16. 1E-3. 0.14 0.12. ID(A). VD=1.2V. 1E-6. 0.10. gm(A/V). VD=0.05V. 0.08 0.06 0.04. 1E-9. VD=0.05V 0.02. 1E-12 -0.6 -0.4 -0.2 0.0. 0.00. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). (b) Fig. 3-1: (a) DC characteristics of a MOSFET before and after CHE stress. (b) DC characteristics of a MOSFET before and after DAHC stress.. 26.

(40) Max Mag 9. Max Mag 0.15. Increasing stress time S21 S12 V G=0.8V VD=1.2V. S22. S11. Max Mag 9. Increasing stress time. VG=0.8V VD=1.2V. Max Mag 0.15. Increasing stress time S21. S12. VG=0.65V VD=1.2V. Increasing stress time. S22 S11. VG=0.65V VD=1.2V. Fig. 3-2 S-parameter degradations with increasing stress time at different bias conditions.. 27.

(41) 200. VG=0.65V. 180. VG=1.2V. Rout(Ω). 160 140 120 100. 80 0. 1000 2000 3000 4000 5000 6000 7000. Stress time(seconds). Fig. 3-3: Output impedance versus stress time at different bias condition.. VTH (V). 0.55. 0.50. 0.45. 0. 1000 2000 3000 4000 5000 6000 7000. Stress time(sec). Fig. 3-4: Threshold voltage versus stress time.. 28.

(42) 100 90 80. fT(GHz). 70 Before Stress After HC Stress. 60 50 40 30 20. VD=1.2V. 10. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). (a). 75. fmax(GHz). 70 65. Before Stress After HC Stress. 60 55. VD=1.2V. 50 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). (b) Fig. 3-5: (a) Cut-off frequency before and after HC stress. (b) Maximum oscillation frequency before and after HC stress.. 29.

(43) fT & fmax Degradation (%). 10 8. 1000s 2000s 4000s 5000s 6000s 7000s. fT. 6. fmax. 4 2. VG=0.8V VD=1.2V 3. 6. 9. gm Degradation(%). Fig. 3-6: Relation between fT and fmax degradations and gm degradation.. 30.

(44) 40. Before Stress After HC Stress. 20. Pout & IM3(dBm). 0 -20 -40 -60 -80. freq=2.4GHz. IIP3. VG=0.8V VD=1.2V. -100 -40. -30. -20. -10. 0. 10. Input Power(dBm). Fig. 3-7: Output power and 3rd-order intermodulation (IM3) power versus input power before and after HC stress.. Linear Power Gain(dB). 30 25. Before Stress After HC Stress. 20 15 10 5 Pin=-30dBm. 0. VDS=1.2V f=2.4GHz. -5 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VGS(V). Fig. 3-8: Power gain versus gate bias voltage for a MOSFET before and after stress measured at a fixed VDS = 1.2V.. 31.

(45) 10. VDS=1.2V. 1 Before Stress After HC Stress. 500. Fit Data. 2. Effective Mobility (cm /V-s). VIP3(V). Before Stress After HC Stress. 400 2. µ0=378 cm /V-s. 300. θ=1.54 V µ0=221 cm /V-s. 200. -1. θ=0.68 V. 0.2. 0.1. -1. 2. 0.3. 0.4. 0.5. 0.6. 0.7. 0.8. VGS-VTH(V). -0.4. -0.2. 0.0. 0.2. 0.4. 0.6. VGS-VTH(V) `. Fig. 3-9: VIP3 versus VGS –VTH for a MOSFET before and after stress. Inset is the effective channel mobility before and after stress.. 30 Before Stress After HC Stress. IP3(dBm). 20. OIP3. 10. IIP3 0. -10. -20. f=2.4GHz VDS=1.2V 0. 10. 20. 30. 40. 50. 60. Drain Current(mA). Fig. 3-10: Measured OIP3 and IIP3 versus drain current for a MOSFET before and after HC stress.. 32.

(46) Fig. 3-11: Simulation results of VIP3 with different subthreshold swings and mobility degradation coefficients.. 33.

(47) port 1. 4kTRg. Cgd. Rg. Sig. port 2. Cgs Sid. gm. Cds. Rds. (a). Cgd. v n2. Rg. port 1. port 2 Cgs. i n2. gm. Cds. Rds. (b). Fig. 3-12: (a) Equivalent circuit model of a MOSFET with thermal noise sources, where SiD and Sig are drain current and induced gate noise, respectively. (b) Noise free MOSFET circuit model with input referred noise voltage and current.. 34.

(48) Fig. 3-13 Optimized input reflection coefficient (Γopt) before and after stress.. 35.

(49) 1.8 Before Stress After HC Stress. 1.6 1.4. NFmin(dB). 1.2 1.0 0.8 0.6 0.4 0.2. VG=0.8V VD=1.2V. 0.0 0. 2. 4. 6. 8. 10. 12. 14. 16. 18. 20. Frequency(GHz). Fig. 3-14: Minimum noise figure (NFmin) versus frequency before and after HC stress. 1.0. NFmin(dB). 0.8. Before Stress After HC Stress. f=5.8GHz VD=1.2V. 0.6. 0.4. 0.2. 0.1. 1. 10. 100. ID(mA). Fig. 3-15: Minimum Noise figure versus drain current before and after HC Stress.. 36.

(50) 45 Before Stress After HC Stress. 40. Rn(Ω). 35 30 VG=0.8V VD=1.2V. 25 20 15 0. 2. 4. 6. 8. 10. 12. 14. 16. 18. 20. Frequency(GHz). Fig. 3-16: Noise resistance (Rn) versus frequency before and after stress at fixed bias.. Before Stress After HC Stress. 200. Rn(Ω). 150. 100. VD=1.2V f=5.8GHz. 50. 0 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). Fig. 3-17: Noise resistance versus gate voltage before and after stress. 37.

(51) Chapter 4. Characteristics of RF MOSFETs after Oxide Breakdown. In this chapter, we discuss the degradations of RF MOSFETs after soft breakdown (SBD) and hard breakdown (HBD). The channel length and total width of the devices under test are 0.12 µm and 158.4 µm respectively in our experiments. The gate oxide stress was subjected to a constant voltage stress under 3.9 V with the source, drain and bulk terminals shorted to ground. As shown in Fig. 4-1(a), the time to soft breakdown is defined as a time at which the gate current increases by 10 % from its initial value. From Fig. 4-1(b), the oxide hard breakdown was defined using a threshold on-stress current of 1 mA. Then we study the effects of oxide breakdown on DC, high-frequency, and power characteristics of a MOSFET.. 4.1 Effects of Oxide Breakdown on DC Characteristics In Fig. 4-2, it shows the IG-VG characteristics of the device before and after stress. The gate current is extremely low before HBD. After HBD, the gate current increases dramatically. It implies that a consistent leakage path in the gate oxide is formed. From the insert figure of Fig. 4-2, the resistance of this leakage path is about 7kΩ. Fig. 4-3 shows the ID-VG characteristics of the MOSFET before and after oxide breakdown. Due to the generation of the interface states and oxide traps after oxide breakdown, the “on” drain current and transconductance all decrease. After soft breakdown, the degradation of saturation drain current in our experiments is about 3%, and the threshold voltage is shifted from 0.45 V to 0.46 V. On the other hand, the degradation of saturation drain current is about 9% and threshold voltage is shifted from 0.45V to 0.48V after hard 38.

(52) breakdown. It is obvious that the “off” current increases dramatically after hard breakdown due to the contribution of the gate leakage current. It will increase static power consumption of a MOSFET in digital operation.. 4.2 Effects of Oxide Breakdown on Cut-off frequency and Maximum Oscillation Frequency Because a new leakage path will be generated after oxide breakdown, we add gate-to-drain and gate-to-source resistors to the small signal model of MOSFETs to derive the equation of cut-off frequency. The cut-off frequency can be approximated as:. gm − fT ≅. 2 1 − Rgd Rgs. (4-1). 2π (C gs + Cgd ). where Rgd is the gate-to-drain resistance and Rgs is the gate-to-source resistance. From the above discussions, the new leakage path was not formed after soft breakdown. Therefore the degradation of fT is very slight, as shown in Fig. 4-4(a). However it is clear that the cut-off frequency reduces significantly after oxide hard breakdown. It is due to the gm degradation and the existence of Rgd and Rgs. The fT degradation is less significant at high gate voltage. It suggested that biasing at higher gate voltage is more robust to hard breakdown. As shown in Fig. 4-4(b), the maximum oscillation frequency (fmax) is affected by SBD and HBD. From equations 3-2, the fmax is proportional to fT, so fmax reduced after oxide breakdown. In addition, it is obvious that the degradation is more serious after HBD. Since fmax is directly proportional to the power gain of the MOSFET. Due to the new leakage path in the gate oxide, the power loss of the MOSFET will increase after oxide breakdown. Therefore fmax suffers degradations after oxide breakdown. 39.

(53) 4.3 Effects of Oxide Breakdown on S-Parameters The S-parameters of a MOSFET before and after oxide breakdown are shown in Fig. 4-5. We observed that the S12 and S11 are almost not affected by SBD. It implies that the input impedance and isolation of the MOSFET may not change. However, for devices after HBD, a gate-to-source leakage path is created. This leakage path would change the input impedance of MOSFETs and thus S11 changes obviously. We also found that the degradation of S12 is very slight. Therefore we can infer that the main leakage path doesn’t locate at the gate-to-drain overlap region. As shown in Fig. 4-5, the magnitude of S21 both decreased after SBD and HBD. However the degradations are not obvious at high frequencies. By using the small signal model shown in Fig. 4-6, the S21 of a MOSFET can be approximated as:. S 21 = −2 ⋅. Z in ,i = [. Z in ,i. (. g m − sCgd. Z o + Rg + Z in ,i 1 + g m Rs. )⋅. (1 + g m Rs ) Z L Zo ⋅ sZ L Cgd + 1 + g m Rs Z 0 + Rd. (1 + g m Rs ) 2 (1 + g m Rs ) Z L (1 + g m Rs ) + ]& s (1 + g m RL )(1 + g m Rs )Cgd 1 + gm Z L sCgs. (4-2). (4-3). At low frequency, S21 can be approximated by:. S 21 = −2 g m RL. Z0 (1 + g m Rs )( Z o + Rd ). (4-4). The S21 is strongly proportional to gm. Hence the magnitude of S21 reduces significantly at low frequency after oxide breakdown. Since the correlation between gm and S21 is smaller at high frequencies, S21 is less degraded by oxide breakdown. There are almost no degradations above 12 GHZ. Finally, the degradations of low frequency value of S22 are due to the degradations of 40.

(54) gm and output conductance. 4.4 Effects of Oxide Breakdown on Power Performance and Linearity The gate oxide breakdown is an important reliability issue for the design of power amplifiers. Fig. 4-7 shows the linear power gain measured with different gate voltages after SBD and HBD. It was found that the degradation is more significant after HBD. Moreover, it shows a slight deviation in higher gate bias regions. The degradation of power gain is corresponded to the gm degradation in Fig. 4-3. From Fig. 4-7, it suggested that the device biasing at high gate voltages is more robust to oxide breakdown. The degradations of output power, power gain and power-added efficiency (PAE) are shown in Fig. 4-8. The PAE can be expressed by:. PAE =. Pout − Pin PDC. =. Pout 1 (1 − ) PDC G. (4-5). At low input power, the PAE is less changed under stress, due to the output power and drain current, and thus power dissipation, reduce simultaneously. When input power is larger than 1dB compression point, the degradations of PAE become serious. Because a part of the ac signal of drain current will be cut off as the input power is large enough. For this reason, the average drain current will increase with increasing input power. Since the bias current of the device after oxide breakdown and HC stress is lower than that of the fresh one, the negative duty cycle of output waveform would enter the cut off region earlier. As a result, the power dissipation of stressed device is higher than that of fresh one, leading to lower PAE. Since the DC degradation is more serious after HC stress, the degradations of PAE is more 41.

(55) serious after HC stress. As a result, hot carriers effect is a more critical concern as designing power amplifiers from above discussions. Since the dc behaviors are changed, the linearity would be affected by the oxide breakdown. As shown in Fig. 4-9, the linearity suffers obvious degradation at a fixed voltage bias after HBD. It is due to the gm degradations shown in Fig. 4-3. Because the gm degradation after oxide breakdown is less serious for device biasing at constant currents, RF linearity suffers less degradation. As shown in Fig. 4-10, oxide breakdown degrades the RF linearity slightly if biasing the MOSFET at constant drain currents.. 4.5 Effects of Oxide Breakdown on Noise Performance The impact of gate shot noise is associated with the gate leakage current in MOSFETs. After oxide breakdown, the gate leakage current increases dramatically. Therefore gate shot noise plays a dominant role in determining the high frequency noise in the MOSFET after oxide breakdown. The drastic change of noise characteristics due to oxide breakdown could be qualitatively explained using established analytical expressions considering the increased contribution from gate shot noise [22]:. Rn =. v2n γ = 4kT ∆f α g m. Fmin ≅ 1 + 2 RnωC gs. (4-6). δ (1 − CG 2 )α 2 2qI G g mα + 5γ (4kT γω 2Cgs 2 ). (4-7). where α  g m / g d 0 , with gd0 being the drain conductance for VDS=0V, γ,δand CG are. parameters of the models for drain noise and induced gate noise. From above equations, noise resistance is mainly dominated by the drain (channel) thermal noise and gm. Hence Rn reduces 42.

(56) significantly after oxide breakdown as shown in Fig. 4-11. From Fig. 4-12, we found that the Rn degradations are almost consistent when the MOSFET turns on. From (4-7), the minimum noise figure is not only determined by Rn but also induce gate noise [term of of. δ (1 − CG 2 )α 2 ] under the square root of in (4-7) and gate shot noise [term 5γ. 2qI G g mα ] under the square root of in (4-7). When the gate leakage is low or frequency (4kT γω 2Cgs 2 ). is high enough, NFmin is dominated by the induce gate noise, and (4-7) simplifies as:. NF min ≅ 1 + 2ω / ωT γδ (1 − CG 2 ) / 5. (4-8). It is proportional to the frequency. On the other hand, when the gate leakage become larger or the frequency is low enough, the NFmin can be approximated as:. NFmin ≅ 1 + 2qI Gγ /(kT α g m ). (4-9). It is independent of frequency. Due to gm degradation, NFmin increases after oxide breakdown shown in Fig. 4-13(a). The degradation is more serious after hard breakdown due to the additional shot noise source. Since IG increases dramatically for device after hard breakdown, the frequency independent region is much larger than that of the fresh one. Fig. 4-13(b) compares the NFmin degradations after HBD and HC stress. The NFmin suffers less degradation after HC stress. It is quite different from the degradations of the other electric performances. As shown in Table 4-1, the DC characteristics, power performance and noise resistance are degraded more significantly for devices under HC stress. From above discussions, those characteristics depend on transconductance strongly. Since gm suffers larger degradations after HC stress, those characteristics are degraded more dramatically. However,. 43.

(57) the NFmin is degraded more significantly for device after HBD than that after HC stress due to the additional shot noise source occurred in the gate region. Fig. 4-14 shows the NFmin as a function of drain current before and after oxide breakdown. The locations of the NFmin valley shift after hard breakdown. It may due to the shift of threshold voltage. Finally, Fig. 4-15 shows the degradations of optimized input reflection coefficient. For devices after oxide breakdown, an additional resistance in leakage path will be introduced between gate and source, leading to the reduction of input impedance. As a result, the magnitude of the optimized input reflection coefficient will be reduced after oxide breakdown.. 44.

(58) Δgm (%). ΔID (%). ΔIIP3 (%). ΔPower Gain(%). ΔNFmin (%). ΔRn (%). ΔfT (%). Δfmax (%). After HBD. -6. -10.3. -4.1. -4.2. 232.1. 28. -8.3. -1.5. After HC Stress. -15.3. -22.8. -8.1. -8.3. 88.3. 114. -17.1. -6.9. Table 4-1: The variations of DC, high-frequency, noise and power characteristics of a MOSFET after HBD and HC stress at VG=0.8V VD=1.2V.. 45.

(59) 9.6E-7. VG=3.9V ; others ground. 9.4E-7. IG(A). 9.2E-7 9E-7 8.8E-7 8.6E-7 8.4E-7 100 200 300 400 500 600 700 800 900. Stress time(sec). (a). VG=3.9V ; others ground 1E-3. IG(A). 1E-4. 1E-5. 1E-6. 1E-7. 10. 100. 1000. Stress time(sec). (b). Fig. 4-1: (a) Time evolution of gate current before and after soft breakdown. (b) Time evolution of gate current before and after hard breakdown.. 46.

(60) 0.01 1E-4. Before Stress After SBD After HBD. VDS=0.05V. IG(A). 1E-6 1E-8 1E-10 0.00020. 1E-12. After HBD. IG(A). 0.00015. 1E-14. 0.00010. 0.00005 0.00000. 1E-16. 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). 0.0. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). Fig. 4-2: Gate current versus gate voltage before and after oxide breakdown.. 0.01. Before Stress After SBD After HBD. 0.18. VDS=1.2V VDS=0.05V. 1E-4. 0.12. VDS=1.2V. ID(A). 0.15. 1E-6. 0.09. 1E-8. 0.06 VDS=0.05V. 1E-10 1E-12 -0.6 -0.4 -0.2 0.0. gm(A/V). 1. 0.03 0.00. 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). Fig. 4-3: DC characteristics of a MOSFET before and after oxide breakdown.. 47.

(61) 100 90 80. fT (GHz). 70 60 Before Stress After SBD After HBD. 50 40. VD=1.2V. 30 20. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). (a). 75. fmax (GHz). 70 65 Before Stress After SBD After HBD. 60 55. VD=1.2V 50 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). (b). Fig. 4-4: (a) Cut-off frequency and (b) maximum oscillation frequency versus gate voltage before and after oxide breakdown.. 48.

(62) 0.8. Swp Max 40GHz 0 2.. 2.. 0. 0.. 6 4. 0. VG=0.8V VD=1.2V. 0.. 0.. 3.. 0 4.. 5.0. 10.0. 5.0. 3.0. 2.0. 1.0. 10.0. After HBD. 0.8. 0.2. 0. 10.0. 5.0. 4.0. 3.0. 2.0. 1.0. 0.8. 0.6. 0.4. 0.2. 0. After SBD. 10.0. 0.6. 0.2. 0.2. After SBD. 5.0. Before Stress. 0.4. 4. Before Stress. After HBD. 0 3.. 0 4.. 4.0. 0.8. 0.. 6. Swp Max 40GHz. 1.0. S22. 1.0. S11. -10.0. -10.0. 2 -0.. -3. .4. .0. -2. .6. S12 75. 45. VG=0.8V VD=1.2V. 45. Swp Max 40 GHz. 60. 60. 75. 0 12. 0 12. 5 13. 5 13. VG=0.8V VD=1.2V. 90. Mag Max 0.12. Swp Max 40 GHz. 105. 105. 90. S21 Mag Max 9. Swp Min 0.1GHz. -1.0. -0.8. -0. Swp Min 0.1GHz. -1.0. -0.8. -0. .6. -2. .0. .0. -0. -3 .0. -4 .0 -5. 0. .4 -0. -4 .0 -5. 0. VG=0.8V VD=1.2V. 2 -0.. 30. 30 15. 15 0. 0. Before Stress 15. 15. After SBD. 165. 165. After HBD. 0. After SBD. -15. -15 -165. After HBD -3. -3 0. 0 50 -1. 50 -1. -1 35. 49. -105. -75. Fig. 4-5: S-parameters before and after oxide breakdown.. -90. 0.04 Per Div. Swp Min 0.1 GHz. 0 -6. 0. -1 20. -1. 35. 5 -4. 5 -4. -6. -75. -90. 3 Per Div. -105. -165. 0. -180. Before Stress. -1 20. -180. Swp Min 0.1 GHz.

(63) Zi. Rd. Vo1. Cgd. Cgs. Rd. gmV Cds. Rds. ZO. Vo2 V2. V1 Rs. Fig. 4-6: Small signal model for the measurement of S-parameters.. 50.

(64) 25. Linear Power Gain(dB). 20. Before Stress After SBD After HBD. 15 10 5. Pin=-30dBm 0. V DS=1.2V f=2.4GH z. -5 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VGS(V). 25. 60. 20. Before Stress After SBD After HBD After HC Stress. 15 10 5. 50 40 30. 0 -5. 20. -10 VG=0.8V VD=1.2V. -15. 10. f=2.4GHz. -20. 0. -40. -30. -20. -10. Power Added Efficiency (%). Output Power & Power Gain (dBm/dB). Fig. 4-7: Power gain versus gate bias voltage for a MOSFET before and after oxide breakdown at a fixed VDS = 1.2V.. 0. Intput Power(dBm). Fig. 4-8: Output power, power gain and PAE versus input power before and after oxide breakdown and HC stress.. 51.

(65) 40 Before Stress After SBD Pout. Pout & IM3(dBm). 20 0 -20. IM3. -40 -60. freq=2.4GHz. -80. IIP3. VG=0.8V VD=1.2V. -100 -40. -30. -20. -10. 0. 10. Input Power(dBm). (a). 40. Before Stress After HBD. Pout & IM3(dBm). 20 Pout. 0 -20 -40. IM3. -60 freq=2.4GHz. -80. IIP3. VG=0.8V VD=1.2V. -100 -40. -30. -20. -10. 0. 10. Input Power(dBm). (b) Fig. 4-9:. (a) Output power and 3rd-order intermodulation (IM3) power versus input power before and after soft breakdown. (b) Output power and 3rd-order intermodulation (IM3) power versus input power before and after hard breakdown.. 52.

(66) Before Stress After SBD After HBD. 30. IP3(dBm). 20. OIP3. 10. IIP3 0 -10 -20. f=2.4GHz VDS=1.2V 0. 10. 20. 30. 40. 50. 60. 70. Drain Current(mA). Fig. 4-10: Measured OIP3 and IIP3 versus drain current for a MOSFET before and after oxide breakdown. 53.

(67) 30 Before Stress After SBD After HBD. 28 26. Rn(Ω). 24 22 20 18 16 14 12. VG=0.8V VD=1.2V 0. 2. 4. 6. 8. 10. 12. 14. 16. 18. Frequency(GHz). Fig. 4-11: Noise resistance (Rn) versus frequency before and after oxide breakdown at a fixed gate bias.. 140 After SBD After HBD. 120. ∆Rn(%). 100 80 VD=1.2V. 60 40 20 0 0.2. 0.4. 0.6. 0.8. 1.0. 1.2. VG(V). Fig. 4-12: The variations of Rn versus different VG after HBD and SBD.. 54.

(68) Before Stress After SBD After HBD. 0.16. Fmin -1. 0.12. 0.08. 0.04. VG=0.8V VD=1.2V 0.00. 2. 4. 6. 8. 10. 12. 14. 16. 18. 20. Frequency(GHz) `. (a). 0.20. Before Stress After HBD After HC Stress. 0.18 0.16. Fmin -1. 0.14 0.12 0.10 0.08 0.06 0.04 0.02. VG=0.8V VD=1.2V. 0.00. 0. 2. 4. 6. 8. 10. 12. 14. 16. 18. 20. Frequency(GHz). (b) Fig. 4-13: Minimum noise figure (NFmin) versus frequency before and after stress.. 55.

(69) 1.2 Before Stress After SBD After HBD. 1.0. NFmin(dB). 0.8 0.6 VD=1.2V 0.4. f=5.8GHz. 0.2 0.0. 1. 10. 100. ID(mA). Fig. 4-14: Minimum Noise figure versus drain current before and after oxide breakdown.. 56.

(70) Gamma_opt(Mag). 1.0 Before Stress After SBD After HBD. 0.9. 0.8. 0.7. VG=0.8V VD=1.2V 0.6. 0. 2. 4. 6. 8. 10. 12. 14. 16. 18. Frequency(GHz). (a). 120 Before Stress After Stress After HBD. Gamma_opt(Ang). 100 80 60 40 20. VG=0.8V VD=1.2V 0. 0. 3. 6. 9. 12. 15. 18. Frequency(GHz). (b). Fig. 4-15: (a) Magnitude of optimized input reflection coefficient before and after oxide breakdown. (b) Phase of optimized input reflection coefficient before and after oxide breakdown. 57.

(71) Chapter 5. Modeling of RF MOSFETs under HC stress and Oxide Breakdown. In this chapter, we establish a small-signal model of the RF MOSFET which is valid up to 18 GHz. The cold-FET method [24] was used in our model to extract the parasitic resistances. An extraction approach, which was proposed by S. Lee [25], was adopted to determine the intrinsic circuit parameters. For modeling devices under HC stress, we compare the variations of each parameter after stress. To model the oxide breakdown effects, we add gate-to-source and gate-to-drain resistances to the device model after oxide breakdown. The main leakage path located at the gate and source overlap region. It is quite important while considering the input network matching. 5.1 Extraction Method of Small-Signal Model Parameters The small-signal model shown in Fig. 5-1(a) can be partitioned into three parts. The first part includes the parasitic series resistors Rg, Rd and Rs, and the second part refers to as the substrate network. The third part is the intrinsic model. We extract the parasitic resistors by using the zero-bias small-signal equivalent circuit as shown in Fig. 5-2. If the frequency is not high enough, we can ignore the substrate network. Conversion of the measured zero bias S-parameters into real components of an equivalent z-parameters network yields the parasitic resistance values. Equations for the parasitic resistances of the model shown in Fig. 5-2 are given by: 58.

(72) Re( Z11 ) = Rg + Rs. (5-1). Re( Z 22 ) = Rd + Rs. (5-2). Re( Z12 ) = Re( Z 21 ) = Rs. (5-3). Fig. 5-3 illustrates the values of Rg, Rs and Rd extracted by this technique. After de-embedding the parasitic parameters, we use the curve-fitting method [26] to extract the parameters associated with the substrate parasitic. After d-embedding Rg, Rs, and Rd, the resulting network would become that shown in Fig. 5-1(b) and it will produce following equations:. 1 Rds eff. = Re al (Y22 c + Y12 c ) =. Cds eff = Rbk = Cbk =. k ω2 1 + 1 2 Rds 1 + k2ω. (5-4). 1 + m1ω 2 Im(Y22 c + Y12 c ) = Cds + C jd ( ) 1 + m2ω 2 ω 1. k2 m [1 − 1 ]2 k1 m2. (5-5) (5-6). m1C jd. (5-7). m2 − m1. where k1, k2, m1, m2 can be considered as constants. From above equations, the parameters which are associated with substrate network can be obtained by using curve-fitting method. Finally the parameters of the intrinsic network shown in Fig. 5-1(c) can be directly extracted by following equations [26]:. Cgd = − Cgs =. 1. ω. 1. ω. Im(Yi ,12 ). (5-8). Im(Yi ,12 + Yi ,11 ). (5-9). 59.

(73) Cds = Rds =. 1. ω. Im(Yi ,12 + Yi ,22 ). (5-10). 1 Re(Yi ,22 ). (5-11). g m 0 = Mag (Yi ,21 + Yi ,12 ). τ =−. 1. ω. (5-12). Phase(Yi ,21 − Yi ,12 ). (5-13). Fig. 5-4 shows the extracted values of each parameter versus frequency. The extracted parameters remained somewhat constant with frequency. Finally we show the measured and modeled S-parameters in Fig. 5-5 to verify the accuracy of this model.. 5.2 Modeling of RF MOSFETs under HC Stress From the observations of S-parameters after HC stress, we assume that there are no new components added to the equivalent circuit shown in Fig. 5-1.Therefore we directly use conventional small-signal model to establish the device model under HC stress. As shown in Fig. 5-6, this model is accurate under HC stress. Table 5-1 shows the extracted parameters before and after HC stress at different bias conditions. We found that only Cgs, gm0, Rds and Rd suffer degradations after HC stress. First of all, we plot the extracted Cgs and Cgd with increasing stress time, as shown in Fig. 5-7. It is obvious that Cgs and Cgd increase with increasing HC stress time. The variations of Cgd are very slight compared with that of Cgs. We use the definition of small-signal gate-to-source capacitance to explain this observation [27]:. Cgs = −. ∂Qg ∂Vs. =. WCOX vsig. x= L. ∫v. ac. ( x)dx. (5-14). x =0. 60.

(74) in which L and W are the length and width of the MOSFET, respectively, vac is the small signal potential along the channel, vsig is the small signal voltage applied to the source in order to measure Cgs, and Cox is the gate oxide capacitance per unit area. For fresh device, there are no negative trap charges near drain. Hence vac changes uniformly from source to drain terminal. After HC stress, due to the presence of negative trap charges near drain, vac near drain increases. Therefore the value of equation (5-14) increases and Cgs increases dramatically after HC stress. It implies that input matching has been changed at high frequency. It should be pointed out that depending on bias point, Cgd changes slightly, as confirmed by the data in [28]. As a result, the variation of Cgd is too small to have any significant effects on the RF performance of the MOSFET compared to that of Cgs. Fig. 5-8 shows the degradations of gm0 and Rds with increasing stress time. The degradations of gm0 are more serious when biasing at lower gate voltages. Rds decreases initially and then increases with increasing stress time. They are all in agreement with the discussions in Chapter 3, Section 3-2. We also found that drain resistance increases slightly which is due to the generation of negative trap charges near drain terminal after HC stress.. 5.3 Modeling of RF MOSFET after Oxide Breakdown From Fig. 4-2, the gate leakage current almost didn’t change after SBD. Therefore we still use the equivalent circuit shown in Fig. 5-1 to establish the small-signal model of a MOSFET under SBD. On the other hand, due to the dramatic increase of gate leakage current after HBD shown in Fig. 4-2, we assume that there are two leakage paths generated in gate-to-source and gate-to-drain overlap regions. Therefore we add gate-to-source resistance (Rgs) and gate-to-drain resistance (Rgd) into the equivalent circuit shown in Fig. 5-1 to establish HBD model shown in Fig. 5-9. Rgs can be determined by fitting the low frequency value of S11 and Rgd can be determined by fitting the magnitude of S12. Fig. 5-10 and Fig. 5-11 61.

數據

Table 1-1: Performance of CMOS technology in several generations.

Table 1-1:

Performance of CMOS technology in several generations. p.18
Fig. 1-1: Schematic of a typical bulk MOSFET structure.
Fig. 1-1: Schematic of a typical bulk MOSFET structure. p.19
Fig. 2-3: The schematic and block diagram of the RF noise measurement system.
Fig. 2-3: The schematic and block diagram of the RF noise measurement system. p.29
Fig. 2-4:  (a) Block diagram of the load-pull measurement system.  (b) Power contours on a Smith chart
Fig. 2-4: (a) Block diagram of the load-pull measurement system. (b) Power contours on a Smith chart p.30
Fig. 3-7: Output power and 3 rd -order intermodulation (IM3) power versus input  power before and after HC stress
Fig. 3-7: Output power and 3 rd -order intermodulation (IM3) power versus input power before and after HC stress p.44
Table 4-1: The variations of DC, high-frequency, noise and power  characteristics of a MOSFET after HBD and HC stress at V G =0.8V V D =1.2V

Table 4-1:

The variations of DC, high-frequency, noise and power characteristics of a MOSFET after HBD and HC stress at V G =0.8V V D =1.2V p.58
Fig. 4-1:  (a) Time evolution of gate current before and after soft breakdown.  (b) Time evolution of gate current before and after hard breakdown
Fig. 4-1: (a) Time evolution of gate current before and after soft breakdown. (b) Time evolution of gate current before and after hard breakdown p.59
Fig. 4-2: Gate current versus gate voltage before and after oxide breakdown.
Fig. 4-2: Gate current versus gate voltage before and after oxide breakdown. p.60
Fig. 4-3: DC characteristics of a MOSFET before and after oxide breakdown.
Fig. 4-3: DC characteristics of a MOSFET before and after oxide breakdown. p.60
Fig. 4-4: (a) Cut-off frequency and (b) maximum oscillation frequency versus  gate voltage before and after oxide breakdown
Fig. 4-4: (a) Cut-off frequency and (b) maximum oscillation frequency versus gate voltage before and after oxide breakdown p.61
Fig. 4-6: Small signal model for the measurement of S-parameters.
Fig. 4-6: Small signal model for the measurement of S-parameters. p.63
Fig. 4-7: Power gain versus gate bias voltage for a MOSFET before and after  oxide breakdown at a fixed V DS  = 1.2V
Fig. 4-7: Power gain versus gate bias voltage for a MOSFET before and after oxide breakdown at a fixed V DS = 1.2V p.64
Fig. 4-10: Measured OIP3 and IIP3 versus drain current for a MOSFET before  and after oxide breakdown
Fig. 4-10: Measured OIP3 and IIP3 versus drain current for a MOSFET before and after oxide breakdown p.66
Fig. 4-12: The variations of R n  versus different V G  after HBD and SBD.
Fig. 4-12: The variations of R n versus different V G after HBD and SBD. p.67
Fig. 4-11: Noise resistance (R n ) versus frequency before and after oxide  breakdown at a fixed gate bias
Fig. 4-11: Noise resistance (R n ) versus frequency before and after oxide breakdown at a fixed gate bias p.67
Fig. 4-13: Minimum noise figure (NF min ) versus frequency before and after  stress.
Fig. 4-13: Minimum noise figure (NF min ) versus frequency before and after stress. p.68
Fig. 4-14: Minimum Noise figure versus drain current before and after oxide  breakdown
Fig. 4-14: Minimum Noise figure versus drain current before and after oxide breakdown p.69
Fig. 4-15:  (a) Magnitude of optimized input reflection coefficient before and  after oxide breakdown
Fig. 4-15: (a) Magnitude of optimized input reflection coefficient before and after oxide breakdown p.70
Fig. 5-3 illustrates the values of R g , R s  and R d  extracted by this technique.
Fig. 5-3 illustrates the values of R g , R s and R d extracted by this technique. p.72
Fig. 5-1: (a) Conventional small-signal model of a MOSFET. (b) Equivalent  circuit after de-embedding parasitic components
Fig. 5-1: (a) Conventional small-signal model of a MOSFET. (b) Equivalent circuit after de-embedding parasitic components p.79
Fig. 5-2: Small-signal model of the MOSFET at the zero bias condition.
Fig. 5-2: Small-signal model of the MOSFET at the zero bias condition. p.80
Fig. 5-3: Extracted values of R s , R g  and R d  versus frequency.
Fig. 5-3: Extracted values of R s , R g and R d versus frequency. p.81
Fig. 5-4: (a) Extracted capacitance versus frequency. (b) Extracted g m0  and τ  versus frequency
Fig. 5-4: (a) Extracted capacitance versus frequency. (b) Extracted g m0 and τ versus frequency p.82
Fig. 5-5: Measured and modeled S-parameters of a MOSFET before stress at  V G =0.8V V D =1.2V
Fig. 5-5: Measured and modeled S-parameters of a MOSFET before stress at V G =0.8V V D =1.2V p.83
Fig. 5-6: Measured and Simulated S-parameters of a MOSFET after 7000s HC  stress.
Fig. 5-6: Measured and Simulated S-parameters of a MOSFET after 7000s HC stress. p.84
Fig. 5-7:  (a) Extracted C gs  with increasing stress time.
Fig. 5-7: (a) Extracted C gs with increasing stress time. p.85
Fig. 5-8: (a) Variations of Extracted g m0  with increasing HC stress time.   (b) Extracted R ds  with increasing HC stress time
Fig. 5-8: (a) Variations of Extracted g m0 with increasing HC stress time. (b) Extracted R ds with increasing HC stress time p.86
Fig. 5-9: Small-signal model of a MOSFET after HBD.
Fig. 5-9: Small-signal model of a MOSFET after HBD. p.87
Fig. 5-10: Measured and modeled S parameters after SBD at V G =0.8V, V D =1.2V.
Fig. 5-10: Measured and modeled S parameters after SBD at V G =0.8V, V D =1.2V. p.88
Fig. 5-11: Measured and modeled S parameters after HBD at V G =0.8V,  V D =1.2V.
Fig. 5-11: Measured and modeled S parameters after HBD at V G =0.8V, V D =1.2V. p.89

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