Abnormal sub-threshold swing degradation under dynamic hot carrier stress in
HfO2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
Jyun-Yu Tsai, Ting-Chang Chang, Wen-Hung Lo, Ching-En Chen, Szu-Han Ho, Hua-Mao Chen, Ya-Hsiang Tai, Osbert Cheng, and Cheng-Tung Huang
Citation: Applied Physics Letters 103, 022106 (2013); doi: 10.1063/1.4811784 View online: http://dx.doi.org/10.1063/1.4811784
View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/103/2?ver=pdfcov Published by the AIP Publishing
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Abnormal sub-threshold swing degradation under dynamic hot carrier stress
in HfO
2/TiN n-channel metal-oxide-semiconductor field-effect-transistors
Jyun-Yu Tsai,1Ting-Chang Chang,1,2Wen-Hung Lo,1Ching-En Chen,3Szu-Han Ho,3 Hua-Mao Chen,4Ya-Hsiang Tai,4Osbert Cheng,5and Cheng-Tung Huang5
1
Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan
2
Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan
3
Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan
4
Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan
5
Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan
(Received 28 April 2013; accepted 29 May 2013; published online 10 July 2013)
This work finds abnormal sub-threshold swing (S.S.) degradation under dynamic hot carrier stress (HCS) in n-channel metal-oxide-semiconductor field-effect-transistors with high-k gate dielectric. Results indicate that there is no change in S.S. after dynamic HCS due to band-to-band hot hole injection at the drain side which acts to diminish the stress field. Moreover, the impaired stress field causes the interface states to mainly distribute in shallow states. This results in ON state current and transconductance decreases, whereas S.S. degradation is insignificant after dynamic HCS. The proposed model is confirmed by one-side charge pumping measurement and gate-to-drain capacitance at varying frequencies.VC 2013 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4811784]
Consumer electronic products which are combined dis-play design,1–5 memory circuits,6–10 and IC circuits have popularized considerably in the last few years. To achieve high speed and lightweight, the continuous scaling-down of metal oxide semiconductor field effect transistors (MOSFETs) is driving conventional SiO2-based dielectric to only a few
atomic layers thick, leading to excessive gate leakage current and reliability issues.11To solve the leakage current problem, a high-k material is utilized as gate insulator to reduce both tunneling gate leakage and power consumption in comple-mentary MOS (CMOS) circuits.12–14Furthermore, the high-k/ metal gate can be integrated with silicon-on-insulator techniques.15–18 Additionally, charge trapping in high-k gate stacks remains a key reliability issue, since it causes threshold voltage (VTH) shift and drive current degradation
19–22
due to the filling of pre-existing traps in the high-k dielectric layer.23–25In addition, charge trapping effect is found to have great impact on hot carrier stress (HCS)-induced device insta-bility since carriers tend to be injected into the high-k layer.26,27Hot carrier injection is a critical issue for submicron transistors since devices encounter higher lateral electric fields, and this issue is even more severe in high-k/metal gate MOSFETs. Moreover, in circuit applications, the CMOS in-verter is always operated with dynamic gate voltage (VG)
rather than a constant VG. Therefore, in this experiment,
dynamic HCS has been simulated to resemble real CMOS operation conditions for high-k/metal gate n-MOSFETs. The dynamic HCS condition was with square waveform of VG switching from2 V to 2 V and a fixed VD¼ 3 V with source
and body grounded. The VG¼ 2 V, VD¼ 3 V condition can
induce band-to-band hot hole generation, and the VG¼ 2 V,
VD¼ 3 V condition can lead to the most serious HCS
degrada-tion. Additionally, abnormal sub-threshold swing (S.S.) degra-dation could be observed after dynamic HCS, which is a degradation trend different from previous studies.28 This unusual phenomenon is analyzed by the saturation drain
current-gate voltage (ID-VG), gate induced drain leakage
(GIDL) current, and one-side charge pumping measurements. In addition, the drain-to-gate capacitance (CGD) at varying
frequencies was used to explain the model proposed in this work.
High-performance TiN/HfO2n-MOSFETs with an
inter-facial layer (IL) thickness of 30 A˚ fabricated via 28-nm CMOS technology were studied in this paper. Devices were fabricated using a conventional self-aligned transistor which progressed via the gate-first process. For gate-first process devices, high quality thermal oxides with thicknesses of 30 A˚ were grown on a (100) Si substrate as an IL oxide layer. After standard cleaning procedures, 30 A˚ of HfO2film was
sequentially deposited by atomic layer deposition. Next, 10 nm of TiN film was deposited by radio frequency physical vapor deposition, followed by poly-Si deposition as a low resistance gate electrode. The activation for source/drain and poly-Si gate was performed at 1025C. The channel and source/drain doping concentrations were about 1 1018cm3and 1 1021cm3, respectively. In this study, the dimensions of the devices were width (W)/length (L)¼ 10/1 lm. The dynamic HCS condition was with square waveform of VG switching from 2 V to 2 V and a fixed
VD¼ 3 V with source and body grounded. The stress was
briefly interrupted to measure the linear ID-VG, saturation
ID-VG, GIDL current, charge pumping, and gate-to-drain
capacitance (CGD) at various frequencies. In the CGD
mea-surement, measurement signals were applied to the gate elec-trode, and drain electrode was connected to a capacitance sensing unit with frequency¼ 2 MHz. In the charge pumping measurement, the base of VG pulse (VG-base) was fixed at
0.8 V and the peak of VGpulse (VG, high) was ranging from
0.4 V to 2 V with frequency ¼ 5 MHz. GIDL current was measured at VG¼ 0.5 V and VD¼ 2.4 V. All experimental
curves were measured using an Agilent B1500 semiconduc-tor parameter analyzer and a Cascade M150 probe station.
0003-6951/2013/103(2)/022106/4/$30.00 103, 022106-1 VC2013 AIP Publishing LLC
Figure 1(a) shows the ID-VG and corresponding
transconductance-gate voltage (Gm-VG) at linear region
measurement after dynamic HCS for high-k/metal gate n-MOSFETs. For dynamic HCS, the drain is biased at 3 V and the gate bias is square waveform switching from 2 V to 2 V, where VG¼ 2 V was where the most serious HCS
degra-dation occurred for the device. It can be seen that both ON state current (ION) and Gm degrade under dynamic HCS,
while there is no significant change in S.S. This abnormal S.S. degradation phenomenon is different from general dynamic HCS, where S.S. shows a clear degradation.
Figure1(b)shows the forward ID-VGand the reverse ID
-VGcurves (source/drain interchanged) measured at the
satu-ration region after dynamic HCS for high-k/metal gate n-MOSFETs. It can seen that in the forward saturation ID-VG
curve, there is only an insignificant decrease in IONbecause
measured VDdepletes the main interface states and trapping
charge. However, in the reverse ID-VGoperation, there is an
early turn on at the OFF state with S.S. degrading at the sub-threshold region after dynamic HCS. These phenomena may be due to the hole injection and interface state generation at the drain side, as shown in the inset of Fig.1(b).
To confirm the phenomenon of hole injection, Fig. 2
shows measurements of ID-VG corresponding to body
cur-rent-VG (IB-VG) at VD¼ 2.4 V. It can be observed that the
GIDL current decreases after HCS due to hole trapping increasing the band-to-band tunneling distance, as shown in the inset of Fig.2. Obviously, the trapping holes is generated by band-to-band hot hole tunneling when the dynamic VG
switches to 2 V at constant VD¼ 3 V. Then the
band-to-band hot hole prefers to inject into the high-k layer because of a strong electric field towards the gate. To further confirm the presence of hole trapping and interface state generation, the charge pumping method was utilized.29Figure 3shows charge pumping current (ICP) versus VG,highand shows that
ICP increases by about 330% and flat band voltage (VFB)
shifts 0.5 V toward the negative direction after dynamic HCS. Nevertheless, this ICPincrease and VFBshift were due
to interface state generation and hole trapping, respectively. Since hole trapping can lead to VFB and VTH downward
band bending, VG,high contacts the VFB and VTH curves to
produce an earlier ICP. Moreover, by measuring ICP with
FIG. 1. (a) ID-VGand corresponding Gm-VGat linear region measurement shows no significant change in S.S. (b) Forward ID-VG and the reverse ID-VG (source/drain interchanged) at the saturation region measurement after dynamic HCS for high-k/metal gate n-MOSFETs. Inset shows the lateral energy band diagram with hole trapping lowering the VTH at the reverse ID-VGmeasurement.
FIG. 2. ID-VGand corresponding IB-VGmeasurement at VD¼ 2.4 V show-ing GIDL current decrease after dynamic HCS. Inset shows that hole trap-ping increases band-to-band tunneling distance.
FIG. 3. ICP-VG,highshows an increase of 330% and VFBshift of 0.5 V toward the negative direction during dynamic HCS. Inset shows one-side floating CP technique with floating source or drain terminal to measure ICP.
floating source or drain terminal, the location of charge trap-ping can be determined. The inset of Fig.3shows the one-side floating CP technique with floating source or drain ter-minal to measure ICP. Clearly, the drain floating only results
in an increasing ICP, but no shift in VFB. However, the source
floating shows not only increasing ICPbut also VFBshifting
0.5 V toward the negative direction after dynamic HCS. Therefore, the hole trapping at the drain side can be con-firmed by this one-side floating CP technique.
Based on the experimental analysis above, a physical model is proposed to explain the abnormal S.S. degradation under dynamic HCS. Our experimental observations confirm both hole trapping at the high-k layer and interface state gen-eration near the drain side, as shown in Fig. 4(a). Corresponding to the lateral energy band diagram, as shown in Fig.4(b), the trapped holes can form a buffer region at the depletion region to reduce the stress electron field, in turn reducing electron kinetic energy.30Therefore, the weakened hot electron kinetic energy is not enough to generate a deeper level interface states during dynamic HCS, but mostly shallow states, as shown in Fig.4(c). Consequently, when a small sweep Vg is applied (VG< VTH) at the linear ID-VG
measurement, the Fermi energy is still insufficient to cover the shallow states at the sub-threshold region, resulting in an insignificant change in S.S. after dynamic HCS, as shown in Fig. 1(a). However, when a large sweep VG is applied
(VG> VTH), the Fermi energy moves up to cover the shallow
states; thus, the shallow states fill with electron to form nega-tive charge states and then lower the ION.
To further prove the presence of shallow state genera-tion after dynamic HCS, the capacitance measurement tech-nique can be utilized to confirm our assumption. Figure 5
shows normalized CGD curves at various measured
frequencies before and after dynamic HCS. It can be clearly seen that capacitance rises early, indicated by the blue dashed circle, due to hole trapping at the drain side, which is in agreement with previous experimental data. In addition, the blue dashed circle marks a stretched out capacitance for different frequencies, indicating that there was interface state generation at the drain side after dynamic HCS, also in agreement with previous analyses. More worthy of mention is the green dashed circle region which marks a two-step ca-pacitance that become less apparent at lower frequencies. This behavior is dominated by channel carrier trapping and detrapping time when capacitance is measured. For higher frequency measurements, the electron can fill up interface states, because there is insufficient time to allow the trapping electron to drop out from shallow states. Therefore, the trap-ping electron forms a higher barrier height at the drain side, as shown in the upper left inset of Fig.5, leading an evident two-step capacitance at higher frequency measurements. For the lower frequency measurements, the electron also can fill up interface states but has enough time to allow the trapping electron to drop from shallow states. Thus, the trapping elec-tron forms a lower barrier height at the drain side, as shown in the bottom right inset of Fig. 5, leading to only a slight two-step capacitance at lower frequency measurements. By this capacitance measurement technique at various frequen-cies, the contribution of shallow states can be known after dynamic HCS.
It has been generally thought that dynamic HCS could generate many interface states, resulting in serious S.S. deg-radation in n-MOSFETs with high-k gate dielectric. However, this work finds abnormal S.S. degradation in that there is no change after dynamic HCS. This is due to band-to-band hot hole injection at the drain side where hot holes act to diminish the stress field. Moreover, the reduced stress field decreases the impact ionization rate; this weaker impact ionization rate leads to the generation of only shallow inter-face states. Consequently, the shallow states result in decreases in both ON state current and Gm but no significant S.S. degradation after dynamic HCS. The proposed model is explained by one-side charge pumping measurement and
FIG. 4. (a) Diagram of n-MOSFET structure showing hole trapping and interface state generation at the drain side. (b) The lateral energy band dia-gram indicating that trapping holes form a buffer region at the depletion region to reduce the stress electron field. (c) The energy band diagram shows only shallow states generated after dynamic HCS.
FIG. 5. Normalized CGD curves at various frequencies before and after dynamic HCS. Inset shows the lateral energy band diagram of electron trap-ping and detraptrap-ping behavior for higher and lower measurement frequencies.
CGD at various frequencies. Therefore, the mechanism of
abnormal S.S. degradation can be illustrated after dynamic HCS in n-MOSFETs with high-k gate dielectric.
Part of this work was performed at United Microelectronics Corporation. The work was supported by the National Science Council under Contract No. NSC 101-2120-M-110-002.
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