326 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 19, NO. 5, MAY 2009
A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar
Bulk-CMOS Technology With High-
Q
Above-IC Inductors
Wen-Chieh Wang, Student Member, IEEE, Zue-Der Huang, Geert Carchon, Member, IEEE,
Abdelkarim Mercha, Member, IEEE, Stefaan Decoutere, Walter De Raedt, Associate Member, IEEE, and
Chung-Yu Wu, Fellow, IEEE
Abstract—A 23 GHz electrostatic discharge-protected low-noise
amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high- above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- above-IC inductors have been implemented by thin-film wafer-level pack-aging technology. The fabricated LNA has a good linearity where the input 1 dB compression point(IP 1 dB) is 9 5 dBm and the input referred third-order intercept point( IIP3) is +2 25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.
Index Terms—CMOS, electrostatic discharge (ESD) protection,
45 nm, K -band, low-noise amplifier (LNA).
I. INTRODUCTION
T
HE rapid development of bulk-CMOS technologies makes the realization of low-cost and high-integration RF integrated circuits at frequencies above 20 GHz feasible. The low-noise amplifier (LNA) is a key building block in the RF receiver front-ends. So far, numerous bulk-CMOS LNAs designed at frequencies around 20 GHz have been reported [1]–[8], but not in 45 nm bulk-CMOS technologies. Among them, the single-ended structure has been used in [2]–[7], whereas the differential topology has been adopted in [1] and [8]. The inductive degeneration at the source of the input transistor is used in [2]–[3], [6]–[8] to achieve both noise and input impedance matching. To obtain high gain, the multi-stage configuration has been proposed [1], [5]–[8]. But they gener-ally consume more power and lose the linearity performance. Generally, the single-ended structure has the advantage of a good noise figure (NF) and low-power consumption.In this work, a LNA is designed and implemented in 45 nm gate length planar bulk-CMOS devices (fabricated at IMEC)
Manuscript received September 19, 2008; revised January 12, 2009. First published April 24, 2009; current version published May 08, 2009.
W.-C. Wang, Z.-D. Huang, and C.-Y. Wu are with the Department of Elec-tronics Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]; [email protected]).
G. Carchon, A. Mercha, S. Decoutere, and W. De Raedt are with the IMEC, Leuven B-3001, Belgium (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LMWC.2009.2017611
to verify its feasibility in RF-IC design. The single-ended one-stage cascode structure with inductive source degeneration is adopted to achieve low power dissipation, high linearity, and good NF. The electrostatic discharge (ESD) protection circuits for both power pins and bias pins have been imple-mented in the designed LNA. The fabricated LNA has a small power consumption of 3.6 mW under 1 V power supply. It has good linearity performances with the values of and and , respectively. Furthermore, the LNA has a NF of 4 dB and a gain of 7.1 dB at the peak gain frequency of 23 GHz. The measurement results of the fabricated LNA have the highest figure-of-merit (FOM) as compared with other LNAs.
The circuit design is presented in Section II, while the exper-imental results are described in Section III. Finally, the conclu-sion is given in Section IV.
II. CIRCUITDESIGN
In the 45 nm planar bulk-CMOS technology, the transistor has been demonstrated with a peak cut-off frequency around 300 GHz with the achievable transconductance ef-ficiency of 2.5 . In the back-end process, the 45 nm CMOS technology offers five layers of metal in the Cu damascene process and metal-insulator-metal (MIM) capacitor. The circuit diagram of the designed one-stage LNA is shown in Fig. 1. The cascode amplifier formed by and is used to reduce the Miller effect of and to achieve good reverse isolation. The degenerative inductor at the source of is used to provide the real-part impedance for the input impedance matching. With , the design goals of both noise and input impedance matching can be achieved simultaneously. Further-more, does not seriously degrade the NF performance. How-ever, increasing the value of reduces the gain of the amplifier. The value of in this design is set at 0.2 nH.
With a minimum channel length of 45 nm, the widths of and are chosen by setting the bias current to the optimal current density of minimum noise figure to min-imize the noise contributions from and . The is 0.15 approximately, which is nearly independent of CMOS technologies [9]. The widths of and are chosen as 30 each when the power consumption is designed to be less than 5 mW from 1 V power supply. The input matching net-work has been designed by using , , , and the parasitic capacitance of the input pad.
The output is loaded with an inductor to provide parallel resonance and to increase the gain at the desired frequency. The
WANG et al.: 1 V 23 GHZ LNA 327
Fig. 1. Circuit diagram of the one-stage cascode LNA with ESD power clamp diodes.
Fig. 2. Chip microphotograph of the one-stage cascode LNA with the size of 0.722 1.12 mm including testing pads.
Fig. 3. Measured and simulated S-parameters of the one-stage cascode LNA.
output matching network has been designed to match 50 by , , , and the parasitic capacitance of output pad. The bypass capacitors is added between and ground in order to stabilize the bias voltage (supply voltage) and to isolate the bias (supply) noise from entering the LNA.
In this design, the wafer-level packaging (WLP) technology [10] is used to realize the low-cost high- above-IC inductors , , and . and are one-turn spiral inductors. is a microstrip transmission line inductor, where the signal path is realized in the WLP process, and the ground path is realized by the metal-1 and metal-2 of the back-end process in this 45 nm gate length planar bulk-CMOS technology. In the WLP process, the 5 thick electroplated metal layer of Cu on the 20 low- dielectric of BenzoCycloButhene (BCB) has been post-processed on top of the 45 nm planar bulk-CMOS process. From the HFSS simulation, the factors of , , and at 23 GHz
Fig. 4. Measured and simulated NF of the one-stage cascode LNA.
Fig. 5. Two-tone measured results of the one-stage cascode LNA.
TABLE I
HBM ESD ROBUSTNESS OFPOWER-CLAMPSTI DIODE
can be extracted as 41, 39, and 39, respectively. In addition, the values of , , and are 0.38 nH, 0.45 nH, and 0.2 nH, respectively. The shallow trench isolation (STI) -well and -well diodes are implemented between supply/bias ( and ) and ground for ESD protection. The drawing dimension of each STI diode is 19.35 by 1.85 .
III. EXPERIMENTALRESULTS
Fig. 2 shows the chip microphotograph of the fabricated LNA where the dimension is of 0.72 mm 1.12 mm including the testing pads. On wafer measurements have been performed on the LNA. The circuit draws 3.6 mA from a 1 V supply voltage. The measured and simulated S-parameters are shown in Fig. 3 where the measured gain of the LNA is 7.1 dB. In this ex-perimental chip, the measured of around is margin-ally acceptable. The measured and simulated NF are shown in Fig. 4 where the measured NF at 23 GHz is about 4 dB. The simulated characteristics are based on the preliminary version of 45 nm planar bulk-CMOS transistor models. The measured
328 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 19, NO. 5, MAY 2009
TABLE II
PERFORMANCECOMPARISONWITHBULK-CMOS LNASAROUND20 GHZ
Fig. 6. Comparison with the published bulk-CMOS LNAs around 20 GHz by
FOM .
value of is . The linearity performance is ver-ified by two-tone testing. Two RF inputs with the same input signal power level of are at the frequencies of 23.1 and 23.1 GHz. The two-tone measured results shown in Fig. 5 reveal that the is . It is shown that the fabricated LNA has good linearity.
Human-body-model (HBM) ESD tests were performed at the supply and biasing pads for both positive and negative test volt-ages. The HBM ESD robustness of power-clamp STI diodes is summarized in Table I. In the worst case, HBM ESD protection level of 3 kV is achieved.
The measured results of the fabricated LNA are compared with those of published CMOS LNAs around 20 GHz in Table II. As can be seen from Table II, the fabricated LNA has good linearity performance as well as low power consumption. The LNAs in [3] and [5] have better linearity performance than this work at the cost of higher power consumption.
To characterize the performance of all LNAs, the FOM de-fined in [11] has been used. It can be written as
(1) where represents the gain, IIP3 denotes the linearity, is the operating frequency, is the noise factor, and is the power dissipation. In (1), and are in absolute values, and
are in units of mW, and is in the unit of GHz. The values of are calculated for different LNAs and are presented in Table II and Fig. 6. As shown in Fig. 6, the fabricated 45 nm CMOS LNA has the highest as compared with other published bulk-CMOS LNAs around 20 GHz.
IV. CONCLUSION
A 23 GHz LNA has been designed and fabricated in 45 nm gate length planar bulk-CMOS technology. The fabricated LNA has a NF of 4 dB and a of at the 1 V supply voltage and 3.6 mW power consumption with the chip size of 0.72 1.12 . As compared with other bulk-CMOS LNAs around 20 GHz, the fabricated LNA has good linearity, low power dissipation, low NF, and the highest FOM. From the above experimental results, it is shown that 45 nm gate length planar bulk-CMOS technology is suitable for the design of high-performance LNAs and other RF ICs above 20 GHz.
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