• 沒有找到結果。

多媒體與多重服務之數位用戶迴路通訊系統

N/A
N/A
Protected

Academic year: 2021

Share "多媒體與多重服務之數位用戶迴路通訊系統"

Copied!
5
0
0

加載中.... (立即查看全文)

全文

(1)

1

!

!!!

! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

! !

OTD!:1.3329.F.113.148

90

! 8 ! 1

91

! 7!

! 31!

! ! ! !!

!

!

!

!

!

!

! !

!

!

! !

(2)

!

!

xDSL Multimedia & Multi-service Communication System

OTD!:1.3329.F.113.148!

:1

9

2

:2

8

42

!

!!!

!

!

!

!

!

!

!

! ! 3C xDSL xDSL (QoS) ! ! Abstract

The first goal of this 3C group project is to explore xDSL transceiver using SoC techniques. The topics include technologies of xDSL, mixed signal processing, VLSI circuits, DMT engine, embedded DSP core, mixed signal circuits testing, SoC testing and design for test (DFT). Second, advanced technologies for broadband services will be explored. The specific applications include VoIP, web proxy and real-time multimedia services. In addition, we also aim to explore advance protocol for mentioned services and quality of service (QoS).

INTRODUCTION

ENU! !\2^! ! ! ! ! DMT (Programmable Filter) (AGC) (1-1) (VGA) (Programmable Filter) (Gain & Buffer)

VGA (1-2) Chebyshev 1.104x2n MHz (1-3) AGC Programmable Filter (1-4) (1-1) ! (1-2)

(3)

! (1-4) AGC ENU !\3^! ! ! ! ! !!!! )ENU* )BXHO* )OFYU* )GFYU* )SGJ* )Jnqvmtf!opjtf*! )3.2* )3.3* hbuf.mfwfm 1/46!vn2Q5N )3.4* !

ADC Interpolator BoundaryEstimator FFT

Frequency Domain Equalizer Decision & Deinterleaver Reed-Solomon Decoder Descrambler Timing Offset Tracking Loop

Estimate Symbol Boundary Received

Signal

Bit stream Output Loop Filter Timing Error Detector Channel Estimation Timing Controller ! )3.2*! !! ! )3.3*! ! ! )3.4*! ! EN JQ !\4^! ! ! ! ! ! JQ JGGU! )4.2* )NEDU* )NETU* Sffe!Tpmpnpo )4.3* GTN ST!dpefd )dpefxpse* 1d od 366 1d ud 9 UDN )4.4* UDN CBSH)CN.up.BDT!Spvujoh!Hfof.!sbups* CNV BDT ! (3-1) IFFT (3-2) RS (3-3) ! !\5^! ! ! ! ! 0.5 Vpp 0.5 Vpp

(4)

yETM UDQ!Gpsnptb uftucfe yETM )Bqqmjdbujpo!Mbzfs!Dpogfsfodf!Usff* Nfhbdp0I/359 )5.2* Hbufxbz )5.3* )5.4* Dptu!Fggfdujwf ! 0 1000 2000 3000 4000 5000 6000 7000 8000 0 20 40 60 80 100 Number of on-tree gateways

Jo in la te nc y Number of GWs = 100 Number of GWs = 300 Number of GWs = 600 Number of GWs = 1000 ! )5.2*! ! Time line B an dw id th (M B ) Conference tree MCU ! )5.3*! ! ! )5.4*!Dptu!Fggfdujwfoftt! ! yETM! !\6^! ! ! ! ! RpT SUQ ot3 kjuufs UDQ.Gsjfoemz )B!Ofx!

Bqqspbdi! Vtjoh! Ujnf.Cbtfe! Npefm! gps! UDQ.Gsjfoemz!Sbuf!Ftujnbujpo* SUQ0SUDQ mptt.sbujp kjuufs.sbujp UDQ UDQ.gsjfoemz ot3 ! mptt.kjuufs )Uif! mptt.kjuufs! Cbtfe! Bekvtunfou! gps! Nvmujnfejb! Bqqmjdbujpot*! N e t w o r k L a y e r A p p l ic a t io n L a y e r ! V id eo C a m era

Ap p lica tion T ran spo r t Ne tw ork

V id eo C a p tu rer E n c o d erM P E G4 R T P S e n d e r T raffic S h a p e r P a th R es e rve d e ffo rtB e s t V id eo P la ye r D ec o d erM P E G4 R T P R e c eiv er Ap p lica tion T ran spo r t D isp la y

D e vic e

C o n tro ller

A n aly sis M o n ito r

YETM! ! !!!!!!!!!! !\7^! ! ! !!!!! ! ! !!!! YETM ETQ

(5)

)Jotusvdujpo!Tfu! Bsdijufduvsf!JTB* WETM )Hsbqijd!Vtfs!Joufsgbdf!HVJ* ETQ!Dpsf )Hfofsbups* WETM )7.2* )7.3* ! S Data Memory Program Memory MA Multiplier EB MB MC ALU MH Barrel shifter Multiplier MF Delay Reg Hamming distance MG

NCU_DSP_2002 Processor Function Block:

FIR ADDER EAB DB DAB CB PB PAB CAB T R2 R3 R4 R5 R6 R7 R0 R1 0 MW

Basic Function Block Optional Special Function Block

Slicer R

S R Mux

Correlator

Optional Multi-Function Block

! )7.2*!WETM

!

Configuration Setup in Window GUI

Invoke corresponding modules

buf_ver3.v Optional module

HDL codes Generators based on C language

IF_gen.exe arau.exe reg_file.exe

IF_con.exe generate fetch.v fetch_all.v generate arau.v generate reg_file.v generate config.exe generate config.v Generate SRAM instructions SRAM instructions

RA2SD poscript verilog synopsys -instname HPI_mem -words 64 -bits 16 -mux 16

! )7.3*! ! ! yETM! !\8^! !! ! ! ! !!!!BED ! ! )8.2*! ! ! )8.3*! ! ! )8.4*! BED!JOM ! ! !

REFERENCE

!

[1] NSC Program Report, System Architecture and AFE Designs of DMT Transceiver, NSC-90-2218-E-002-038.

[2] NSC Program Report, Design of DMT Baseband Processing Architecture for High-speed DSL, NSC-90-2218-E-002-039. [3] NSC Program Report, Design and

Implementation of Digital IP for DMT Engine in High-Speed DSL Applications, NSC-90-2218-E-002-40.

[4] NSC Program Report, Voice over IP (VoIP) and Web proxy over xDSL,

NSC-90-2218-E-002-041.

[5] NSC Program Report, Adaptive QoP/QoS Support for Multiresolution Video Application over xDSL,

NSC-90-2218-E-008-022.

[6] NSC Program Report, Parameterized DSP Core for XDSL, NSC-90-2218-E-008-023. [7] NSC Program Report, xDSL Mixed Signal

System on Chip Testing and Desin for Testability, NSC-90-2218-E-008-024. ADC Under M U D r V

參考文獻

相關文件

4.1 多因子變異數分析 多因子變異數分析 多因子變異數分析 多因子變異數分析與線性迴歸 與線性迴歸 與線性迴歸 與線性迴歸 4.1.1 統計軟體 統計軟體 統計軟體 統計軟體 SPSS 簡介 簡介

Research on Analog and Mixed-Signal Processing Integrated Circuit Design for ISFET-Based Linear Sensor Array

(英文) The Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP 2010). 發表 論文

First we explain how to implement CMOS current-mode quadratic circuits and design the proposed circuit in the way of multiple corrections.. We use the best

[7]Jerome M .Shapiro “Embedded Image Using Zerotree of Wavelet Coefficients”IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL,41,NO.12,DECEMBER 1993. [8 ]Amir Said Willam

It allows a much wider range of algorithms to be applied to the input data and can avoid problems such as the build-up of noise and signal distortion during processing.. Since

The purpose of this study is to explore the development of child concept and the effectiveness of learning in the design of learning areas for young mixed-age-oriented

Target organ specificity is the result of specific receptor molecules for the hormone, either on the plasma membrane surface, or in some cases in the cytoplasm, of cells in the