High-performance fully integrated 4 GHz CMOS LC VCO in standard 0.18-μm CMOS technology

1

High-performance Fully Integrated 4 GHz CMOS LC VCO

in Standard 0.18-Pm CMOS Technology

Shey-Shi Lu, Tao Wang, and Yo-Sheng Lin1

Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, ROC

Tel: 886-233663228; Fax: 886-223652907; Email: sslu@ntu.edu.tw 1

Department of Electrical Engineering, National Chi-Nan University, Puli, Taiwan, R.O.C.

Abstract - In this paper, we demonstrate that high Q-factor inductors on normal 750-Pm-thick silicon substrate (in standard 0.18-Pm CMOS technology) can be achieved by optimization of the layout of the inductors. To study the effect of pattern-ground-shield (PGS) on our designed inductors, we compare the performance of the inductors with and without PGS. In addition, a state-of-the-art 4-GHz CMOS LC voltage-controlled oscillator (VCO) with phase noise of -119.94 dBc/Hz measured at 1 MHz offset frequency is reported.

Index Terms  CMOS, LC, VCO, PGS

I. Introduction

Recently, the on-chip spiral inductor has been extensively studied because it is a must for the fulfillment of single-chip radio. However, the quality (Q) factor of on-chip inductors is low due to losses in the conductive substrate as well as the series resistance of the metallization. Various methods have been reported to enhance the Q factor such as high-resistivity silicon [1], front-side micromachining [2][3], back-side micro- machining [4], porous silicon [5], proton implantation [6]. Most of the proposed methods are very difficult, if not impossible, to be integrated into the standard CMOS technology because they are non-standard processing steps. In addition, the front-side etching has inherent limitations as to how far circuits can be placed from the inductors [3]. Therefore, the CMOS technology compatible patterned ground shield (PGS) method [7], which can improve the Q in the frequency bands of interest, seems to be a better choice.

In this work, the performance of high Q-factor on-chip inductors with and without PGS is reported. In addition, based on these high Q-factor inductors, a state-of-the-art 4-GHz CMOS LC VCO is implemented.

II. Designs of the Inductors and the 4-GHz LC VCO

A. Inductors

To optimize Q-factor, self-resonant frequency (fSR) of the inductors, metal width, metal space, and inner dimension of the inductors were carefully selected based on the simulated results of EM simulation tools of Sonnet Software’s SONNET and “Momentum” of Agilent’s advanced design system (ADS). Fig. 1 shows the layouts of the 2.5-turn on-chip inductors with PGS (PGS IND) and

without PGS (STD IND) implemented in a standard 0.25 Pm CMOS process provided by the commercial foundry UMC. The track width and spacing are 20 Pm and 2 Pm, respectively. The slot spacing and metal strip width of the PGS are both 0.24 Pm.

B. 4-GHz LC VCO

CMOS VCOs with integrated inductors are well suited for wireless applications [8], [9]. To prevent the unwanted frequency pulling effect, a VCO operating at twice the carrier frequency with a following divide-by-2 stage can be utilized as the local oscillator in a direct- conversion transceiver. For wireless applications such as DCS, PCS, and WCDMA, a phase noise of -113dBc/Hz at 600 kHz offset from the carrier frequency is the minimum requirement for a 3.8.4.2 GHz VCO. When the operating frequency exceeds 3 GHz, losses caused by the induced eddy current in the silicon substrate begins to degrade the Q-factor of inductors. For LC VCOs, Q of the resonance tank, which is strongly related to the phase noise, will also be pulled down by such painful loss. Therefore, considerable power consumption is usually necessary to maintain an acceptable phase noise performance in VCOs.

Fig. 2 shows the schematic diagram of our designed 3.9-4.2 GHz monolithic low-phase noise CMOS VCO with 7.5 mW DC power consumption by using the standard 0.18 ȝm CMOS technology. The circuit parameters are: PMOS transistor size: W/L = 300 ȝm/0.34 ȝm, resistor size: W/L = 4u10 ȝm/40 ȝm, varactor size: W/L = 120ȝm/1 ȝm, and inductor value = 0.56 nH. The negative conductance required to sustain a stable oscillation is generated by the cross-coupled PMOS pair. Although a NMOS or CMOS topology seems to be more power-saving, VCO cores consisting of NMOS usually suffer from excess 1/f noise. To prevent the up-conversion of low frequency noise, the tail current is defined by a poly-silicon resistor instead of an FET current source which may contribute considerable 1/f noise.

III. Experimental Results and Discussions

A. Inductors

The frequency-dependent S-parameters measurements were performed from 0.1 GHz to 40 GHz by an HP-8510C network analyzer. The measured Q-factor versus frequency characteristics of the 2.5-turn inductors in Fig. 1 are shown in Fig. 3. PGS increases the Qmax of STD IND from 10.7 (at 0-7803-9329-5/05/$20.00 ©2005 IEEE

2 4.7 GHz) to 12.69 (at 5.1 GHz). While increasing the Qmax of STD IND, the PGS IND has a lower self-resonance frequency fSR (11.4 GHz) than that (16.5 GHz) of STD IND. The measured effective inductance (Leff) versus frequency characteristics of the STD IND and the PGS IND are shown in Fig. 4. The inductances of the two inductors are almost the same (~ 2 nH) at lower frequencies and are kept constant up to 8 GHz and 12 GHz for PGS IND and STD IND, respectively.

The reason why PGS can only improve Qmax but deteriorate fSR of an inductor can be explained as follows. Based on the theory introduced in [10], substrate loss factor of Q-factor, specifically Qmax, can be improved by making the silicon substrate either close to a short circuit (i.e. PGS, etc.) or close to an open circuit (i.e. substrate transfer etc. [11]). Compared to a normal silicon substrate, a short- and an open-circuited silicon substrate make the equivalent substrate capacitance larger and smaller, respectively, which in turn result in a smaller and a larger fSR, respectively. B. 4-GHz LC VCO

The die photo of the 4-GHz CMOS LC VCO is shown in Fig. 5. The VCO can operate from 3.9 to 4.2 GHz as shown in Fig. 6. Fig. 7 shows this VCO achieves very good phase noise of -119.94 dBc/Hz at 1 MHz offset frequency. Table I is a summary of the state-of-the-art 4 to 6 GHz CMOS LC VCO, in which the “FOM” means the widely accepted figure-of-merit defined as follows [8].

) ( log 10 2 f L P f f FOM DC o '  » » ¼ º « « ¬ ª ˜ ¸¸ ¹ · ¨¨ © § ' (dBc/Hz), (1)

where f means carrier frequency, f_o ' means offset frequency, and L ' means phase noise. According to ( f) table I, the FOM of our VCO is compatible with the reported state-of-the-art 4-6 GHz CMOS LC VCO with a practical tuning range ( > ~ 5 %).

IV. Conclusions

In this paper, first, high Q-factor inductors on normal 750-Pm-thick silicon substrate in standard 0.18-Pm CMOS technology were realized by optimization of the layout of the inductors. Second, PGS was used to further improve the performance of the inductors in the frequency bands of interest. Finally, a state-of-the-art 4-GHz CMOS LC VCO with phase noise of -119.94 dBc/Hz measured at 1 MHz offset frequency is also implemented.

Acknowledgements

The authors thank UMC for IC fabrication under the UMC campus program, and NDL for assistance with measurements.

References

[1] J. N. Burghartz, D. C. Edelstein, K. A. Jenkins and Y. H. Kwark, “Spiral inductors and transmission lines in silicon technology using copper-damascene interconnects and low-loss substrates,” IEEE T. Microwave Theory and Techniques, vol. 45, no. 10, pp. 1961-1968, Oct. 1997.

[2] J. Y.-C Chang, A. A Abidi and M. Gaitan, “Large suspended inductors on silicon and their use in a 2-um CMOS RF amplifier,” IEEE Electron Device Lett., vol.14, no.5, pp. 246-248, May 1993.

[3] H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L. R. Carley, and G. K. Fedder, “Micromachined high-Q inductors in a 0.18 um copper interconnect low-k dielectric CMOS process” IEEE J. Solid-State Circuits, vol. 37, no.3, pp.

394-403, Mar. 2002.

[4] M. Ozgur, M. E. Zaghloul, and M. Gaitan, “Optimization of backside micromachined CMOS inductors for RF applications,” IEEE Int. Symp. Circuits and System, Geneva, Switzerland, May 2000, pp.V-185-188.

[5] Y. H. Xie, M. R. Frei, A. J. Becker, C. A. King, D. Kossives, L. T. Gomez, and S. K. Theiss, “An approach for fabricating high-performance inductors on low-resistivity substrates,” IEEE J. Solid-State Circuits,

vol. 33, pp. 1433-1438, Sept. 1998.

[6] C. Y. Lee, T. S. Chen, C. H. Kao, J. D. S. Deng, C. C. Yen, Y. K. Lee, J. C. Kuo, J. F. Chang, G. W. Huang, K. M. Chen, and T. S. Duh, “A Simple Systematic Procedure of Si-Based Spiral Inductor Design,” IEEE Proc. RFIC conference, pp. 619-622, June 2004.

[7] C. P. Yue, and S. S. Wong, “On-chip spiral inductors with patterned ground shields for si-based RF IC’s,” IEEE J. Solid-State Circuits, vol. 38, pp. 427-435, Mar. 2003.

[8] T. Y. Kim, A. Adams, and N. Weste, “High performance SOI and bulk CMOS 5 GHz VCO,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Philadelphia,

USA, Jun. 2003, pp. 93-96.

[9] J. Maget, M. Tiebout, and R. Kraus, “Influence of Novel MOS Varactors on the Performance of a Fully Integrated UMTS VCO in Standard 0.25-Pm CMOS Technology,”

IEEE J. Solid-State Circuits, vol. 37, pp. 953-958, July

2002.

[10] C. P. Yue, and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 743-752, May 1998.

[11] K. T. Ng, B. Rejaei, and J. N. Burghartz, “Substrate effects in monolithic RF transformers on silicon,” IEEE Trans. on Microwave Theory and Techniques, vol. 50, no. 1, pp.

377-383, Jan. 2002.

[12] T. Song, S. Ko, D. H. Cho, H. S. Oh, C. Chung, and E. Yoon, “A 5GHz Transformer- Coupled CMOS VCO Using Bias-Level Shifting Technique,” in IEEE Radio Frequency Integrated Circuits Symp. Dig., Fort Worth,

3 Fig. 1 Layouts of the 2.5-turn on-chip inductors with PGS

(PGS IND) and without PGS (STD IND)

Fig. 2 The schematic of the 4-GHz CMOS LC VCO.

Fig. 3 Measured Q-factor versus frequency characteristics of the STD IND and PGS IND inductors.

Fig. 4 Measured equivalent inductance (Leff) versus frequency characteristics of the STD IND and PGS IND inductors.

Fig. 5 The front-side die photograph of the 4-GHz CMOS LC VCO.

Fig. 6 The measured tuning range of the 4-GHz CMOS LC VCO.

Output

-V

Control Voltage

Output +

Me

a

s

ured

Q-f

a

c

to

r

Frequency (GHz)

Me

as

ure

d L

(n

H

)

Frequency (GHz)

4 Fig. 7 The measured phase noise of the 4-GHz CMOS LC

VCO.

Table I A Summary of the presented and the previously reported state-of-the-art 4 to 6 GHz CMOS LC VCO. PDC (mW) Carrier frequency (GHz) Phase noise at 1MHz (dBc/Hz) FOM (dBc/Hz) This work 0.25 Pm CMOS 7 4.2 GHz -119.94 -183.9 [9] 0.25 Pm CMOS 7.5 4 GHz -117 -180.3 [12] 0.18 Pm CMOS 5.9 5.6 GHz -116.7 -184 100k 1M 10M -150 -140 -130 -120 -110 -100 -90

P

h

a

s

e no

is

e (

d

B

c

/ Hz

)

Offset Frequency (Hz)