Narrow-Width Effect on High-Frequency
Performance and RF Noise of Sub-40-nm
Multifinger nMOSFETs and pMOSFETs
Kuo-Liang Yeh, Member, IEEE, and Jyh-Chyurn Guo, Senior Member, IEEE
Abstract—The impact of narrow-width effects on high-frequency performance like fT, fMAX, and RF noise
parame-ters, such as N Fmin and Rn, in sub-40-nm multifinger CMOS
devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower Rg and higher fMAX. However, these narrow-OD
devices suffer fT degradation and higher N Fmin, even with
the advantage of lower Rg. The mechanisms responsible for the
tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.
Index Terms—fMAX, fT, multifinger, nanoscale CMOS,
narrow width, N Fmin, RF noise, Rg.
I. INTRODUCTION
N
ANOSCALE CMOS devices adopting multifinger lay-out have been extensively used in modern RF circuits and proven successful to improve high-frequency performance, such as higher fTand fMAX, driven by gate length scaling, andlower RF noise due to lower gate resistance (Rg) from
multi-finger structure [1]–[5]. Unfortunately, the continuous increase of finger number (NF) and reduction of finger width (WF) for
smaller Rgmay lead to the penalty of lower transconductance
(gm) and larger parasitic capacitances. The former one comes
from stress-induced mobility degradation, and the latter one stems from gate-related fringing capacitances [6], [7]. Both cannot be scalable with device scaling, and the impact may dominate high-frequency characteristics in nanoscale devices.
In our previous work on multifinger devices in 90-nm CMOS technology [7], we achieved the important finding that the kind of parasitic capacitances, which cannot be removed by existing open deembedding, was contributed from the poly finger sidewall and finger-end fringing capacitances, namely,
Cofand Cf (poly end). Note that Cf (poly end)increases linearly
with NF and the impact on high-frequency performance may
Manuscript received June 14, 2012; revised September 21, 2012; accepted November 7, 2012. Date of current version December 19, 2012. This work was supported in part by the National Science Council under Grant NSC 98-2221-E009-166-MY3. The review of this paper was arranged by Editor J. C. S. Woo. K.-L. Yeh is with the The institute of Electronics Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, and also with Silicon Motion Technology Corporation, Hsinchu 30265, Taiwan (e-mail: rexyeh@yahoo. com).
J.-C. Guo is with the Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu 30010, Taiwan (e-mail: jcguo@mail.nctu.edu.tw).
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2228196
Fig. 1. Schematics of multifinger MOSFETs with different layouts. (a) Stan-dard multifinger device: WF× NF = 2 μm× 32 (W2N32). (b) Narrow-OD device: WF× NF = 1 μm× 64 (W1N64) and 0.5 μm × 128 (W05N128).
become significant in multifinger devices with very narrow WF
and very large NF. Meanwhile, ΔW caused by STI top corner
rounding (TCR) becomes a critical parameter when trying to minimize Rgby continuously increasing NF and reducing WF
[7]. Both Cf (poly end) and ΔW appear as two key factors for
an accurate extraction of effective mobility (μeff) in multifinger
devices with narrow width. Also, ΔW may offset the impact of STI stress on μeff. However, the mentioned study was focused
on dc characteristics and flicker noise limited to nMOSFETs, and the potential impact from narrow width on high-frequency performance and RF noise remains unknown and deserves further research effort.
In this paper, the impact of aggressive width scaling on fT,
fMAX, and RF noise parameters in multifinger devices will be
explored. The investigation will be carried out on both nMOS and pMOS, which were fabricated by 65-nm CMOS process, with gate length aggressively scaled to below 40 nm.
II. DEVICEFABRICATION ANDCHARACTERIZATION
In this paper, multifinger MOSFETs were fabricated in 65-nm CMOS process with gate oxide of 1.4-nm physical thickness. The gate length drawn on the layout is 60 nm, i.e.,
Ldrawn= 60 nm, and the total gate width Wtot is fixed at
64 μm. Fig. 1(a) and (b) shows multifinger MOSFET layouts, namely, standard and narrow-oxide-diffusion (OD) devices in which σ// and σ⊥ denote the longitudinal and transverse
stresses introduced from STI (OD means oxide diffusion, i.e., active area). The finger width was reduced from WF =
2 μm for standard device (W2N32) to WF = 1 μm and
WF = 0.5 μm for narrow-OD devices (W1N64 and W05N128)
to investigate the impact from layout-dependent stress (σ⊥),
TABLE I
STRESSFAVORABLE FORMOBILITYENHANCEMENT INnMOSAND pMOS, ALONGLONGITUDINAL ANDTRANSVERSEDIRECTIONS[12]
parasitic capacitances, and parasitic resistances on high-frequency performance.
S-parameters were measured up to 40 GHz by Agilent
net-work analyzer E8364B for high-frequency characterization and device parameter extraction. An open deembedding to the bot-tom metal (M1), namely, openM1, was performed to remove the extrinsic parasitic capacitances from the pads, interconnection lines, and substrate. Three-dimensional interconnect simulation was carried out using Raphael to extract the intrinsic parasitic capacitances, such as Cof and Cf (poly end) [7]. In this way,
taking openM1 deembedding and Raphael simulation, both the extrinsic and intrinsic parasitic capacitances can be eliminated to obtain the truly intrinsic gate capacitances. Also, shortM1 deembedding was done to remove the parasitic resistances and inductances. H-parameters and unilateral gain (U ) obtained from S-parameters after the mentioned openM1 and shortM1 deembedding can achieve fT and fMAX of the intrinsic device
[8]–[11]. Also, Y - and Z-parameters can be used to deter-mine the intrinsic device parameters, such as gate capacitances (Cgg and Cgd), gm, and Rg associated with the multifinger
MOSFETs.
III. LAYOUT-DEPENDENTEFFECTS ONDEVICE
CHARACTERISTICS OFMULTIFINGERMOSFET Layout-dependent stress effect becomes increasingly signif-icant with device scaling and has been known as an important factor influencing the carrier mobility, transconductance (gm),
and channel current (IDS). Table I shows a brief summary
of the stress in different directions, which can favor mobility enhancement in nMOS and pMOS, respectively [8]. The tensile stress in longitudinal direction (σ//) can enhance electron
mobility in nMOS but degrades hole mobility in pMOS. As for the transverse stress (σ⊥) of our major interest, the compressive stress from STI always leads to mobility degradation in both nMOS and pMOS [12], [13]. In this paper, narrow-OD layouts were implemented to enhance σ⊥ and investigate the impact on device characteristics, with major focus extended to high-frequency performance and RF noise.
A. STI Transverse Stress Effect ongmof Narrow-OD
nMOS and pMOS
Transconductance gm has been known as one of the key
parameters governing high-frequency performance, noise, and also dc gain (Av= gm/gds), which are of special concern in
RF and analog circuit design. Fig. 2(a) and (b) shows gm
-versus-VGTin linear region measured from nMOS and pMOS
with different multifinger layouts, such as W2N32 (standard) and W1N64 and W05N128 (narrow OD), shown in Fig. 1.
Fig. 2. Transconductance gm-versus-VGT in linear region, measured from
(a) nMOS with W2N32, W1N64, and W05N128 and (b) pMOS with W2N32 and W1N64.|VDS| = 50 mV and VGT= VGS− VT.
Note that VGT= VGS− VT is used to offset VT variations
due to inverse narrow-width effect [14]. The result for nMOS [Fig. 2(a)] indicates a monotonic degradation of gmwith WF
scaling and suggests that μeff degradation from STI σ⊥ (along
the width) is the dominant factor responsible for the lower
gmsuffered by narrow-OD nMOS. However, pMOS shown in
Fig. 2(b) reveals a dramatically different result that W2N32 and W05N128 have nearly the same gmover the full range of VGT.
This interesting phenomenon suggests that the lower μeff from
narrower WF is no longer the dominant factor determining gm
and other parameters may offset μeff degradation and recover gm to a comparable value. To explore the mechanism
under-lying the unusual narrow-width effect on gm, we propose to
revisit the fundamental I–V model for MOSFET in which the width scaling effect on the parameters other than μeffshould be
taken into consideration.
B. Device Parameter Extraction and for Narrow-Width Effect Analysis in Multifinger nMOS and pMOS
According to the linear I–V model used for CMOS devices given by (1), gm can be derived from the differential of IDS
w.r.t. VGS and written as (2). Note that the effective width
(Weff) for multifinger MOSFETs is expressed by (3) in which
ΔW represents width extension created by STI TCR. We can understand from this model that the narrower WF may lead
to lower gmdue to μeff degradation caused by larger STI σ⊥,
but an aggressive reduction of WF may result in a significant
increase of Weffdue to nonscalable ΔW and then contributes to
higher gm. The narrow-width effect on gmis determined by the
tradeoff between the lower μeff and wider Weff. To verify and
justify the mentioned argument, μeff and ΔW appear as two
key parameters and can be extracted by using our proprietary capacitance method [7]
IDS= WeffCox(inv)(VGS− VT− λVDS)μeff VDS Leff (1) gm= ∂IDS ∂VGS
= WeffCox(inv)μeff VDS Leff
(2)
Weff = (WF+ ΔW )× NF (3)
where Cox(inv)is the equivalent oxide thickness under inversion
and Leffis the effective channel length.
In the following, the basic device parameters, such as Lg,
Fig. 3. Cgg(DUT,OM1)-versus-NF extracted by using openM1 deembed-ding on multifinger MOSFETs with various WF and NFunder fixed WF× NF = 64 μm. (a) nMOS: W2N32, W1N64, and W05N128. (b) pMOS: W2N32 and W05N128.
then, μeff can be extracted with sufficient accuracy. First,
Fig. 3(a) and (b) shows Cgg(DUT,OM1)extracted using openM1
deembedding for nMOS and pMOS with various WF and NF
as specified. The Cgg(DUT,OM1)-versus-NFreveal a linearly
in-creasing function. Theoretically, the truly intrinsic Cggof
mul-tifinger devices with fixed Wtot= WF× NF should remain
constant under various NF. The increase of Cgg(DUT,OM1)
with NF suggests the existence of some parasitic capacitances,
which cannot be removed even using openM1 deembedding. Following our previous work [7], two components of gate-related fringing capacitance, such as Cof (finger sidewall) and Cf (poly end) (finger end), have been identified as the kind of
intrinsic parasitic capacitances, which cannot be eliminated us-ing existus-ing open deembeddus-ing. Accordus-ing to our capacitance analysis method, the linear function of Cgg(DUT,OM1) versus NF can be modeled by (4)–(6), in which Cf (poly end) and
Cof contribute to the slope α and intercept β, respectively.
Both Cof and Cf (poly end) can be calculated by Raphael. The
simulation based on 65-nm CMOS technology and layout parameters achieves Cof = 0.23 fF/μm and Cf (poly end)=
0.06764 fF/finger. Referring to Fig. 3, α and β extracted from
Cgg(DUT,OM1) versus NF are 0.0905 fF/finger and 52.49 fF
for nMOS and 0.111 fF/finger and 51.1 fF for pMOS. The physical gate length (Lg) can be extracted by (7), with known
β and Cof, under specified WF and NF. The results indicate
Lg= 35 and 37 nm for nMOS and pMOS, respectively. Finally,
ΔW can be extracted from (8) with given α and Cf (poly end)
and Cox(inv)Lgdetermined by (6). Interestingly, ΔW extracted
from pMOS is 77.1 nm, which is around two times larger than ΔW = 38.7 nm for nMOS. This large ΔW can contribute more than 10% Weff in W05N128, and it appears as a key
factor offsetting μeff reduction due to STI σ⊥. It can explain
why the pMOS reveals nearly the same gm between W2N32
and W05N128 [Fig. 2(b)]. Table II summarizes the device parameters extracted from the multifinger nMOS and pMOS following the mentioned extraction flow. Note that the extracted
Tox(inv) approaches the target Tox(inv) with a difference as
small as 0.5−1.0 Å. It is important to justify the accuracy and precision of the basic parameters like Cox(inv), Lg, and ΔW to
ensure an accurate determination of μeff
Cgg(DUT,OM1) = αNF + β (4)
α = (ΔW· Lg)Cox(inv)+ Cf (poly end) (5)
β =Cox(inv)Lg+ Cof
WFNF (6)
TABLE II
MULTIFINGERnMOSANDpMOS DEVICEPARAMETERS
Fig. 4. μeff-versus-VGT extracted from linear I–V for multifinger
devices. (a) nMOS: W2N21, W1N64, and W05N128. (b) pMOS: W2N32 and W05N128. Weff= NF(WF+ ΔW ). |VDS| = 50 mV and
VGT= VGS− VT. Lg= β WFNFCox(inv) − Cof Cox(inv) (7) ΔW =α− Cf (poly end) Cox(inv)Lg . (8)
C. Effective Mobility Extraction and Narrow-Width Effect
The effective mobility μeff can be extracted from linear I–V
model given by (1) and written as (9) in which Weff has been
accurately determined by including ΔW . Note that VDS is
the drain bias applied to the effective channel region defined by Leff and obtained by subtracting the voltage drop across
the parasitic S/D resistances, RS and RD. Herein, Leff, RS,
and RD can be determined by our decoupled C–V method
[15] based on the precisely extracted Lg. Fig. 4(a) and (b)
shows μeff-versus-VGTextracted from nMOS and pMOS with
specified split of WFand NF. The results indicate a monotonic
reduction of μeffwith WFscaling (both nMOS and pMOS) and
manifest the increasing impact of STI σ⊥ on μeff in
narrow-OD devices. To verify the accuracy of extracted μeff and the
influence of ΔW , μeffextracted by assuming ΔW = 0 is added
into the same plot for a comparison, as shown in Fig. 5(a) and (b) for nMOS and pMOS, respectively. We can see that μeff
determined by using extracted ΔW can achieve a good match with μeff calculated by μ0[1− k ∗ log(Wref/WF)] [13], [16].
However, the assumption of ΔW = 0 leads to certain deviation, particularly large for pMOS. Again, this verification justifies
Fig. 5. Extracted μeffwith different ΔW versus calculated μeffwith
width-dependent stress effect. (a) nMOS: ΔW = 0 and 38.7 nm, and k = 0.3465. (b) pMOS ΔW = 0 and 77.1 nm, and k = 0.1598.
the accuracy of extracted ΔW . The difference of ΔW between nMOS and pMOS suggests that STI TCR is dependent not only on STI etching profile and postetching thermal budget but also on implantation and postannealing process. The differences in gate oxide thinning and gate depletion near the STI top corner, between nMOS and pMOS, may be one more reason responsible for the ΔW difference. Note that this difference is determined not only by STI process but also by the gate stack process
μeff = IDS VDS
1
Cox(inv)(VGS− VT − λVDS)Weff/Leff
(9)
VDS= VDS,ext− IDS(RD+ RS). (10)
D. Gate Resistance Extraction and Layout Dependence in Multifinger MOSFETs
Gate resistance Rg has been recognized as the most critical
parameter determining fMAX and RF noise parameters, such
as N Fmin and Rn [8]–[10]. However, an accurate extraction
and modeling of Rgremain a challenging subject. Most of the
previous works relied on curve fitting to the measured input impedance for Rgextraction. As a result, it is difficult to figure
out a scalable Rg model, which can predict layout and bias
dependence. The mentioned problem adds the challenge to high-frequency simulation accuracy, particularly for the design with special concern of fMAX and RF noise [17]. First, an
an-alytical expression with Z-parameters, expressed by (11)–(13), was proposed for Rgextraction [18]. This Z-method requiring
measurement up to infinitely high frequency faces the limitation of existing vector network analyzer. An alternative approach by curve fitting was proposed based on the assumption that the frequency-dependent term in (11) with Agand B given by
(12) and (13) becomes negligible at sufficiently high frequency. Afterward, another Rgextraction method using Y -parameters
was presented and given by a simple formula (14) [19]. This
Y -method looks much simpler and may avoid the difficulty
in measurement to infinite frequency. Both Z- and Y -methods were applied to our multifinger devices to verify the accuracy and limitations in Rg extraction. The results indicate that Rg
extracted by these two methods reveals a dramatic difference at lower frequency but tends to converge to nearly the same value at very high frequency, up to 35–40 GHz, expressed by (15). However, this convergence is achievable only for W2N32
Fig. 6. Rg-versus-VGS extracted from Re(Z11− Z12) at very high
fre-quency for multifinger devices. (a) nMOS (W2N32, W1N64, and W05N128) and (b) pMOS (W2N32 and W05N128).
(standard) and becomes invalid for narrow-OD devices, such as W1N64 and W05N128. The major problem happens when try-ing to apply the Y -method to narrow-OD devices, in which the extracted Rgis underestimated due to overestimated Im(Y11),
by including Cof and Cf (poly end). Note that both Z- and
Y -parameters went through openM1 and shortM1
deembed-ding, but the openM1 cannot remove Cofand Cf (poly end). The
impact on Im(Y11) increases with increasing NF and leads to
underestimated Rg. The mentioned verification suggests that
Y -method cannot be applied to narrow-OD devices with very
narrow WF and very larger NF
Rg= Re(Z11− Z12)− Ag ω2+ B (11) Ag= Cds[gds(Cgs+ Cgd) + gmCgd] (CgsCds+ CgsCgd+ CgdCds)2 − gds (CgsCds+ CgsCgd+ CgdCds) (12) B = gds(Cgs+ Cgd) + gmCgd (CgsCds+ CgsCgd+ CgdCds) 2 (13) Rg= Re(Y11) [Im(Y11)]2 . (14)
For W2N32 at very high frequency up to 35–40 GHz
Rg ∼= Re(Z11− Z12)|35−40 GHz∼=
Re(Y11)
[Im(Y11)]2
|35−40 GHz.
(15) According to the aforementioned verification and identified mechanism, Z-method was adopted as a reliable solution. Fig. 6(a) and (b) shows Rg extracted from nMOS and pMOS,
respectively. The narrow-OD devices can achieve smaller Rg,
i.e., the expected benefit from smaller WF and larger NF.
nMOS and pMOS indicate similar result in layout and VGS
dependence. Fig. 7 shows that the extracted Rgversus WF can
be approached by a simple analytical model given by (16), in which the first term from poly sheet resistance (RSH(poly)) is
proportional to WF/NF and the second term from the contact
resistance of M1 to poly gate (RCT(poly)) is proportional to
1/NF. The good match between the extracted and calculated
Rgsuggests that (16) can serve as a scalable model to predict
Fig. 7. Extracted and calculated Rg-versus-WF for multifinger devices. (a) nMOS (W2N32, W1N64, and W05N128) and (b) pMOS (W2N32 and W05N128).
Fig. 8. gm,sat-versus-VGT in saturation region, measured from (a) nMOS
with W2N32, W1N64, and W05N128 and (b) pMOS with W2N32 and W1N64. |VDS| = 1.0 V and VGT= VGS− VT.
WF and NF. In the following section, the influence of Rg on
fMAX and RF noise parameters like Rn and N Fmin will be
investigated Rg= RSH(poly) 2Lg × WF NF +RCT(poly) NF + ΔRg. (16)
IV. NARROW-WIDTHEFFECT ONHIGH-FREQUENCY
PERFORMANCE ANDRF NOISE
The influence on μeff, gm, Cgg, and Rg from narrow-width
effects (STI σ⊥, TCR-induced ΔW , Cof, and Cf (poly end))
suggests an extended impact on fT, fMAX, and N Fmin, which
are key performance parameters for RF circuit design. The experimental results and detailed analysis will be described as follows.
A. Narrow-Width Effect onfT in Multifinger
nMOS and pMOS
First, Fig. 8(a) shows gm,sat-versus-VGT in saturation
re-gion (VDS= 1.0 V) measured from nMOS with standard and
narrow-OD layouts. The result reveals a monotonic degradation of gm,satwith WFscaling, which follows the same trend as that
of linear gm[Fig. 2(a)] and reflects the extended impact from
STI σ⊥ to saturation velocity. The gm,satdegradation reaches
12.1% for W05N128 compared to W2N32 (standard). As for pMOS shown in Fig. 8(b), the gm,satdegradation of W05N128
becomes much smaller to around 3%. Again, it indicates that
gm,satdegradation from compressive σ⊥can be compensated
by much larger ΔW (77.1 nm) in pMOS, which results in a
Fig. 9. Multifinger nMOS with W2N32, W1N64, and W05N128. (a) Mea-sured and calculated fT-versus-VGT(VDS= 1.0 V) and (b) Cgg-versus-VGS
extracted from Im(Y11).
Fig. 10. Multifinger pMOS with W2N32 and W05N128. (a) Measured and calculated fT-versus-|VGT| (|VDS| = 1.0 V) and (b) Cgg-versus-|VGS|
ex-tracted from Im(Y11).
significant increase of Weff and then certain compensation to gm,sat.
Fig. 9(a) shows the measured and calculated fT
-versus-VGT for standard and narrow-OD nMOS devices. Note that fT is determined by the extrapolation of |H21| to unity gain
and H-parameters can be converted from S-parameters after openM1 and shortM1 deembedding. The experimental result indicates that fT can approach 350 GHz for the standard
nMOS (W2N32), attributed to the aggressive Lg scaling to
35 nm. However, the WF scaling leads to a monotonic
degra-dation of fT. As compared to W2N32, the maximum fT of
W1N64 is reduced by 5.8%, and the degradation becomes even larger to 15.1% for W05N128, resulting in fT below 290 GHz.
Referring to the analytical model given by (17) and (18) for cal-culating fT [8], it is predicted that fT degradation is originated
from the degradation of gm,satand/or the increase of Cgg. For
narrow-OD nMOS, the smallest gm,satappearing in W05N128
[Fig. 8(a)] suggests to be one of the factors responsible for the lowest fT. Furthermore, Cggmeasured from narrow-OD nMOS
shown in Fig. 9(b) indicates 8.3% larger Cggin W05N128. Note
that the increase of Cggwith smaller WFand larger NFreveals
the impact from Cf (poly end)[6], [7]. The combined effect from
lower gm,sat and larger Cgg can explain fT degradation in
narrow-OD devices. A good match between the measured and calculated fT shown in Fig. 9(a) for nMOS with various WF
and NF justifies the accuracy of the proposed fT model. As
for pMOS shown in Fig. 10(a), W05N128 (narrow OD) reveals more than 15% degradation in maximum fT than W2N32
(standard), even though the extraordinarily large ΔW (77.1 nm) can effectively suppress gm,satdegradation [Fig. 8(b)]. Again,
the result can be ascribed to the increase of Cgg by around
Fig. 11. Measured and calculated fMAX-versus-|VGT|. (a) nMOS with
W2N32, W1N64, and W05N128 and (b) pMOS with W2N32 and W1N64. |VDS| = 1.0 V and VGT= VGS− VT.
accurately predict fT degradation suffered by the narrow-OD
pMOS fT = gm 2π C2 gg− Cgd2 (17) Cgg= Im(Y11) ω Cgd=− Im(Y12) ω . (18)
B. Narrow-Width Effect onfMAXin Multifinger nMOS and pMOS
The maximum oscillation frequency fMAXis another
impor-tant performance parameter for RF circuit design, particularly for power amplifiers. In this paper, fMAX is determined by
conventionally used unilateral gain (U ) method in which the frequency corresponding to the unit power gain is defined as fMAX, i.e., f (U = 1) = fMAX. Fig. 11(a) shows fMAX
extracted from nMOS and reveals an interesting result that the narrow-OD layout can lead to higher fMAXand the maximum fMAX of W05N128 can achieve 366 GHz, which is 24.8%
improvement over W2N32. Through an equivalent circuit anal-ysis on unilateral gain (U ), fMAX can be calculated by (19)
in which gds is the output conductance, Cgdis the gate–drain
capacitances, Ri is the real part of the input impedance, and
Rsis the source series resistance [9], [10]. This model predicts
that the higher fT and lower Rgcan enhance fMAX. Referring
to Fig. 9(a), W05N128 suffers the lowest fT and more than
15% degradation in the maximum fT compared to W2N32.
However, the smaller WF and larger NFin narrow-OD nMOS
can effectively reduce Rgas shown in Fig. 6(a). The 40% lower
Rg realized in W05N128 can overcompensate fT degradation
and contribute higher fMAX. A good agreement between the
measured and calculated fMAX shown in Fig. 11(a) justifies
the accuracy of the proposed fMAX model in (19) [9], [10].
Fig. 11(b) shows the fMAX measured from pMOS, which
indicates WF and NF effect similar to NMOS, i.e., the
nar-rower WF and larger NF can yield higher fMAX. The
narrow-OD pMOS W05N128 can offer 13.5% improvement in the maximum fMAXthan W2N32 even though it suffers 15% lower fT[Fig. 10(a)]. Again, Fig. 6(b) shows around 30% lower Rgin
W05N128 than in W2N32 and explains the origin responsible for fMAXenhancement. The proposed fMAXmodel showing a
good agreement with measured fMAX can consistently predict
the layout dependence and guide device optimization design
fMAX=
fT
2Rg(gds+ 2πfTCgd) + gds(Ri+ Rs).
(19)
Fig. 12. Noise parameters of nMOS (standard: W2N32; narrow OD: W1N64 and W05N128). (a) Measured and calculated N Fmin, (b) measured and
calculated Rn, (c) Re(Yopt), and (d) Im(Yopt) measured under VGS= 0.7 V
and VDS= 1.0 V.
C. Narrow-Width Effect on RF Noise in Multifinger nMOS and pMOS
The proliferated impact from layout-dependent stress, para-sitic capacitances, and, most importantly, Rgon high-frequency
noise parameters appears as one more key topic for RF circuit design, particularly for low-noise amplifiers using nanoscale CMOS devices. Note that high-frequency noise measurement was carried out using ATN-NP5B system with NP5 controller, a noise figure meter (HP8970B), a remote receiver module, a mismatch noise source, a noise source, a network analyzer (HP 8510), and a dc power supply (HP4142).
Fig. 12(a)–(d) shows four noise parameters, such as N Fmin, Rn, Re(Yopt), and Im(Yopt) measured from nMOS under VDS= 1.0 V and VGS= 0.7 V corresponding to maximum gm,sat. Note that N Fmin is the minimum noise figure, Rn is
the equivalent noise resistance, and Yoptis the optimum source
admittance achieving N Fmin. Unfortunately, W05N128 with
the smallest WF and Rg suffers 0.2–0.5 dB higher N Fminin
9-18 GHz. Rn shown in Fig. 12(b) indicates very minor
dif-ference among three layouts. However, Re(Yopt) and Im(Yopt)
shown in Fig. 12(c) and (d) reveal significant increase (absolute value) in W05N128 at frequency above 9 GHz. An analytical model for noise parameters derived from noisy two-port net-work given by (20)–(22) [20] is employed to explain the layout-dependent effect on N Fmin and Rn. According to (20) and
(21), the increase of either Rnor Re(Yopt) will lead to higher N Fminand the calculated N Fminmatch with measured data in
terms of frequency and layout dependence, i.e., W 05N 128 >
W 1N 64 > W 2N 32, as shown in Fig. 12(a). This proven
model combined with Fig. 12(b) and (c) for measured Rnand
Re(Yopt) indicates that the increase of Re(Yopt) is the primary
factor responsible for higher N Fminin narrow-OD nMOS. The
aforementioned analysis is applied to measured noise param-eters before deembedding, and the increase of Re(Yopt) and |Im(Yopt)| in narrow-OD device is originated from larger Cgg
due to more parasitic capacitances. Regarding the WF scaling
effect on Rn, further analysis on three key elements given by
Fig. 13. Multifinger nMOS with W2N32, W1N64, and W05N128. (a) Mea-sured Rn, Rg, and gdo/g2mversus frequency. (b) Measured γmeaand γmodel
for best fitting to frequency dependence of γmea. VDS= 1.0 V and VGS=
0.7 V.
Fig. 14. Noise parameters of pMOS (standard: W2N32; narrow OD: W05N128). (a) Measured and calculated N Fmin, (b) measured and calculated
Rn, (c) Re(Yopt), and (d) Im(Yopt) measured under VGS=−0.7 V and
VDS=−1.0 V.
Fig. 15. Multifinger pMOS with W2N32 and W05N128. (a) Measured Rn, Rg, and gdo/g2mversus frequency. (b) Measured γmeaand γmodelfor best
fitting to frequency dependence of γmea. VDS=−1.0 V and VGS=−0.7 V.
Rg in narrow-OD devices happens to be cancelled out by the
increase of the second term, i.e., γ· gdo/gm2, due to lower gm
from compressive σ⊥ and γ > 1 shown in Fig. 13(b). Note that γ represents excess noise factor and γ > 1 comes from short-channel effect. The increase of γ at lower frequency can be ascribed to significant substrate potential variation [21]. Fig. 14(a)–(d) shows four noise parameters of pMOS with lower Rnbut significantly higher Re(Yopt) for W05N128. The
lower Rn is attributed to smaller Rg [Fig. 6(b)] and lower γ.
However, the higher Re(Yopt) still plays as the dominant factor
and leads to 0.2–0.5 dB higher N Fminthan W2N32. Again, the
proposed model (20)–(22) and Rnanalysis made in Fig. 15 can
consistently predict the measured N Fminand Rn and explain
the narrow-width effect
Fmin= 1 + 2RnRe(Yopt) [1 + RnRe(Yopt)] (20) N Fmin= 10· log Fmin (21)
Rn ≈ Rg+ γ
gdo g2
m
(γ > 1 for short channel). (22)
V. CONCLUSION
Narrow-OD MOSFET W05N128 with four times smaller
WF/larger NF than the standard multifinger device W2N32
can achieve 40%/30% lower Rg and 24.8%/13.5% higher
fMAX for nMOSFET/pMOSFET. The maximum fMAX can
reach 366 GHz for 35-nm nMOS and 155 GHz for 37-nm pMOS. However, these narrow-OD devices, even with the advantage of lower Rg, suffer lower fT and higher N Fmin. The gmdegradation caused by STI compressive σ⊥and the increase
of Cgg due to finger-end fringing capacitance are identified as
two layout-dependent factors responsible for fT degradation in
narrow-OD devices. The increase of measured N Fmin before
deembedding can be ascribed to the increase of Re(Yopt) also
due to larger Cgg. The lower Rgcannot guarantee lower Rndue
to a competing factor from gmdegradation. The narrow-width
effects on high-frequency performance and RF noise and the mechanism underlying the tradeoff between different param-eters provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology.
ACKNOWLEDGMENT
The authors would like to thank the support from the National Device Laboratory for noise measurement and the Chip Implementation Center for test key tape-out and device fabrication.
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Kuo-Liang Yeh (M’09) is currently working toward
the Ph.D. degree in electronics engineering at Na-tional Chiao Tung University, Hsinchu, Taiwan.
He is currently a Senior Manager with Silicon Motion Technology Corporation, Hsinchu.
Jyh-Chyurn Guo (M’06–SM’07) received the Ph.D.
degree in electronics engineering from the National Chiao-Tung University (NCTU), Taiwan.
She is currently a Professor in the department of electronics engineering, NCTU. She has published more than 70 technical papers and is the holder of 19 U.S. patents
