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InAs Thin-Channel High-Electron-Mobility Transistors with Very High Current-Gain Cutoff
Frequency for Emerging Submillimeter-Wave Applications
View the table of contents for this issue, or go to the journal homepage for more 2013 Appl. Phys. Express 6 034001
(http://iopscience.iop.org/1882-0786/6/3/034001)
InAs Thin-Channel High-Electron-Mobility Transistors with Very High Current-Gain
Cutoff Frequency for Emerging Submillimeter-Wave Applications
Edward-Yi Chang1, Chien-I Kuo1, Heng-Tung Hsu2, Che-Yang Chiang2, and Yasuyuki Miyamoto3
1Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C. 2Department of Communications Engineering, Yuan Ze University, Chungli 32003, Taiwan, R.O.C.
3Department of Physical Electrons, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
E-mail: edc@mail.nctu.edu.tw
Received January 15, 2013; accepted January 31, 2013; published online February 18, 2013
60 nm InAs high-electron-mobility transistors (HEMTs) with a thin channel, a thin InAlAs barrier layer, and a very high gate stem structure have been fabricated and characterized. The thickness of the channel, as well as that of the InAlAs barrier layer, was reduced to 5 nm. A stem height of 250 nm with a Pt-buried gate was used in the device configuration to reduce the parasitics. A high DC transconductance of 2114 mS/mm and a current-gain cutoff frequency (fT) of 710 GHz were achieved atVDS¼ 0:5 V. # 2013 The Japan Society of Applied Physics
S
tate-of-the-art high-electron-mobility-transistor (HEMT) technologies are capable of providing frequency conversion and amplification up to the submillimeter-wave frequency regime (>300 GHz) for ultrawide-band communication, imaging systems, remote atmospheric sensing, and space exploration applications.1) Recent literature reported characteristics of InGaAs/InAlAs HEMTs with a considerably high fT and maximum oscillation frequency ( fmax) exceeding 600 GHz.2–8)Efforts devoted to increasing the frequency limits of operation included gate-length scaling,9,10)increasing the In content of transistor channels, narrowing the source–drain spacing,6) reducing the barrier layer or channel thickness to enhance the electron transport properties, reducing the parasitic resistances or capacitances, and improving the short channel effect.11) However, further scaling of the relevant device dimensions may require combinations of other device techniques such as optimal channel aspect ratio and high gate stem for future ultrahigh-speed applications.
The combination of 60 nm Pt-buried gate and stem height of 250 nm InAs channel HEMT with a thin channel and InAlAs barrier layer was fabricated successfully. The thick-nesses of both the channel and InAlAs barrier layer were reduced to 5 nm. A thin InAlAs barrier layer is typically preferable for reducing the resistance across the Schottky barrier InAlAs/InAs heterostructure and achieving a high transconductance.12)The stem height of the gate was 250 nm to minimize the parasitics.4) The fabrication process was simplified through the growth of a thin barrier layer and Pt-buried gate during passivation to maintain an optimal channel aspect ratio compared with the two-step recess technique.13) The fabricated 60 nm devices demonstrated excellent DC and RF characteristics that benefitted from the reduction of parasitic resistance/capacitance and improve-ment of the channel aspect ratio and output conductance.
The epitaxial layer structure of the InAs thin-channel device was grown by MBE on a 3-in. InP substrate, as shown in Fig. 1. The structure consisted of a 600-nm-thick In0:52 -Al0:48As buffer, a thin 2 nm pure InAs layer with 1 nm In0:7Ga0:3As upper sub-channel and 2 nm In0:7Ga0:3As lower subchannel, a 3-nm-thick InAlAs spacer, a Si -doping with 5 1012cm2, a 2-nm-thick InAlAs barrier, and a 3-nm-thick InP etching stop. For the multilayer cap structure, 15-nm nþ-In0:52Al0:48As (2 1018cm2), 15-nm nþ-In0:53 -Ga0:47As (2 1019cm2), and 4-nm nþ-In0:65Ga0:35As
(2 1019cm2) layers were used from bottom to top to reduce the potential barrier across the undoped Schottky barrier, parasitic source/drain resistances, and contact resistance and to assist the electron tunneling under ohmic contact in such ultrahigh-speed HEMTs. After removing the cap layer, the measured room-temperature two-dimensional electron gas (2DEG) density and electron mobility were 3:02 1012/cm2 and 11,100 cm2V1s1, respectively.
For the device fabrication, mesa isolation was conducted using a wet chemical phosphoric-based solution. A mesa sidewall was also obtained by using the mixture solution of succinic acid, H2O2and NH4OH. After surface pretreatment with the diluted HCl solution for 60 s, a 1.83m ohmic con-tact spacing between source and drain electrodes was formed by using nonalloyed Au/Ge/Ni/Au (20/40/14/220 nm). The low ohmic contact resistance of 0.018 mm (with cap) and the channel sheet resistance of 119/ (without cap) were attained by TLM. Subsequently, the recess engineering was performed carefully by using a citric acid/hydrogen peroxide mixture to etch the multilayer cap and controlling the side-recess length precisely.14)Finally, a 60 nm T-shaped gate was formed with a Pt (4 nm)/Ti (20 nm)/Pt (20 nm)/ Au (250 nm) metal stack. After gate metal deposition, 100-nm-thick SiNx was deposited as a passivation layer using PECVD at 250C for 1 h, which also caused the Pt front contact to react with the InP stop layer and In0:52Al0:48As barrier layer, in other words, forming a Pt-buried gate. The inset image shows the 60 nm T-shaped gate with a stem height of 250 nm (Fig. 1). In addition, the Pt fully diffused into the Schottky barrier and improved the gate stability during passivation. The gate-to-channel distance was esti-mated at approximately 4 nm and the lateral recess length was approximately 70 nm.
Figure 2(a) shows the measured DC current–voltage char-acteristics of 60 nm gate InAs thin-channel HEMTs with 2 20 m2gate width. A favorable saturation with excellent pinch-off behaviors is observed in the figure. The on resist-ance RON was calculated at approximately 0.49 mm at a VGS of 0.3 V for the Lg¼ 60 nm D-mode HEMTs. Smaller output conductance values were obtained compared with the device structure in a previous study,15) in which a thicker channel and a thicker InAlAs barrier layer were used. The dependence of the output conductance (go) on the aspect ratio (defined as the gate length divided by the total thickness of the channel and barrier layer) is plotted in Applied Physics Express 6 (2013) 034001
034001-1 # 2013 The Japan Society of Applied Physics http://dx.doi.org/10.7567/APEX.6.034001
Fig. 2(b) for various gate lengths of 60, 80, and 100 nm. A higher yields a lower go value, which implies that scaling of only the gate length is not sufficient for the reduction of the output conductance. The measured DC transconductance
gmand drain current versus VGSwith various Lg values are shown in Fig. 3. An increase of peak gm value from 1726 to 2114 mS/mm was observed as the Lgwas scaled down from 100 to 60 nm. The short gate-to-channel distance and the low source resistance (0.15 mm) are the main reasons for such high gm due to the improvement of carrier transport prop-erties. Gate leakage current for thin-barrier devices with various gate lengths is shown in the inset of Fig. 3. For such device, the gate leakage current was slightly higher than those of our previous devices, which indicates a trade-off between the gate leakage current, and high output con-ductance for such thin-barrier HEMTs.
The RF performance was characterized from 2 to 110 GHz by using an HP 8510XF network analyzer with E7352 test heads calibrated by using a standard load-reflection-reflec-tion-match method. The procedures of small-signal equiva-lent circuit modeling with the removal of the parasitic capacitances from the probing pads followed those described in Refs.16–18. The extracted parasitic capacitance at the gate-source end was 11.3 fF and that at the drain–source end
Fig. 1. Schematic view of thin-channel InAs HEMT structure. The inset SEM images are the high-stem T-gate.
0 100 200 300 400 500 600 700
Drain current (mA/mm)
Drain voltage (V) VGS = -0.3 V ~ 0.3 V, step 0.1 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 (a) 0 200 400 600 800 1000 0 200 400 600 800 1000 1200 1400 Output conductance g 0 (mS/mm)
Current density (mA/mm)
Lg = 100 nm, α = 11.1 Lg = 60 nm, α = 6.7 Channel thickness = 10 nm Lg = 80 nm Channel thickness = 5 nm VDS = 0.5 V
Channel aspect ratio, α = Lg/(d + dc)
α = 4.4
(b)
Fig. 2. (a) Drain–source current versus drain–source voltage curve for 60 nm device; (b) output conductance as a function of drain current for various channel-thicknesses. -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0 100 200 300 400 500 600 700 60 nm 100 nm Gate voltage (V)
Drain current (mA/mm)
0 300 600 900 1200 1500 1800 2100 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 10-8 10-7 10-6 10-5 10-4 IG (A/ μ m) VGS (V) 60 nm 100 nm T ransconductance (mS/mm)
Thin Channel InAs HEMTs VDS = 0.5 V
Fig. 3. Transconductance versus gate–source voltage with 60 and 100 nm gate lengths. The inset figure is the Schottky gate leakage current for these fabricated devices.
E.-Y. Chang et al. Appl. Phys. Express 6 (2013) 034001
was 9.5 fF. The de-embedded current gain (H21), maximum stable gain (MSG), Mason’s unilateral power gain (U), and stability factor (K) as functions of frequency at VDS¼ 0:5 V and VGS¼ 0:25 V are plotted in Fig. 4(a). The predictions of the equivalent circuit model are also included in the same figure. The fT and fmax were extracted by extrapolating H21 and U with a20 dB/decade slope to be 710 and 478 GHz, respectively. Measurement on multiple devices using differ-ent test systems was performed for verification purposes.
To avoid the ambiguity during the extrapolation procedure, we have also applied Gummel’s approach [Eq. (5) in Ref.19] to determine fT. The slope of the imaginary component of the reciprocal of the current gain versus frequency, taken from the low-frequency portion of the measurement range, was plotted in Fig. 4(b). Equation (3) in Ref.20was applied for fmax. Both of these equations yielded good consistency. The large difference in fT and fmax for the device was mainly because of the narrow-side recess length (Lside).11)The small Lside concentrates the applied drain voltage in this short recess region to increase the lateral electric field under the gate electrode, which boosts the electron velocity and causes the high fT.21)A possible tradeoff between current gain and power gain can be made depending on the applications. We
believe that the superior performance is attributed to the successful combination of high electron mobility of InAs, low parasitic resistance and capacitance obtained using a high-gate-stem structure, and the optimal channel aspect ratio through the use of the thin channel and barrier layer.
In summary, 60 nm InAs thin-channel HEMTs with a stem height greater than 250 nm and 5-nm-thick barrier layer thickness were characterized for frequencies in the submillimeter-wave range. The device exhibited a consider-ably high DC gmof 2,114 mS/mm and a high fTof 710 GHz when biased at VDS ¼ 0:5 V, indicating that the device is an excellent candidate for emerging submillimeter-wave applications. This high fT is attributable to the use of a thin InAs transistor channel, a thin InAlAs barrier layer, and a Pt-buried gate, which reduces the gate-to-channel distance to 4 nm, thus, improving the channel aspect ratio. In addi-tion, the use of a multicap layer and a high gate stem decreases the source and gate resistances, as well as the overall capacitance of the device.
Acknowledgments The authors would like to acknowledge the assistance
and support from the National Science Council, Taiwan, R.O.C., under contracts NSC 99-2120-M-009-005 and NSC101-2221-E-155-047. Part of this work was also supported by the ‘‘Nanotechnology Network Project’’ of the Ministry of Education, Culture, Sports, Science and Technology, Japan (MEXT).
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