高性能金氧半製程相容射頻電感器的研製

行政院國家科學委員會專題研究計畫 成果報告

高性能金氧半製程相容射頻電感器的研製

計畫類別： 個別型計畫

計畫編號： NSC91-2215-E-006-014-

執行期間： 91 年 08 月 01 日至 92 年 07 月 31 日 執行單位： 國立成功大學微電子工程研究所

計畫主持人： 方炎坤

計畫參與人員： 梁孟松 陳重輝 陳碩懋 陳世芳

報告類型： 精簡報告

處理方式： 本計畫可公開查詢

中 華 民 國 92 年 8 月 25 日

行政院國家科學委員會補助專題研究計畫 R 成 果 報

告 □期

中進度

報 告

高性能金氧半製程相容射頻電感器的研製

The study and manufactur e of high per for mance CMOS

pr ocess compatible r adio fr equency inductor

計畫類別： R 個別型計畫 □ 整合型計畫

計畫編號：NSC 91 － 2215 － E － 006 － 014 －

執行期間： 91 年 8 月 1 日至 92 年 7 月 31 日

計畫主持人：國立成功大學電機系/微電子工程所 方炎坤 教授

共同主持人： 台灣積體電路公司研發部 梁孟松 協理

計畫參與人員： 陳重輝、陳碩懋、陳世芳

成果報告類型(依經費核定清單規定繳交)： R 精簡報告 □完整

報告

本成果報告包括以下應繳交之附件：

□赴國外出差或研習心得報告一份

□赴大陸地區出差或研習心得報告一份

□出席國際學術會議心得報告及發表之論文各一份

□國際合作研究計畫國外研究報告書一份

處理方式：除產學合作研究計畫、提升產業技術及人才培育研究

計畫、列管計畫及下列情形者外，得立即公開查詢

□涉及專利或其他智慧財產權，□一年□二年後可公開

查詢

執行單位：國立成功大學

中 華 民 國 92 年 9 月 22 日

行政院國家科學委員會專題研究計畫成果報告

高性能金氧半製程相容射頻電感器的研製

The study and manufactur e of high per for mance CMOS pr ocess

compatible r adio fr equency inductor

計畫編號：NSC 91-2215-E-006-014 執行期間：91 年 8 月 1 日至 92 年 7 月 31 日

計畫主持人：方炎坤 教授 國立成功大學 微電子工程研究所/電機工程系 (e-mail: ykfang@eembox.ee.ncku.edu.tw)

一、中英文摘要

本 計 畫 旨 在 研 究 於 矽 基 板 上 製 作 與

CMOS 製 程 相 容 （ CMOS process

Compatible）的高性能射頻電感器。利用 ULSI CMOS 技術的後段製程（Back-End process）研製各種不同結構之 air gap 電感

器，如平面螺旋結構（spiral）、立體線圈結

構（Solenoid）、堆疊式螺旋結構（stacked spiral） 以應各 種不 同 場合之 射頻 電路使 用。本報告主要在研究新型平面螺旋結構 的高性能射頻電感。

關鍵字：旋臂式電感、CMOS 技術、基板 耦合損

Complementary

metal-oxide-semiconductor (CMOS) technologies are widely adopted in the low cost radio frequency (RF) applications for its high fT transistors that can compete with the GaAs IC’s in the low gigahertz frequency ranges. [1] However, in a conventional RF on-chip planar spiral inductor which

embraced by the SiO2, the capacitive and substrate losses can result in interference with other devices through substrate coupling due to its large area, thus making it difficult to integrate a high energy RF power amplifier and a sensitive RF receiver circuit on the same die, since it is necessary to keep each planar on-chip inductor away to lower the substrate coupling noise. [2] This report presents the study on the electrical characteristics between conventional aluminum on-chip spiral inductors on silicon substrate and various structures of the CMOS process compatible suspended RF inductor [3]. Simulation results indicate the substrate coupling loss of the suspended inductor is 13.6dB lower than the conventional on-chip spiral inductor at 2.4GHz. Four types of suspended spiral inductors with different percentage of suspended area are developed and studied extensively to provide optimal inductor characteristics and physical structure support. Experiment shows that when

frequency increase, more energy loss from inductor to the substrate, therefore, less energy transfer through the inductor and dissipated in the inductor, leading the suspended inductor has lower effective resistance compared with the conventional on-chip inductor. The result also shows the maximum Q were improved from 3.8 at 1.25Ghz in the conventional on-chip inductor to 6.6 @ 2 GHz in the CMOS compatible suspended inductor with supporting pillar.

Keywords: Inductor, suspended inductor, CMOS technology, substrate coupling loss

二、計畫的緣由與目的

We had reported the pillar supported suspended on-chip spiral inductor [2] on CMOS compatible process. In this report, various new structures of suspended on-chip spiral inductors with different percentage of suspended area had been developed. To ease the use of RF design, the electrical characteristics of all the supported inductors had been measured carefully by embedding the open GSG pads parasitics.

三、研究的方法與成果

各種懸空結構的新型射頻電感器

The samples in this study were prepared using conventional 0.18um CMOS technology. After having finished the single-layer inductor with a thickness of 1.2ìm and desired pattern using the third TiW/Al-1%Si/TiW metalization process, the windows of the inductor were opened over the proposed on-chip inductor by removing the Si3N4 and SiO2 layers on the top using the process for the opening of bonding pad window. Then the slope etcher consists of 107ml DI water, 509ml 10:1 BOE, 35ml 49%

HF, and 349ml CH3COOH per one liter at 25°C was applied for one minute to form the air gap. That is to remove the SiO2 embraced the inductor. Since the dielectric constant of air is about one fourth (1/4) of the SiO2, the areas of air-gap where the capacitance without oxide layers can be lowered effectively almost 75% capacitances of oxide meaning that the capacitive and substrate

losses can be reduced obviously. The SiO2 embraced the on-chip inductor, and the post-processing wet-etch removes the SiO2 underneath the opening pad window area and form the air-gap in the inductor and between itself and the substrate.

There are five structures of the on-chip spiral inductors studied here as shown in Fig.1. As shown in Fig.1 (a), the conventional inductor which was buried inside the SiO2 inter-metal-dielectric. For the proposed CMOS process compatible suspended spiral inductor, to strengthen the structure of the inductors, the metal pillars which marked as the dashed black ellipse in Fig.1(b) were formed by the underneath metal layers, contacts and polysilicon layers, thus support the suspended inductor after the air gap formation. The percentage of the suspended area of CMOS process compatible suspended spiral inductor is near 100 %, since all the SiO2 underneath the inductor was removed except the pillars which support the inductor.

To compare the effects of the energy loss in the parasitic oxide layer, three inductor with different percentage of the suspended area were designed. As shown in Fig.1 (c), the suspended inductor with the diamond opening windows whose suspended area is only 18.8% of the inductor. As shown in Fig.1 (d) and Fig. 1(e), the suspended inductor with the circle opening windows whose suspended area is 43.5% of the inductor, and the suspended inductor with the triangle opening windows whose suspended area is 90.4% of the inductor. The suspended inductor with diamond, circle, triangle opening window patterns to replace the pillar to support the inductor thus create different suspended area, all three suspended inductor with diamond, circle, triangle opening window patterns successfully remove the SiO2 embraced the inductor underneath the opening windows, while the rest area of the inductor support the suspended inductor from collapse.

基礎元件電性參數量測

After the extraction of the significant parameters from de-embedding Y-matrix, the parameters in the Ashiby’s model of the

on-chip inductor can be extracted as shown in table 1.

Since the suspended inductor with pillars’ support is filled with air-gap, the percentage of the suspended area is 99.5%.

The percentage of the suspended area formed by the wet-etch removed the SiO2 underneath the with air-gap for the diamond, circle, and triangle opening pad window patterns are about individually 18.8 %, 43.5 %, and 90.4

% areas of the entire planar inductors, and the capacitances in air-gap are proportional to the area of air-gap. Since the effective dielectric constants of SiO2 and air are 4 and 1, respectively. Lower capacitive coupling and oxide capacitance represent that lower capability of penetration into substrate through the air-gap layer by electrically induced currents can result in lower dissipated energy, more energy can pass the Ls and Rs from port 1 to port 2 in the Ashby’s Model in Fig.2, reduce the loss energy less to higher the quality factor and make the inductor more inductive at high frequencies.

As shown in table 1, Cf, Cox1 and Cox2 are in proportional to the suspended area.

And the series resistance, Rs, is unchanged after the wet-etch, since the Al in the inductor and the ambient oxygen in the air reacts and forms the alumina which can protect the Al-1%Si from further oxidation. The measurement Csub1, Csub2, Rsub1 and Rsub2 are similar as shown in table 1.

The inductor of all five inductors are 23nH at 200Mhz, and their parasitic capacitors, Cf, Cox1, Cox2, Csub1 and Csub2 are less than 120fF, therefore, most of the signal at low frequencies pass the inductor Ls and the series resistance Rs.

S-參數,等效阻抗,等效電感與品質因數的量 測

As shown in Fig.3, the smith charts for two-port S-parameters shows when the frequency is low, the S11 of all five inductors are the same. When the frequency goes higher and higher, most of the signal AC coupled directly through the Cf from port 1 to port2, through Cox2 and Csub1 from port1 to the ground, through Cox2 and Csub2 from

port 2 to the ground, coupled from port 1 via Cox1 and converted as current through Rsub1 to the ground, coupled from port 2 via Cox2 and converted as current through Rsub2 to the ground, making the extracted the S21 and S11 more capacitive at high frequencies, as shown in the insert of Fig.3. As shown in Fig.4, when the frequency is lower 1GHz, the inductances of all five inductors are nearly the same. As the frequency goes higher, the effective inductance increases due to most of the energy flow through the inductor. As the frequency goes higher and higher, and the effective inductance finally decades to zero, it is called the self-resonance frequency as shown in Fig. 5 and table 1.The self-resonance frequency of the conventional on-chip spiral inductor is only 2.8Ghz and the lowest, since the capacitance between the inductor interconnections, Cf, as shown in the Ashiby’s model in Fig. 2 shorts port 1 and port 2 at lower frequency than other suspended inductors due to the Cf of the conventional on-chip inductor has higher effective dielectric constant as shown in table1. The enhancement of maximum quality factor, Qmax, frequency of Qmax, fQmax, and self-resonance frequency, fsr, are proportional to the percentage of the suspended areas in the inductor as observed in table 1.

As shown in Fig. 5, similarly, all five inductors with different percentages of suspended area measured same resistance lower than 1.8Ghz. As frequency of the signal at port 1 goes higher, not only the skin effects raise the resistance, the coupled lost from Cox1 to Rsub1 and from Cox2 to Rsub1 also diminish the signal that pass through the resistor, making the measured signal at port 2 is smaller, both lead the effective resistance higher. As the measured frequency higher and higher, the signal coupled from Csub1 to Csub2, thus forming a resistive element at high frequency, leading the effective resistance become smaller.

The quality factor versus measured frequencies of all five inductors was plots in Fig.6. The enhancement of maximum quality factor, Qmax, frequency of Qmax, fQmax,

and self-resonance frequency, fsr, are proportional to the areas of the opening bonding pad windows with lower capacitive coupling and oxide capacitances observed in table 1. Since the dielectric constant of air is about one fourth (1/4) of the SiO2, the areas of air-gap where the capacitance without oxide layers can be lowered effectively almost 75% capacitances of oxide meaning that the capacitive and substrate losses can be reduced obviously. The suspended area in the inductor with air-gap of the diamond, circle, triangle window patterns and suspended inductor with pillars are about individually 18.8 %, 43.5 %, 90.4% and 99.5 % areas of the entire planar inductors, and the capacitances in air-gap are proportional to the area of air-gap. Therefore, in Fig. 6 and recorded in table 1 the enhancement of maximum quality factor, Qmax, frequency of Qmax, fQmax, and self-resonance frequency, fsr, are proportional to the areas of the opening bonding pad windows with lower capacitive coupling and oxide capacitances.

Therefore, as shown in Fig. 6 and table 1 the enhancement of maximum quality factor, Qmax, frequency of Qmax, fQmax, and self-resonance frequency, fsr, are proportional to the areas of the opening bonding pad windows with lower capacitive coupling and oxide capacitance. In all of the proposed inductors with different opening bonding pad window patterns, the suspended inductors have the best optimum performance of Qmax, fQmax, and fsr due to its biggest area of air-gap layer. For instance, the maximum Q factor of the conventional and the suspended inductor with the same geometry are 3.8 (at 1.2 GHz) and 6.6 (at 2 GHz), respectively.

Almost 73.7 % improvement in the magnitude and 66.7 % in the frequency of the maximum Q factor are attained. The table 1 not only shows the model parameters of all the inductors, but also the Q factor involved significant frequency at 2.4Ghz.

四、結果與討論

In this report, the coupling loss between the substrate and the inductor is reduced by removing the SiO2 embraced the inductor by wet-etch, thus lowering the dielectric constant

of the in standard CMOS technology with Aluminum metal interconnection. The electrically capacitive coupling loss not only reduce the Q factor, but also become a source of substrate coupling due to its big area at high frequencies in on-chip spiral inductors.

Suspended the inductor in the air can lower the capacitive coupling between the inductor to the substrate, thus lowering the dissipated energy in inductor, and higher the quality factor. Nevertheless, reducing the capacitance between the inductor and the substrate can provide better isolation of noise, thus preventing the inductor interfering with another inductor or noisy high-speed digital circuits through the substrate. In this study, four structures of suspended inductor with different percentage of suspended area are designed, developed and compared with the conventional on-chip spiral inductor. The SiO2 embraced the on-chip inductor is removed by wet-etch and either the pillar or the remaining SiO2 outside the opening pad window support the inductor from collapse.

Compared with the conventional on-chip inductor embraced with SiO2, the suspended on-chip spiral inductor improves the self-resonance frequencies, maximum quality factor, and frequency at maximum Q by 63%, 65%, and 61%, respectively. Ignore the physical support of the inductor, the percentage of suspended areas in the inductor is proportional to the reduction of substrate loss, the reduction of noise interference, the increase of quality factor, the reduction of effective resistance at the same frequency, and the increase of the self-resonance frequency

五、計畫成果自評

This project successfully developed new suspended on-chip inductors that have stronger structure than the one we reported in [3]. Moreover, all the parasitic components of these on-chip inductors were extracted based on Ashiby’s model and discussed in depth.

The R, L, and Q were also measured after de-embedding. The complete electrical characterization can help the circuit designer to build their RF blocks based on these parameters.

Thanks to the great support from NSC 91-2215-E-006-014 on this project.

六、參考文獻

[1] A. M. Niknejad and R. G. Meyer, “Analysis,

design, and optimization of spiral inductors and transformers for Si RF IC’s,” IEEE J. Solid-State Circuits, vol. 33, pp. 1470-1481, Oct. 1998.

[2] Tony Yeung, Alan Pun, Zhiheng Chen, Jack Lau, and Francois J.R. Clement, “Noise coupling in heavily and lightly doped substrate from planar spiral inductor,” IEEE International Symposium on Circuits and Systems, pp.1405-1408, 1997.

[3] Chung-Hui Chen; Yean-Kuen Fang; Chih-Wei Yang; C.S. Tang, ”A deep submicron CMOS process compatible suspending high-Q inductor”, IEEE Electron Device Letters, Volume: 22 Issue:

11 , Nov. 2001 pp. 522 –523.

[4] K. B. Ashby, A. Koullias, W. C. Finley, J. J.

Bastek, and S. Moinian,”High Q inductors for wireless applications in a complementary silicon Bipolar process,” IEEE J. Solid-State Circuits, vol. 31, pp. 4-9, Jan.1996.

[5] M. Park, S. Lee, C. S. Kim, H. K. Yu, and K. S.

Nam, “The detailed analysis of high CMOS-compatible microwave spiral inductors in silicon technology,” IEEE Trans. Electron Devices, vol. 45, pp. 1953-1959, Sept. 1998.

[6] J. Y.-C. Chang, A. A. Abidi, and M. Gaitan,

“Large suspended inductor on silicon and their use in a 2-ìm CMOS RF amplifier,” IEEE

Electron Device Letter, vol. 14, pp.1953-1959,Sep.1998.

[7] Yue, C.P. and Wong, S.,”On-chip spiral inductors with patterned ground shields for Si-based RF IC’s,” IEEE Symposium on VLSI Circuits, pp.85-86, 1997

[8] Jan Craninckx, and Michiel S. J. Steyaert, “A 1.8-GHz Low-Phase-Noise CMOS VCO using optimized hollow spiral inductors,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, MAY 1997

[9] Hanjin Cho, and Dorothea E. Bulk, “ A Three-Step Method for the De-Embedding of High-Frequency S-Parameter Measurements,”

IEEE Transactions on Electron Devices, vol. 38.

no. 6, JUNE 1991

[10] G. D. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave Circuit Design Using Linear and Nonlinear Techniques, New Your, John Wiley and Sons, 1990.

[11] R. B. Merrill, T. W. Lee, Hong You, R.

Rasmussen, and L. A. Moberly, “Optimization of High Q Integrated Inductors for Multi-Level Metal CMOS,” IEEE IEDM, pp. 38.7.1-38.7.3, 1995

(b)

(c) (a)

(d)

(e) Fig.1

port 1

Cf

Ls Rs

Cox1 Cox2

Csub1

Rsub1

Rsub2

port 2

Csub2

Fig.2

S11 comparison for different patterns

S11_conventional S11_diamond S11_circle S11_triangle S11_suspended 0.2

0.5

1.0

-0.2

5.0 2.0

-5.0

-2.0

-1.0 -0.5

2.0 5.0 0.5 1.0

0.2

Fig 3

Fig. 4

Rs comparison for different patterns

0 500 1000 1500 2000 2500 3000 3500

0.E+00 1.E+00 2.E+00 3.E+00 4.E+00 5.E+00 freq. [GHz]

Rs

R_conventional R_diamond R_circle R_triangle R_suspended

Ls comparison for different patterns

0.00E+00 1.00E+01 2.00E+01 3.00E+01 4.00E+01 5.00E+01 6.00E+01 7.00E+01

0.E+00 1.E+00 2.E+00 3.E+00 4.E+00 5.E+00 freq. [G H z]

Ls [nH]

L_conventional L_diamond L_circle L_triangle L_suspended

Fig. 5

Q comparison for different patterns

4 5 6 7

Q

Q_convential Q_diamond Q_circle Q_triangle Q_suspended

Types of Inductor

The Parameters in the Ashiby’s lump inductor model (@200Mhz)

Quality Factor and Frequencies in Measurement

Suspen ded Area (%)

Ls (nH)

Rs (Ù )

Cf (fF)

Cox1 (fF)

Cox2 (fF)

Rsub1 (Ù )

Rsub2 (Ù )

Csub1 (fF)

Csub2 (fF) Qmax

Freq @ Qmax (GHz)

fsr (GHz)

Q

@2.4G Hz conventional on-chip inductor

0 23.3 29 62.5 107 116 375 420 30 35 3.8 1.2 2.8 1

suspended inductor with diamond window pattern

18.8 23.3 29 50.6 86 93.9 386 431 30.8 36.5 4.3 1.2 3.2 1.6

suspended inductor with circle window pattern

43.5 23.3 29 38.6 66 71.7 391 448 32.6 37.4 4.8 1.6 3.6 2.7

suspended inductor with triangle window pattern

90.4 23.3 29 26.4 45 49 408 457 33.5 38.6 5.8 1.8 4.2 4.7

suspended inductor with pillar

98 23.3 29 15.6 27 29 423 472 35.2 40.7 6.6 2 4.8 6.1

Table 1