極薄閘極金氧半元件的基極電流的模擬研究
Study on Substrate Current of Ultra-Thin Gate MOSFETs
計畫編號：NSC 90-2215-E-011-008 執行期限：90 年 08 月 01 日至 91 年 07 月 31 日
主持人：張勝良 執行機構及單位名稱 台灣科技大學
E-mail:sljjj@et.ntust.edu.tw
一、中文摘要
這個計畫的目標是發展一個次微米金氧半 場效電晶體的的電腦化有效基極電流模型 以包含量子透納和離子撞擊效應。而這個 模型應該能夠預測基極電流與汲極偏壓的 關係。在這個超薄閘氧化層金氧半場效電 晶體，閘極透納電流造成的基極電流是不 能夠被忽略的。它是由 N 型金氧半場效電 晶體的價電帶電子透納產生的一個基極電 流。 基極電流也能由通道載子撞擊游離過 程所產生。本論文同時考慮通道量子化，
量子透納和離子撞擊效應以模擬基極電 流。
關鍵詞：基極電流，離子撞擊，透納電流，
薄閘極，金氧半場效電晶體，模擬研究。
Abstract
It has been proved that electron tunneling current from the valence band (EVB)generates a substrate current in nMOS devices. It also noted that thesubstrate current can result from the channel carrier impact-ionization process. This paper is to develop a
computationally efficient substrate current model for both submicrometer and deep submicrometer MOSFETs with the QM tunneling and the impact-ionization effects, and the model is able to predict the
drain-bias dependence of substrate current.
Keywords: substrate current,
impact-ionization, tunneling current, thin-gate MOSFET,
model
二、緣由與目的
During the past decades, ULSI technology has made great progress driven by the downsizing of its components such as MOSFETs. The gate oxide thickness has shrunk from l00nm in 1970 to 7.0nm in 1999 the product level and s expected to reach l.5nm in the year of 2010, the channel length is approximately in the
0.1um level. With this ultra-thin gate oxide, the impact of gate tunneling current on device
substrate current can no longer be ignored[1]. Recently Lee and Hu[2]
proposed a tunneling current model, which can predict all the significant tunneling current components:
electron tunneling from the conduction band (ECB), electron tunneling current from the valence band (EVB), and hole tunneling the valence band (HVB). EVB generates a substrate current (Isub) in nMOS devices. It is claimed that Isub has profound impacts on the floating body effects of SOI devices. This model can not be used to describe the
drain-bias dependence of substrate current, therefore it is difficult to predict the tunneling-caused
substrate current will have an impact on the performance of SOI MOSFETs.
For short-channel MOSFETs, an accurate nonlocal substrate current model for submicron and deep sumicron MOSFET
devices has been presented [2] , this substrate current results from the channel carrier impact-ionization process. The model is valid for the whole operation region, it is based on a complete drain current model and using the non-local impact-ionization coefficient. It is important for us to see a well-developed substrate current model which include both the tunneling-induced and impact-ionization-induced effects.
However this has not been done in open literatures. The experimental data by Momose et al.,[3] shows that in ultra-thin gate oxide MOSFETs the hot-carrier induced substrate current could be more significant than tunneling-induced component. From the above discussion we are required to study more specifically the bias-dependence of substrate current in order to advance our knowledge on the substrate current of ultra-thin gate MOSFETs.
A general trend of integrated circuit technology development has been moving toward reducing channel length and gate oxide thickness. The combination of thin gate dielectrics and high levels of channel doping in deep submicron OSFETs has been used to suppress the short-channel effect and to improve device performance, and results in large transverse electric fields at the Si/SiO2 interface. This leads to quantum mechanical (QM) effects in the inversion layer which alter the electrical characteristics of devices compared to the predictions of classical theory [4,5]. The quantization results in a decreased inversion layer charge density at a given gate voltage as compared to classical calculations without QM effects, this increases the magnitude f threshold voltage. Therefore, it is important in deep submicron MOSFET modeling to account for the QM effect, especially at the anticipated
lower power supply voltages where threshold voltage design. The two-dimensional (2-D) nature of electrons in inversion layers has been studied in detail by a number of researchers[6,7] by solving Schrodinger's and Poisson's equations
self-consistently. A full QM treatment is difficult and is hardly ever necessary for silicon MOSFETs. The MOSFET modeling with the QM effect poses a challenge to the device engineer, however, there is a pressing need for the development of MOSFET models to include this effect.
The goal of this project is to develop a computationally efficient substrate current model for both submicrometer and deep submicrometer MOSFETs with the QM tunneling and the impact-ionization effects. And the model should be able to predict the drain-bias dependence.
三. 研究方法及成果
Figure 1 shows the energy band diagram of a
gate-insulator-semiconductor structure. Eg is the silicon energy-band gap. Evm is the energy below the valence band edge of the silicon valence-band electrons, above which
valence band electrons participate tunneling. From Si/SiO2/Si MIM structure, we can
get Vox= Eox tox=Eg+Evm, where Eox=(Vgb-Vms-Psidep0-Vcs)/tox.
The newly-derived tunneling gate current equation is shown in Appendix.
Fig. 2 shows the calculated gate current and substrate current of a MOSFET with L=0.45um and tox=100nm.
The substrate current is due to the impact-ionization process. The gate current is contributed by the
conduction band electron. Fig.
3(a) shows the calculated gate current of a MOSFET with L=0.15um and tox=35nm, it is contributed by the conduction band and valence-band electrons.
The VBE tunneling occurs at a larger gate bias. Fig. 3(b) shows the calculated gate
and substrate currents of a MOSFET with L=0.25um and tox=35nm. We can see at low gate bias the substrate current is contributed by impact-ionization effect and at high gate bias it is due to the VBE tunneling induced hole current.
四、結果與討論
In this project we have developed a new substrate current model for ultrathin gate dielectric MOSFETs, this model can describe quanlitatively the gate current, and it predicts a new phenomena about substrate current, at low gate bias the substrate current is contributed by impact ionization
process and at higher gate bias it is due to the valence-band electron tunneling effect.
五、圖表
Fig. 1
五、參考文獻
[l] W.-C. Lee and C. Hu. "Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling." In Proc. Symp. VLSI Technology Dig.Tech.
Papers. W.-C. Lee. Ed.. BerkeleyCA. June 2000, pp.198-199.
[2 M.-C. Hu and S.-L. Jang, " A complete substrate current model for submicron and deep submicron MOSFETs," Int. J.
Electronics. Vol. 83, pp.159-l76, 1997.
[3] H. S. Momose et al., "Hot-carrier
reliability of ultra-thin gate oxide CMOS, Solid-State Electron., vol. 44, p. p.2035, 2000.
[4]S. A. Hareland, S. Krishnamurthy, S.
Jallepalli, C.-F. Yeap. K.Hasnat, A. F. Tasch Jr., andC. M. Maziar. "A computationally efficient model for inversion layer quantization effects in deep submicron N-channel MOSFET's," lEEETrans. Electron Devices, vol. 43. pp. 90-96. Jan. 1996.
[5] S. A. Hareland, S. Jallepalli, G.
Chindalore, W.-K. Shih, A. F. Tasch, Jr., andC. M. Maziar, "A simple model for quantum mechanical effects in hole inversion layers in silicon pMOS," IEEE Trans.
Electron Devices, vol. 44, pp.l17-1173, July l997.
[6] T. Ando, and A. B. Fowler and F. Stern, "
Electronic properties of two-dimensional systems," Rev. Modern Phys. vol. 54, No. 2, pp. 437-672, 1982.
[7] A. Shanware, J. P. Shiely, and H. Z.
Massoud ,”Extraction of the gate oxide
thickness of N- and P-Channel MOSFETs below 20A from the substrate current
resulting from valence-band electron tunneling,” IEDM99-815.
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行政院國家科學委員會補助專題研究計畫成果報告
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極薄閘極金氧半元件的基極電流的模擬研究※
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計畫類別：□個別型計畫 □整合型計畫 計畫編號： NSC 90-2215-E-011-008
執行期間： 90 年 08 月 01 日至 91 年 07 月 31 日
計畫主持人：張勝良 共同主持人：
計畫參與人員：
本成果報告包括以下應繳交之附件：
□赴國外出差或研習心得報告一份
□赴大陸地區出差或研習心得報告一份
□出席國際學術會議心得報告及發表之論文各一份
□國際合作研究計畫國外研究報告書一份
執行單位：台灣科技大學
中 華 民 國 91 年 10 月 30 日
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