[PDF] Top 20 Initial-on ESD protection design with PMOS-triggered SCR device
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Initial-on ESD protection design with PMOS-triggered SCR device
... novel SCR design with “initial-on” function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective ... See full document
4
Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
... embedded pMOS transistor was bi- ased at VDD through the resistor in the ESD-transient detec- tion circuit during normal circuit operation ...of SCR devices must be de- signed greater than the ... See full document
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Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
... age SCR [8], SCR with stacked diode string [6], stacked SCR devices [9], high-current-triggered SCR devices [10], and high- holding low-voltage trigger SCR ...an ... See full document
7
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
... applications on the O/P during the normal circuit operating ...mistriggering on the LDNMOS, even if a 10% overshooting voltage happens to the ...gate-driven ESD protection circuit can be ... See full document
10
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
... VLSI Design Department of Computer and Communication Research Labora- tories (CCL), Industrial Technology Research Insti- tute (ITRI), Taiwan, as a Circuit Design ...VLSI Design Division of ... See full document
13
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
... DT_SCR device used for on-chip ESD protection cir- cuits has been successfully investigated in a ...process. With both the substrate and n-well triggered currents, the ... See full document
11
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
... ESD protection devices cause RF performance degradation with several undesired effects [13], ...the ESD protection device is one of the most important design ... See full document
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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
... input pMOS and nMOS devices are shown in ...PS-mode ESD stress with silicide blocking on pMOS and nMOS devices is 3 A, and that without silicide blocking is 2 ...embedded SCR ... See full document
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Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
... STSCR device used for on-chip ESD protection cir- cuits has been successfully investigated in a ...STSCR device has the advantages of controllable switching voltage ...high ESD ... See full document
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SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
... TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, ...STSCR with (b) STI and (c) dummy-gate structures under different substrate-triggered ...turn on this STSCR device during ... See full document
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Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme
... new ESD protection scheme for differential input pads has been proposed and successfully verified in 130-nm CMOS process to protect the differential ...proposed ESD protection scheme ... See full document
8
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
... buffers with or without the proposed substrate-triggered ...stacked-nMOS device is not triggered by such a voltage pulse. On the contrary, when such a 0–8-V voltage pulse is applied to ... See full document
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Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
... NANSCR WITH FASTER TURN-ON SPEED FOR ESD PROTECTION IN A ...be triggered on in time. Once the NANSCR and LVTSCR are turned on, the HBM and MM-ESD-stressed energies ... See full document
12
SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
... The device cross-sectional view of DHVSCR is shown in Fig. 1(b), where a pMOS PM2 and an nMOS NM2 are inserted into the SCR de- vice ...Compared with the traditional pMOS-LVTSCR struc- ... See full document
3
Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
... of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process Chun-Yu Lin, Member, IEEE, and Mei-Lian Fan Abstract—The pin-to-pin electrostatic discharge (ESD) ... See full document
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A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
... Based upon the understanding of CMOS transient latch-up [lo]-[ 131, the low trigger voltage can be achieved through the proper design of device capaci- tances within [r] ... See full document
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On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
... of ESD current involves both avalanche breakdown and turn-on of the parasitic lateral bipolar ...depends on the relative proximity to the avalanching ...bipolar device is acted as “seed ... See full document
8
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
... CDM ESD protection design with GGNMOS can not provide efficient protection in nanoscale CMOS IC products, because the CDM ESD clamp realized with GGNMOS is triggered ... See full document
4
Design on ESD protection scheme for IC with power-down-mode operation
... chip with the traditional ESD protection scheme and the new proposed ESD protection scheme have been fabricated in a ...proposed ESD protection ...input ESD ... See full document
5
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
... used with an SCR-based ESD protection device determines the magnitude of the voltage overshoot that occurs before the SCR fully turns ...the SCR, must be poly-bound to ... See full document
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