Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

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Design of differential low-noise ampliﬁer with cross-coupled-SCR ESD

protection scheme

Chun-Yu Lin

a,*

_{, Ming-Dou Ker}

a,b

_{, Yuan-Wen Hsiao}

a

Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan

b

Department of Electronic Engineering, I-Shou University, Kaohsiung, Taiwan

a r t i c l e

i n f o

Article history:

Received 7 December 2009

Received in revised form 9 February 2010 Available online 7 April 2010

a b s t r a c t

The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD pro-tection scheme was modified from the conventional double-diode ESD propro-tection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other dif-ferential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.

1. Introduction

Electrostatic discharge (ESD) is getting more attention in nano-scale CMOS technology, because it has become one of the most important reliability issues in IC chips[1–4]. With the evolution of CMOS technology, ESD protection design in nanoscale CMOS process becomes more challenging, because the upper bound of the ESD protection design window for an input pad, which is set by the gate-oxide breakdown voltage, is lowered. To achieve satis-factory ESD robustness without seriously degrading circuit perfor-mance, ESD protection design should be taken into consideration during the design phase of all integrated circuits, especially radio-frequency (RF) circuits [5]. Since the low-noise ampliﬁer (LNA) is usually connected to the external of the RF receiver chip such as the off-chip antenna, on-chip ESD protection circuits are needed for all input pads of the LNA.

In the ESD-test standards, there are several ESD-test pin combi-nations. Besides the positive-to-VDD (PD-mode), positive-to-VSS (PS-mode), negative-to-VDD (ND-mode), and negative-to-VSS (NS-mode) ESD tests, the pin-to-pin ESD test is also speciﬁed to evaluate ESD robustness of the differential input pads. Under the pin-to-pin ESD test, one input pad is stressed with the other input pad relatively grounded, while all the other pads including all VDD

and VSS pads are ﬂoating[6]. To provide efﬁcient pin-to-pin ESD protection, the ESD protection device should be turned on quickly with low enough clamping voltage and low enough turn-on resis-tance under ESD stresses to effectively protect the thin gate oxides of MOS transistors in the differential input stage. As the gate-oxide thickness becomes much thinner in nanoscale CMOS processes, ro-bust ESD protection design against all ESD-test pin combinations, especially pin-to-pin ESD tests, becomes more challenging.

There are several ESD protection designs reported for RF front-end circuits to optimize RF performance and ESD robustness[7– 13]. Since the pin-to-pin ESD stress was one of the most critical ESD events for differential input pads, some ESD protection designs have been presented to improve ESD robustness of LNA under pin-to-pin ESD stresses[14]. In this paper, a new ESD protection design realized with cross-coupled silicon-controlled rectifier (SCR) is proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme is modified from the conventional dou-ble-diode ESD protection scheme without adding any extra device. Verified in a 130-nm CMOS process, the new proposed ESD protec-tion scheme exhibited high ESD robustness, especially high pin-to-pin ESD robustness.

2. Differential LNA design

In LNA design, differential conﬁguration is popular because the differential LNA has the advantages of better common-mode noise

* Corresponding author. Tel.: +886 3 5131573; fax: +886 3 5715412. E-mail addresses:[email protected](C.-Y. Lin),[email protected](M.-D. Ker).

Microelectronics Reliability 50 (2010) 831–838

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Microelectronics Reliability

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rejection, as well as less sensitivity to substrate noise, supply noise, and bondwire inductance variation [15–21]. In addition, the differential output signals of the differential LNA can be directly connected to the differential inputs of the double balanced mixer. In this study, the circuit schematic of the LNA without ESD pro-tection for comparison reference is shown inFig. 1. The architec-ture of common-source with inductive degeneration is applied to match the input impedance of LNA to the source impedance (50X) at the operating frequency of 5 GHz. Good isolation be-tween the input and output can be enhanced by using the cascode conﬁguration. Moreover, the cascode conﬁguration reduces Miller effect and provides good stability[22]. The dimensions of the input NMOS transistors M1and M3are designed according to the

com-promise between noise ﬁgure and power consumption. Since the small-signal operation of the differential LNA is symmetrical, the

half circuit can be referred to analyze the LNA. The input imped-ance (Zin) of the RF IN1pad can be calculated as

Zin¼

1 j

x

ðCgs1þ CG1Þ

þ j

x

ðLG1þ LS1Þ þ

x

TLS1 ð1Þ where Cgs1is the gate-source capacitance of M1, CG1is the added

capacitance between the gate and source terminals of M1, LG1 is

the gate inductance, and LS1is the source inductance. The

x

Tis

the unity-gain angular frequency of M1, which can be expressed as

x

T¼

gm1

Cgs1

ð2Þ

where gm1is the transconductance of M1. With the input matching

network resonating at the operating frequency, the input imped-ance (Zin_Resonance) is purely real and can be given by

Fig. 1. Differential LNA without ESD protection for comparison reference.

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Zin Resonance¼

x

TLS1¼

gm1

Cgs1

LS1 ð3Þ

To match the input impedance at resonance to the source impedance, LS1is determined once the size of M1has been chosen.

The resonance angular frequency (

x

0), which is designed to be the

operating frequency, can be obtained by

1

x

0ðCgs1þ CG1Þ

¼

x

0ðLG1þ LS1Þ ð4Þ At resonance, the source inductor LS1and gate inductor LG1

com-pensate the capacitance at the gate terminal of M1. After LS1is

determined to match the source impedance, the remaining capac-itive impedance needs to be cancelled by LG1. However, the small

Cgs1 leads to intolerable large LG1. Therefore, an extra capacitor

CG1is added in parallel with Cgs1to reduce the required inductance

of LG1. The drain inductor LD1and drain capacitor CD1form the

out-put matching network to match the outout-put impedance of LNA to 50X.

The gate voltages of M2and M4are biased to VDD through the

resistor R1. The capacitor C1acts as a decoupling capacitor. LTANK

and CTANKform a LC-tank to enhance the common-mode rejection.

With the deep N-well structure, the P-well (bulk) region of each NMOS transistor can be fully isolated from the common P-sub-strate, so the source and bulk terminals are connected together to eliminate the body effect. All of the inductors are the on-chip spiral inductors implemented by the top metal layer, and all of the capacitors in the differential LNA are realized by the metal– insulator–metal (MIM) capacitors. The aforementioned active and passive devices are fully integrated in the experimental test chip in a 130-nm CMOS process. In order to verify the effectiveness of the on-chip ESD protection circuits at the input pads, the ac cou-pling capacitor between the input pad and LG1(LG2) is not realized

in the test chip, because the ac coupling capacitor connected to the input pad can block some ESD energy when the input pad is stressed by ESD. Thus, the off-chip bias tee is needed to combine the RF input signal and the dc bias at the input node during RF measurement.

3. ESD protection design on differential LNA 3.1. Conventional double-diode ESD protection scheme

The conventional double-diode ESD protection scheme is shown inFig. 2. A P+/N-well diode (DP) is connected between each input

pad and VDD, while an N+/P-well diode (DN) is connected between

each input pad and VSS. Besides, the power-rail ESD clamp circuit is used to provide ESD current paths between VDD and VSS under ESD stresses.

3.2. New proposed cross-coupled-SCR ESD protection scheme The four ESD protection diodes at the differential input pads in the conventional double-diode ESD protection scheme, which in-clude two P+/N-well diodes (DP) and two N+/P-well diodes (DN),

are reserved in the new proposed design, but the placement is changed.Fig. 3illustrates the concept of the proposed ESD protec-tion scheme. In this new proposed ESD protecprotec-tion design, the SCR path is established directly from one differential input pad to the other differential input pad without adding any extra device. The SCR path has very high ESD robustness due to its low clamping voltage under ESD stress conditions[23]. As illustrated inFig. 3a, by merging DP1(P+/N-well diode for RF IN1pad) and DN2

(N+/P-well diode for RF IN2pad) together, an SCR path from RF IN1pad

to RF IN2 pad can be established for pin-to-pin ESD protection

without adding any extra device. Similarly, DP2(P+/N-well diode

for RF IN2pad) and DN1(N+/P-well diode for RF IN1pad) can be

merged together to form another SCR path from RF IN2pad to RF

IN1pad, as illustrated inFig. 3b. Since the pin-to-pin ESD path is

established by SCR, the cross-coupled-SCR ESD protection scheme is expected to have high pin-to-pin ESD robustness. Under PD-PS-, ND-, and NS-mode ESD stresses, the ESD levels are not altered, since DP1, DN1, DP2, and DN2still exist.

Fig. 3. Establishing the SCR paths between the differential input pads by combining (a) DP1(P+/N-well diode for RF IN1pad) with DN2(N+/P-well diode for RF IN2pad),

and (b) DP2(P+/N-well diode for RF IN2pad) with DN1(N+/P-well diode for RF IN1

pad).

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Fig. 4shows the circuit schematic of the differential LNA with the new proposed ESD protection scheme of cross-coupled SCR. SCR1 is placed close to the RF IN1 pad to provide efﬁcient

pin-to-pin ESD current path from the RF IN1 pad to the RF IN2

pad. Similarly, SCR2is placed close to the RF IN2pad to provide

efﬁ-cient ESD current path from the RF IN2pad to the RF IN1pad under

pin-to-pin ESD stresses. To reduce the trigger voltage and increase

Fig. 4. Differential LNA with proposed ESD protection scheme of cross-coupled SCR.

Fig. 5. Cross-sectional view and equivalent circuit of SCR.

Fig. 6. Power-rail ESD clamp circuit realized with SCR.

Fig. 7. Chip micrograph of differential LNA with proposed cross-coupled-SCR ESD protection scheme.

Fig. 8. Measured S11-parameters of differential LNA with the proposed

cross-coupled-SCR ESD protection scheme, and the original differential LNA without ESD protection.

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the turn-on speed of the SCR under ESD stresses, the substrate-triggered technique is used[23]. As shown inFigs. 4 and 5, the P + trigger diffusion is added in the P-well region, and is connected to the ESD detection circuit in the power-rail ESD clamp circuit. In the proposed ESD protection scheme, the PS-mode ESD current path for the RF IN1(RF IN2) pad is provided by DP1(DP2) embedded

in SCR1(SCR2) and the power-rail ESD clamp circuit. The ND-mode

ESD current path for the RF IN1 (RF IN2) pad is provided by the

power-rail ESD clamp circuit and DN1 (DN2) embedded in SCR2

(SCR1). Under pin-to-pin ESD stresses, the ESD current paths

be-tween the differential input pads are provided by the cross-cou-pled SCR1and SCR2.

The total parasitic capacitance from the cross-coupled SCR at each input pad is speciﬁed as 300 fF, which is the same as that of the double-diode ESD protection scheme in [14]. To achieve the total parasitic capacitance of 300 fF at each differential input pad, the sizes of SCR1and SCR2are all drawn as 60

l

m 2.4

l

m. The

source inductors (LS1and LS2) and gate inductors (LG1and LG2) are

adjusted to achieve the input matching of LNA with the cross-coupled SCR.

3.3. Power-rail ESD clamp circuit

Fig. 6shows the power-rail ESD clamp circuit used in this work, where the substrate-triggered SCR is used as the ESD clamp device. The cross-sectional view and equivalent circuit of this SCR is sim-ilar to that inFig. 5. The ESD detection circuit consists of an RC timer and an inverter. The resistor R2and capacitor C2 form the

RC timer with the time constant of 0.3

l

s, which can distinguish the ESD transients from the normal circuit operating conditions [24]. Under normal circuit operating conditions, the node between R2and C2is charged to high potential (VDD). Since NMOS MNis

turned on and PMOS MPis turned off, the trigger node of the SCR

is tied to VSS and no trigger current is injected to the trigger node of SCR. Thus, the SCR is kept off under normal circuit operating conditions. Under ESD stresses, the ESD voltage at VDD has the rise time in the order of nanosecond. With the RC delay provided by R2

and C2, the gate voltages of MPand MNare initially kept at low

po-tential (0 V). Therefore, MPis turned onto inject trigger current

into the trigger node. As a result, the SCR is turned onto provide ESD current path from VDD to VSS. Since the power-rail ESD clamp circuit is placed between VDD and VSS, it does not contribute any parasitic effects to neither input nor output pads. Besides, the ESD detection circuit in the power-rail ESD clamp circuit can also serve

as the trigger circuit for the cross-coupled SCR devices between the differential input pads.

4. Experimental results 4.1. RF performances

The differential LNA circuits have been fabricated in 130-nm CMOS process. The chip micrograph of the differential LNA with cross-coupled-SCR ESD protection scheme is shown in Fig. 7. To measure the S-parameters of the differential LNA, four-port S-parameter measurement with Agilent E8361A network analyzer is performed. The measurement system converted the measured four-port S-parameters to the differential two-port S-parameters. The measured RF performance of the differential LNA with cross-coupled-SCR ESD protection scheme is compared with that of the original differential LNA without ESD protection inFigs. 8–11. To compare the input matching conditions, the measured S11

-parame-ters of these two differential LNAs are shown inFig. 8. It is observed that the operating frequency of the differential LNA with cross-cou-pled-SCR ESD protection scheme is shifted from 5 GHz to 4.8 GHz. At 4.8-GHz, the measured S11-parameter is 26.3 dB. The shift in

the operating frequency is due to the lack of RF model for SCR

Fig. 11. Measured noise ﬁgures of differential LNA with the proposed cross-coupled-SCR ESD protection scheme, and the original differential LNA without ESD protection.

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device in the given CMOS process. The macro model of SCR was ever reported to simulate its turn-on mechanism during ESD stress [25,26]; however, the small-signal model of SCR in RF circuit operation condition is still scarce. To more precisely simulate the differential LNA with the cross-coupled-SCR ESD protection scheme, the parasitic effects of the SCR can be modeled by the diodes with P+/N-well, P-well/N-well, and N+/P-well junctions, rather than only the 300-fF capacitance.

Fig. 9compares the measured power gains (S21-parameters) of

these two differential LNAs. At 4.8 GHz, the S21-parameter of

differ-ential LNA with cross-coupled-SCR ESD protection scheme is 17.2 dB. The measured S22-parameters of these two differential

LNAs are compared in Fig. 10. The S22-parameter of differential

LNA with cross-coupled-SCR ESD protection scheme is 8 dB at 4.8 GHz. Satisfactory reverse isolation is also achieved in differen-tial LNA with cross-coupled-SCR ESD protection scheme, where the S12-parameter is lower than 26 dB at 4.8 GHz.Fig. 11shows the

measured noise figures of these two differential LNAs. At 4.8 GHz, the noise figure of differential LNA with cross-coupled-SCR ESD protection scheme is 3.58 dB. The increase in the noise fig-ure is attributed to the parasitic effects of ESD protection devices with the overlapped wide metal lines in layout, which are con-nected between the differential input pads and the cross-coupled SCR devices.

4.2. ESD robustness

The human-body-model (HBM)[27]and machine-model (MM) [28]ESD levels are also measured from the differential LNAs. The failure criterion is 30% voltage shift under 1-

l

A current bias. Dur-ing ESD tests, the off-chip bias tee is not included. The measured HBM and MM ESD levels of the LNA circuits are listed inTable 1. The LNA without ESD protection is very vulnerable to ESD, because it fails at 50-V HBM and 10-V MM ESD tests. The differential LNA with cross-coupled-SCR ESD protection scheme can pass 3.5-kV-HBM and 300-V-MM PS-mode and ND-mode ESD tests. Moreover, the differential LNA with cross-coupled-SCR ESD protection scheme can sustain pin-to-pin ESD stresses of over 8-kV HBM and 800-V MM.

Table 2summarizes the measured performances of the original differential LNA without ESD protection and the differential LNA with the new proposed cross-coupled-SCR ESD protection scheme, and compares their performances to those of the prior CMOS dif-ferential LNA circuits. The proposed ESD-protected difdif-ferential LNA in this work exhibits excellent ESD robustness as compared with the other differential LNA circuits, especially in the pin-to-pin ESD stress.

4.3. Latchup immunity

Using SCR as the ESD protection device could introduce latchup concern. To avoid latchup issue, the holding voltage of SCR must be higher than the power-supply voltage, which is 1.2 V in this work. The dc I–V characteristics of the stand-alone SCR used in this de-sign are measured by Tektronics 370B curve tracer. As shown in Fig. 12, the curves with square, circular, and triangular symbols indicate the I–V characteristics of the stand-alone SCR without trig-ger circuit under 25, 85, and 125 °C, respectively. The holding volt-ages of the stand-alone SCR under 25, 85, and 125 °C are 2.84, 2.58, and 2.38 V, respectively. With the holding voltage higher than the power-supply voltage (1.2 V), the SCR can be safely used in this RF chip without latchup issue.

4.4. Discussion on pin-to-pin ESD current paths

Under pin-to-pin ESD stresses, there are two ESD current paths exist in the cross-coupled-SCR ESD protection scheme. One ESD current path in the cross-coupled-SCR ESD protection scheme is shown inFig. 13a, which is similar to that in the conventional dou-ble-diode ESD protection scheme. The voltage drop (VPin-to-Pin1)

along this pin-to-pin ESD current path is

Table 2

Comparison on ESD robustness among CMOS differential LNAS.

Technology f0(GHz) VDD (V) PDC(mW) NF (dB) S21(dB) S11(dB) HBM ESD level (kV) MM ESD level (V)

Original LNA (this work) 0.13-lm CMOS 5 1.2 10.3 2.16 16.2 27.2 <0.05 <10 ESD-protected LNA (this work) 0.13-lm CMOS 4.8 1.2 10.3 3.58 17.2 26.3 3.5 300 Ref.[14](double-diode-protected LNA) 0.13-lm CMOS 5 1.2 10.3 2.43 17.9 18.7 2.5 200

Ref.[15] 90-nm CMOS 0.2–3.2 1.2 25 1.76 15.5 10 2.4 N/A

Ref.[16] 0.13-lm CMOS 18 1.5 36 4.1 22.4 7 2 N/A

Ref.[17] 0.18-lm CMOS 6 1.8 6.48 3 7.1 10 N/A N/A

Ref.[18] 0.13-lm CMOS 3–5 1.5 45 4 25.8 11 1.5 N/A

Ref.[19] 0.18-lm CMOS 5.8 1.8 14.4 3.7 12.5 15 N/A N/A

Ref.[20] 0.13-lm CMOS 2–4.6 1.5 16.5 3.5 9.5 10 N/A N/A

Ref.[21] 0.18-lm CMOS 5.75 1 16 0.9 14.2 N/A N/A N/A

Table 1

HBM and MM ESD robustness under different test pin combinations. ESD robustness Original LNA ESD-protected LNA

HBM MM (V) HBM (kV) MM (V) Positive to VSS <50 V <10 3.5 300 Positive to VDD <50 V <10 6 550 Negative to VSS <50 V <10 6 550 Negative to VDD <50 V <10 3.5 350 Pin to Pin <50 V <10 >8 800 VDD to Vss 0.5 kV <10 >8 >1000

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VPin-to-Pin1¼ VDP1þ VVDD Busþ VSCR3þ VVSS Busþ VDN2 ð5Þ where VDP1, VVDD_Bus, VSCR3, VVSS_Bus, and VDN2are the voltage drops

across DP1 embedded in SCR1, VDD bus, SCR3, VSS bus, and DN2

embedded in SCR1, respectively. The other ESD current path in the

cross-coupled-SCR ESD protection scheme under pin-to-pin ESD stresses is shown inFig. 13b. The voltage drop (VPin-to-Pin2) along

the pin-to-pin ESD current path is

VPin-to-Pin2¼ VSCR1þ VSCR1IN2 ð6Þ

where VSCR1 and VSCR1-IN2 are the voltage drops across SCR1

and the metal line between SCR1 and the RF IN2 pad,

respectively. As compared with (5), the voltage drop along the pin-to-pin ESD current path is substantially reduced.

Moreover, the SCR paths between RFIN1 and RFIN2 may

directly turn-on during ESD stress events. Thus, the pin-to-pin ESD robustness is signiﬁcantly improved in differential LNA

with the new proposed cross-coupled-SCR ESD protection

scheme.

Fig. 13. ESD current paths through (a) diodes and power-rail ESD clamp circuit, and (b) SCR, in differential LNA with the proposed cross-coupled-SCR ESD protection scheme under pin-to-pin ESD stresses.

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5. Conclusion

A new ESD protection scheme for differential input pads has been proposed and successfully veriﬁed in 130-nm CMOS process to protect the differential LNA. The proposed ESD protection scheme with the cross-coupled SCR is realized without adding any extra device, as compared with the conventional double-diode ESD protection scheme. Besides, the cross-coupled-SCR ESD pro-tection scheme can signiﬁcantly reduce the voltage drop along the ESD current path under the to-pin ESD test, so the pin-to-pin ESD robustness can be improved. With the evolution of CMOS technology, the gate-oxide breakdown voltage becomes lower, which indicates that reducing the voltage drop along the ESD current path becomes more important for ESD protection de-sign in advanced nanoscale CMOS processes. To achieve good RF performance and high ESD robustness simultaneously, the pro-posed ESD protection scheme in this work can be well co-designed with the differential LNA.

Acknowledgments

The authors would like to thank Mr. T.-H. Tang and Mr. C.-T. Wang of United Microelectronics Corporation, Taiwan, for their support on test chips fabrication. This work was partially sup-ported by ‘‘Aim for the Top University Plan” of the National Chi-ao-Tung University and Ministry of Education, Taiwan, ROC, and partially supported by National Science Council (NSC), Taiwan, un-der Contract of NSC98-2221-E-009-113-MY2.

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