本論文設計 X 頻帶接收器前端電路包含低雜訊放大器以及環形降頻器，使用 TSMC 180 nm CMOS 製程，E 頻帶低雜訊放大器則是使用 TSMC 90 nm CMOS 製 程，已完成所有電路之下線。
首先，第一個電路為 X 頻帶低雜訊放大器，設計採用兩級共源極組態串接的 架構，輸入採用源極退化電感以及串聯閘極電感來完成輸入雜訊匹配以及共軛匹 配，級間匹配網路與輸出匹配網路設計採用變壓器取代三個電感的匹配方式來達 成共軛匹配，量測結果 S 參數稍微往低頻飄移 1 GHz 左右，增益掉 4 dB 左右，
我們猜測為變壓器實際的電感值比模擬預期來的大，造成頻飄，且較大的電感值 的品質因素較差，損耗越大，因此增益不如預期。除此之外，本電路雜訊指數量 測與模擬十分接近，仍證明雜訊匹配網路是可行的，而變壓器匹配的確能減少晶 片面積的使用，且能夠在低功率消耗下有不錯的增益與雜訊指數表現。
接著，第二個電路為 E 頻帶低雜訊放大器，採用三級串接的架構，第一級採 用共源極組態來達到低雜訊指數，後面兩級採用疊接組態來提供足夠的增益，而 為了減少疊接組態的雜訊指數，在疊接組態的共源極組態與共閘極組態之間串聯 一個電感，能有效降低疊接組態的雜訊指數，輸入匹配採用薄膜傳輸線進行雜訊 匹配，級間匹配與輸出匹配使用變壓器來完成共軛匹配。量測結果在 S 參數部分 往低頻飄移了 5 GHz，雜訊指數也不如預期，由於此電路與前一顆電路同樣採用 變壓器的匹配方式，而本次設計的操作頻率非常高，變壓器的電感效應如果有稍 微變大，極可能造成電路有大幅度的頻率飄移，且同時造成輸入雜訊匹配點跑掉，
因此雜訊指數不如預期。而本電路為了減少疊接組的雜訊指數，使電感匹配的方 式，在模擬上也證明是可行的，以及使用變壓器匹配減少晶片面積的使用。
最後為 X 頻帶混頻器的設計，本次設計為降頻器，使用雙平衡式環形混頻器，
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並將混頻器核心電晶體偏壓在弱反轉區，能夠使混頻器操作在較低 LO 驅動功率 以及低功率消耗，並在輸出 IF 端加上緩衝放大器來提供轉換增益。量測結果 LO 功率在-8 dBm 有飽和轉換增益 1.75 dB，整體功率消耗為 2 mW，量測與模擬結 果蠻吻合的，並證明本次架構的選擇是可行的，能夠在低 LO 功率與低功率消耗 維持不錯的電路特性。
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參 考 文 獻
[1] P. Philippe, L. Praamsma, R. Breunisse, E. van der Heijden, F. Meng, S. Bardy, F.
Moreau, S. Wane and E. Thomas “A Low Power 9.75/10.6GHz Down-Converter IC in SiGe:C BiCMOS for Ku-Band Satellite LNBs “, IEEE BCTM, Oct. 2011, pp. 211-214.
[2] Ping-Yi Wang, Min-Chih Chou, Po-Cheng Su, Yin-Cheng Chang, Kai-Hsin Chuang, and Shawn S. H. Hsu, “A Fully Integrated Ku-Band Down-Converter Front-End For DBS Receivers,” IEEE MTT-S Int. Microw. Symp., Jun. 2014, pp. 1-6.
[3] SIVERSIMA, “FC1001E Series E-band Converters,” Datasheet Feb. 2011.
[4] SIVERSIMA, “mm-wave converter series for high capacity wireless transfer,”
http://www.siversima.com/products/millimeter-wave-converters/, 2011.
[5] B. Liu, J. Zhou, and J. Mao, “A fully integrated low voltage (0.5V) X-BAND CMOS low noise amplifier,” in Microwave and Optical Technology Letter-Wiley Online Library, Jan.
2011, pp. 17-20.
[6] K.-J. Sun, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors,” IEEE Trans. Microw.
Theory Tech., vol. 54, no. 4, pp. 1554-1560, Apr. 2006.
[7] K.-J. Sun, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor,” IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp.
1795–1798.
[8] E. Adabi and A.-M. Niknejad, “CMOS low noise amplifier with capacitive feedback matching,” IEEE Custom Integrated Circuits Conference, Sep. 2007, pp. 643-646.
[9] C.-L. Yang, T.-H. Hsieh and Y.-C. Chiang, “A novel self-biased low noise amplifier with current-reused technique for X band applications,” Asia-Pacific Microwave Conference, Dec. 2009, pp. 1667-1670.
130
[10] B. Afshar, A.-M. Niknejad, “X/Ku Band CMOS LNA design techniques,” IEEE Custom Integrated Circuits Conference, Sept. 2006, pp. 389-392.
[11] C. Doan, S. Emami, A. Niknejad, and R. Brodersen, “Millimeter-wave CMOS design,”
IEEE J. Solid-State Circuits, vol. 40, no. 1, pp.144–155, Jan. 2005.
[12] M. Fahimnia, M.R. Nezhad-Ahamadi, B. Bigarbegian, S. Safavi-Naieni, M.
Mohammad-Taheri, and Y. Wang, “A 77 GHz Low Noise Amplifier Using Low-Cost 0.13μm CMOS Technology,” Microsystems and Nanoelectronics Research Conference, Oct. 2009, pp. 73-75.
[13] C. Y. Wu and P. H. Chen, “A Low Power V-band Low Noise Amplifier Using 0.13-μm CMOS Technology”. IEEE International Conference on Electronics, Circuits and Systems, Dec. 2007, pp.1328 – 1331.
[14] Y. Natsukari, M. Fujishima, “36mW 63GHz CMOS differential low noise amplifier with 14GHz bandwidth,” IEEE VLSI Circuits, Jun. 2009, pp. 252 – 253.
[15] M. Fahimnia, S. Safavi-Naieni, M. Mohammad-Taheri, and Y. Wang, “A 77 GHz Controllable Gain Low Noise Amplifier,” Iranian Conference on Electrical Engineering, May 2010, pp. 96 – 99.
[16] T.-P. Wang and H. Wang, “A 71–80 GHz amplifier using 0.13-μm CMOS technology,”
IEEE Microw. Wireless Compon. Lett., vol. 17, no. 9, pp. 685-687, Sept. 2007.
[17] Y.-S. Jiang, Z.-M. Tsai, J.-H. Tsai, H.-T. Chen, and H. Wang, “A 86 to108 GHz amplifier in 90 nm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp.
124–126, Feb. 2008.
[18] Yo-Sheng Lin, Guan-Lin Lee, Chien-Chin Wang, and Chih-Chung Chen, “A 21.1 mW 6.2 dB NF 77~81 GHz CMOS Low-Noise Amplifier with 13.5±0.5 dB S21 and Excellent Input and Output Matching for Automotive Radars,” IEEE Radio and Wireless Symposium (RWS), Jan. 2014, pp.73-75.
[19] E. Cohen, S. Ravid, and D. Ritter, “A wideband gain-boosting 8mW LNA with 23dB
131
gain and 4dB NF in 65nm CMOS process for 60 GHz applications,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Jun. 2012, pp. 1–4.
[20] H.V. Le, H.T. Duong, C.M. Ta, A.T. Huynh, R.J. Evans, and E. Skafidas, “A 77 GHz CMOS low noise amplifier for automotive radar receiver,” IEEE Radio Frequency Integration Technology (RFIT), Nov. 2012, pp. 174–176.
[21] Hsieh-Hung Hsieh, Po-Yi Wu, Chewn-Pu Jou, Fu-Lung Hsueh, and Guo-Wei Huang,
“60GHz High-Gain Low-Noise Amplifiers with a Common-Gate Inductive Feedback in 65nm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Jun. 2011, pp. 1-4.
[22] W. H. Lin, Y. N. Jen, J. H. Tsai, H. C. Lu, and T. W. Huang, “V-band Fully-Integrated CMOS LNA and DAT PA for 60 GHz WPAN Applications,” European Microwave Conference (EuMC), Sept. 2010, pp. 284-287.
[23] W.-H. Lin, J.-H. Tsai, Y.-N. Jen, T.-W. Huang, and H. Wang, “A 0.7-V 60-GHz low-power LNA with forward body bias technique in 90 nm CMOS process,” European Microwave Conference (EuMC), Sept. 2009, pp. 393-396.
[24] C.-S Lin, P.-S. Wu, H.-Y. Chang, and H. Wang, “A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13um CMOS technology,” IEEE Microw. Wireless Compon.
Lett., vol. 16 , no. 5, pp. 293–295, May 2006.
[25] H.-W. Chung, H.-C. Kuo, and H.-R. Chuang, “A 1.5-V 6-1 -GHz Low LO-Power Broadband CMOS Folded-Mirror Mixer for UWB Radio,” Asia-Pacific Microwave Conference, Dec. 2007, pp. 1-4.
[26] M.-D. Tsai and H. Wang, “A 0.3-25-GHz uItra-wideband mixer using commercial 0.18-um CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 11, pp.
522–524, Nov. 2004.
[27] C.-H. Kuo, B.-H. Huang, C.-C. Kuo, K.-Y. Lin, and H. Wang, “A 10-35GHz Low Power Bulk-Driven Mixer Using 0.13μm CMOS Process,” IEEE Microwave and Wireless
132
Component Letters, vol. 18, no. 7, pp.455–457, Jun. 2008.
[28] F.-C. Chang, P.-C. Huang, S.-F. Chao, and H. Wang, “A low power folded mixer for UWB system applications in 0.18-um CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 5, pp. 367–369, May 2007.
[29] C. Kienmayer, M. Tiebout, W. Simburger, and A. L. Scholtz, “A Low power low-voltage NMOS bulk-mixer with 20 GHz bandwidth in 90nm CMOS,” IEEE Int. Symp. Circuits Syst., May 2004, vol. 4, pp. 385–388.
[30] Man-Long Her, Chun-Yuan Huang, Pao-Hsun Wu, “A Gilbert Mixer with High Gain for 18 GHz Application,” Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, July 2012, pp. 68-72.
[31] B. Johnson, “Thermal agitation of electricity in conductors,” Phys. Rev., vol. 32, pp.97-109, July. 1928.
[32] H. Nyquist, “Thermal agitation of electric charge in conductors,” Phys. Rev., vol. 32, pp.110-110, July. 1928.
[33] K. Chang, I. Bahl, and V. Nair, “RF and Microwave Circuit and Component Design for Wireless System,” A John Wiely & Sons, INC.2002.
[34] G. Gonzalez, Microwave Transistor Amplifier-Analysis and Design, 2nd Ed., Prentice Hall, Inc., 1984.
[35] B. Razavi, RF Microelectronics, Prentice-Hall, 1997.
[36] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
[37] I. Aoki, S.D. Kee, D.B. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J.
Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002.
[38] Kuo-Jung Sun, Zuo-Min Tsai, Kun-You Lin, and Huei Wang, “A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor,” IEEE MTT-S Int. Microw. Symp.
133
Dig., Jun. 2007, pp. 1795–1798.
[39] H. Samavati, H. R. Rategh, and T. -H. Lee, “A 5-GHz CMOS wireless LAN receiver front end,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765-772, May 2000.
[40] B.-J. Huang, K.-Y Lin, and H. Wang, “Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology,” IEEE Trans. Microw. Theory Tech., vol.57, no.12, pp. 3049-3059, Dec. 2009.
[41] P.-S. Wu, C.-H. Wang, T.-W. Huang, and H. Wang, “Compact and broad-band millimeter-wave monolithic transformer balanced mixer,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 11, pp. 3106–3114, Oct. 2005.
[42] 林晉申，毫米波頻率轉換電路之研究，國立臺灣大學電機資訊學院電信工程研究所 博士論文，民國 96 年。
[43] Jeng-Han Tsai, “Design of 40-108-GHz Low-Power and High-Speed CMOS Up-/Down-Conversion Ring Mixers for Multistandard MMW Radio Applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 3, March 2012.
[44] B. G. Perumana, R. Mukhopadhyay, S. Chakraborty, C.-H. Lee, and J. Laskar, “A low-power fully monolithic subthreshold CMOS receiver with integrated LO generation for 2.4 GHz wireless PAN applications,” IEEE J. Solid-State Circuits, vol. 43, no. 10, pp.
2229–2238, Oct. 2008.
[45] B. Razavi, Design of Analog CMOS Integrated Circuits. NewYork: McGraw-Hill, 2001, ch. 2, p. 27.
[46] D. M. Pozar, Microwave Engineering, 3rd Ed, John Wiley & Sons, Inc., 2005.
[47] 林益璋，V 頻帶 CMOS 低雜訊放大器設計與分析，國立臺灣師範大學應用電子科 技所碩士論文，民國 100 年。
[48] 林繼揚，應用於 77GHz 汽車防撞雷達系統之毫米波積體電路設計，國立臺灣師範 大學應用電子科技所碩士論文，民國 101 年。
[49] 葉景富，24-GHz CMOS 射頻前端晶片及毫米波電路之研究設計，國立成功大學電
134
腦與通信工程研究所碩士論文，民國 97 年。
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自傳
我是張瑞安，出生於台北市，家庭成員有父母親與姊姊。大學畢業於國立台 灣師範大學應用電子科技學系，在大學期間的專題課程選擇射頻積體電路設計的 領域，因此在研究所亦選擇相同領域繼續研究，研究所就讀國立台灣師範大學應 用電子所，在就讀期間才了解到大學期間對於射頻積體電路設計的所學不足，讓 我在研究所期間更努力學習，且在與指導教授、學長與同學的互相討論中學到很 多經驗與知識，對於未來不管是在生活或者工作上一定能有所幫助。
學術成就
[1] Jeng-Han Tsai, Ruei-An Chang, and Ji-Yang Lin, “A 69-81 GHz Power Amplifier Using 90nm CMOS Technology,” IEEE Silicon Monolithic Integrated Circuits in Rf Systems (SiRF), Jan. 2014, pp. 77-79.